1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "linkage_offsets.h"
27 #define dynarec_local ESYM(dynarec_local)
28 #define add_link ESYM(add_link)
29 #define new_recompile_block ESYM(new_recompile_block)
30 #define get_addr ESYM(get_addr)
31 #define get_addr_ht ESYM(get_addr_ht)
32 #define clean_blocks ESYM(clean_blocks)
33 #define gen_interupt ESYM(gen_interupt)
34 #define psxException ESYM(psxException)
35 #define execI ESYM(execI)
36 #define invalidate_addr ESYM(invalidate_addr)
42 .type dynarec_local, %object
43 .size dynarec_local, LO_dynarec_local_size
45 .space LO_dynarec_local_size
47 #define DRC_VAR_(name, vname, size_) \
48 vname = dynarec_local + LO_##name; \
50 .type vname, %object; \
53 #define DRC_VAR(name, size_) \
54 DRC_VAR_(name, ESYM(name), size_)
56 DRC_VAR(next_interupt, 4)
57 DRC_VAR(cycle_count, 4)
58 DRC_VAR(last_count, 4)
59 DRC_VAR(pending_exception, 4)
63 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
69 DRC_VAR(reg_cop0, 128)
70 DRC_VAR(reg_cop2d, 128)
71 DRC_VAR(reg_cop2c, 128)
75 @DRC_VAR(interrupt, 4)
76 @DRC_VAR(intCycle, 256)
82 DRC_VAR(zeromem_ptr, 4)
83 DRC_VAR(inv_code_start, 4)
84 DRC_VAR(inv_code_end, 4)
85 DRC_VAR(branch_target, 4)
86 DRC_VAR(scratch_buf_ptr, 4)
87 @DRC_VAR(align0, 12) /* unused/alignment */
89 DRC_VAR(restore_candidate, 512)
101 .word ESYM(jump_dirty)
103 .word ESYM(hash_table)
118 .macro load_varadr reg var
119 #if defined(__ARM_ARCH_7A__) && !defined(__PIC__)
120 movw \reg, #:lower16:\var
121 movt \reg, #:upper16:\var
122 #elif defined(__ARM_ARCH_7A__) && defined(__MACH__)
123 movw \reg, #:lower16:(\var-(1678f+8))
124 movt \reg, #:upper16:(\var-(1678f+8))
132 .macro load_varadr_ext reg var
133 #if defined(__ARM_ARCH_7A__) && defined(__MACH__) && defined(__PIC__)
134 movw \reg, #:lower16:(ptr_\var-(1678f+8))
135 movt \reg, #:upper16:(ptr_\var-(1678f+8))
139 load_varadr \reg \var
143 .macro mov_16 reg imm
144 #ifdef __ARM_ARCH_7A__
147 mov \reg, #(\imm & 0x00ff)
148 orr \reg, #(\imm & 0xff00)
152 .macro mov_24 reg imm
153 #ifdef __ARM_ARCH_7A__
154 movw \reg, #(\imm & 0xffff)
155 movt \reg, #(\imm >> 16)
157 mov \reg, #(\imm & 0x0000ff)
158 orr \reg, #(\imm & 0x00ff00)
159 orr \reg, #(\imm & 0xff0000)
163 .macro dyna_linker_main
164 /* r0 = virtual target address */
165 /* r1 = instruction to patch */
166 load_varadr_ext r3, jump_in
179 ldr r5, [r3, r2, lsl #2]
181 add r6, r1, r12, asr #6
196 moveq pc, r4 /* Stale i-cache */
198 b 1b /* jump_in may have dupes, continue search */
201 beq 3f /* r0 not in jump_in */
207 and r1, r7, #0xff000000
210 add r1, r1, r2, lsr #8
214 /* hash_table lookup */
216 load_varadr_ext r3, jump_dirty
217 eor r4, r0, r0, lsl #16
219 load_varadr_ext r6, hash_table
223 ldr r5, [r3, r2, lsl #2]
230 /* jump_dirty lookup */
240 /* hash_table insert */
252 FUNCTION(dyna_linker):
253 /* r0 = virtual target address */
254 /* r1 = instruction to patch */
259 bl new_recompile_block
267 .size dyna_linker, .-dyna_linker
269 FUNCTION(exec_pagefault):
270 /* r0 = instruction pointer */
271 /* r1 = fault address */
273 ldr r3, [fp, #LO_reg_cop0+48] /* Status */
275 ldr r4, [fp, #LO_reg_cop0+16] /* Context */
276 bic r6, r6, #0x0F800000
277 str r0, [fp, #LO_reg_cop0+56] /* EPC */
279 str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
281 str r3, [fp, #LO_reg_cop0+48] /* Status */
282 and r5, r6, r1, lsr #9
283 str r2, [fp, #LO_reg_cop0+52] /* Cause */
284 and r1, r1, r6, lsl #9
285 str r1, [fp, #LO_reg_cop0+40] /* EntryHi */
287 str r4, [fp, #LO_reg_cop0+16] /* Context */
291 .size exec_pagefault, .-exec_pagefault
293 /* Special dynamic linker for the case where a page fault
294 may occur in a branch delay slot */
295 FUNCTION(dyna_linker_ds):
296 /* r0 = virtual target address */
297 /* r1 = instruction to patch */
304 bl new_recompile_block
311 mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
314 .size dyna_linker_ds, .-dyna_linker_ds
318 FUNCTION(jump_vaddr_r0):
319 eor r2, r0, r0, lsl #16
321 .size jump_vaddr_r0, .-jump_vaddr_r0
322 FUNCTION(jump_vaddr_r1):
323 eor r2, r1, r1, lsl #16
326 .size jump_vaddr_r1, .-jump_vaddr_r1
327 FUNCTION(jump_vaddr_r2):
329 eor r2, r2, r2, lsl #16
331 .size jump_vaddr_r2, .-jump_vaddr_r2
332 FUNCTION(jump_vaddr_r3):
333 eor r2, r3, r3, lsl #16
336 .size jump_vaddr_r3, .-jump_vaddr_r3
337 FUNCTION(jump_vaddr_r4):
338 eor r2, r4, r4, lsl #16
341 .size jump_vaddr_r4, .-jump_vaddr_r4
342 FUNCTION(jump_vaddr_r5):
343 eor r2, r5, r5, lsl #16
346 .size jump_vaddr_r5, .-jump_vaddr_r5
347 FUNCTION(jump_vaddr_r6):
348 eor r2, r6, r6, lsl #16
351 .size jump_vaddr_r6, .-jump_vaddr_r6
352 FUNCTION(jump_vaddr_r8):
353 eor r2, r8, r8, lsl #16
356 .size jump_vaddr_r8, .-jump_vaddr_r8
357 FUNCTION(jump_vaddr_r9):
358 eor r2, r9, r9, lsl #16
361 .size jump_vaddr_r9, .-jump_vaddr_r9
362 FUNCTION(jump_vaddr_r10):
363 eor r2, r10, r10, lsl #16
366 .size jump_vaddr_r10, .-jump_vaddr_r10
367 FUNCTION(jump_vaddr_r12):
368 eor r2, r12, r12, lsl #16
371 .size jump_vaddr_r12, .-jump_vaddr_r12
372 FUNCTION(jump_vaddr_r7):
373 eor r2, r7, r7, lsl #16
375 .size jump_vaddr_r7, .-jump_vaddr_r7
376 FUNCTION(jump_vaddr):
377 load_varadr_ext r1, hash_table
379 and r2, r3, r2, lsr #12
386 str r10, [fp, #LO_cycle_count]
388 ldr r10, [fp, #LO_cycle_count]
390 .size jump_vaddr, .-jump_vaddr
394 FUNCTION(verify_code_ds):
395 str r8, [fp, #LO_branch_target]
396 FUNCTION(verify_code_vm):
397 FUNCTION(verify_code):
425 ldr r8, [fp, #LO_branch_target]
430 .size verify_code, .-verify_code
431 .size verify_code_vm, .-verify_code_vm
434 FUNCTION(cc_interrupt):
435 ldr r0, [fp, #LO_last_count]
439 str r1, [fp, #LO_pending_exception]
440 and r2, r2, r10, lsr #17
441 add r3, fp, #LO_restore_candidate
442 str r10, [fp, #LO_cycle] /* PCSX cycles */
443 @@ str r10, [fp, #LO_reg_cop0+36] /* Count */
451 ldr r10, [fp, #LO_cycle]
452 ldr r0, [fp, #LO_next_interupt]
453 ldr r1, [fp, #LO_pending_exception]
454 ldr r2, [fp, #LO_stop]
455 str r0, [fp, #LO_last_count]
458 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
462 ldr r0, [fp, #LO_pcaddr]
466 /* Move 'dirty' blocks to the 'clean' list */
477 .size cc_interrupt, .-cc_interrupt
480 FUNCTION(do_interrupt):
481 ldr r0, [fp, #LO_pcaddr]
485 .size do_interrupt, .-do_interrupt
488 FUNCTION(fp_exception):
491 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
493 str r0, [fp, #LO_reg_cop0+56] /* EPC */
496 str r1, [fp, #LO_reg_cop0+48] /* Status */
497 str r2, [fp, #LO_reg_cop0+52] /* Cause */
501 .size fp_exception, .-fp_exception
503 FUNCTION(fp_exception_ds):
504 mov r2, #0x90000000 /* Set high bit if delay slot */
506 .size fp_exception_ds, .-fp_exception_ds
509 FUNCTION(jump_syscall):
510 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
512 str r0, [fp, #LO_reg_cop0+56] /* EPC */
515 str r1, [fp, #LO_reg_cop0+48] /* Status */
516 str r2, [fp, #LO_reg_cop0+52] /* Cause */
520 .size jump_syscall, .-jump_syscall
524 FUNCTION(jump_syscall_hle):
525 str r0, [fp, #LO_pcaddr] /* PC must be set to EPC for psxException */
526 ldr r2, [fp, #LO_last_count]
527 mov r1, #0 /* in delay slot */
529 mov r0, #0x20 /* cause */
530 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
533 /* note: psxException might do recursive recompiler call from it's HLE code,
534 * so be ready for this */
536 ldr r1, [fp, #LO_next_interupt]
537 ldr r10, [fp, #LO_cycle]
538 ldr r0, [fp, #LO_pcaddr]
540 str r1, [fp, #LO_last_count]
543 .size jump_syscall_hle, .-jump_syscall_hle
546 FUNCTION(jump_hlecall):
547 ldr r2, [fp, #LO_last_count]
548 str r0, [fp, #LO_pcaddr]
551 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
553 .size jump_hlecall, .-jump_hlecall
556 FUNCTION(jump_intcall):
557 ldr r2, [fp, #LO_last_count]
558 str r0, [fp, #LO_pcaddr]
561 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
563 .size jump_hlecall, .-jump_hlecall
566 FUNCTION(new_dyna_leave):
567 ldr r0, [fp, #LO_last_count]
570 str r10, [fp, #LO_cycle]
571 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
572 .size new_dyna_leave, .-new_dyna_leave
575 FUNCTION(invalidate_addr_r0):
576 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
577 b invalidate_addr_call
578 .size invalidate_addr_r0, .-invalidate_addr_r0
580 FUNCTION(invalidate_addr_r1):
581 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
583 b invalidate_addr_call
584 .size invalidate_addr_r1, .-invalidate_addr_r1
586 FUNCTION(invalidate_addr_r2):
587 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
589 b invalidate_addr_call
590 .size invalidate_addr_r2, .-invalidate_addr_r2
592 FUNCTION(invalidate_addr_r3):
593 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
595 b invalidate_addr_call
596 .size invalidate_addr_r3, .-invalidate_addr_r3
598 FUNCTION(invalidate_addr_r4):
599 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
601 b invalidate_addr_call
602 .size invalidate_addr_r4, .-invalidate_addr_r4
604 FUNCTION(invalidate_addr_r5):
605 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
607 b invalidate_addr_call
608 .size invalidate_addr_r5, .-invalidate_addr_r5
610 FUNCTION(invalidate_addr_r6):
611 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
613 b invalidate_addr_call
614 .size invalidate_addr_r6, .-invalidate_addr_r6
616 FUNCTION(invalidate_addr_r7):
617 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
619 b invalidate_addr_call
620 .size invalidate_addr_r7, .-invalidate_addr_r7
622 FUNCTION(invalidate_addr_r8):
623 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
625 b invalidate_addr_call
626 .size invalidate_addr_r8, .-invalidate_addr_r8
628 FUNCTION(invalidate_addr_r9):
629 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
631 b invalidate_addr_call
632 .size invalidate_addr_r9, .-invalidate_addr_r9
634 FUNCTION(invalidate_addr_r10):
635 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
637 b invalidate_addr_call
638 .size invalidate_addr_r10, .-invalidate_addr_r10
640 FUNCTION(invalidate_addr_r12):
641 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
643 .size invalidate_addr_r12, .-invalidate_addr_r12
645 invalidate_addr_call:
646 ldr r12, [fp, #LO_inv_code_start]
647 ldr lr, [fp, #LO_inv_code_end]
651 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
652 .size invalidate_addr_call, .-invalidate_addr_call
655 FUNCTION(new_dyna_start):
656 /* ip is stored to conform EABI alignment */
657 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
658 load_varadr fp, dynarec_local
659 ldr r0, [fp, #LO_pcaddr]
661 ldr r1, [fp, #LO_next_interupt]
662 ldr r10, [fp, #LO_cycle]
663 str r1, [fp, #LO_last_count]
666 .size new_dyna_start, .-new_dyna_start
668 /* --------------------------------------- */
672 .macro pcsx_read_mem readop tab_shift
673 /* r0 = address, r1 = handler_tab, r2 = cycles */
675 lsr r3, #(20+\tab_shift)
676 ldr r12, [fp, #LO_last_count]
677 ldr r1, [r1, r3, lsl #2]
684 \readop r0, [r1, r3, lsl #\tab_shift]
687 str r2, [fp, #LO_cycle]
691 FUNCTION(jump_handler_read8):
692 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
693 pcsx_read_mem ldrbcc, 0
695 FUNCTION(jump_handler_read16):
696 add r1, #0x1000/4*4 @ shift to r16 part
697 pcsx_read_mem ldrbcc, 1
699 FUNCTION(jump_handler_read32):
700 pcsx_read_mem ldrcc, 2
703 .macro pcsx_write_mem wrtop tab_shift
704 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
706 lsr r12, #(20+\tab_shift)
707 ldr r3, [r3, r12, lsl #2]
708 str r0, [fp, #LO_address] @ some handlers still need it..
710 mov r0, r2 @ cycle return in case of direct store
715 \wrtop r1, [r3, r12, lsl #\tab_shift]
718 ldr r12, [fp, #LO_last_count]
722 str r2, [fp, #LO_cycle]
725 ldr r0, [fp, #LO_next_interupt]
727 str r0, [fp, #LO_last_count]
732 FUNCTION(jump_handler_write8):
733 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
734 pcsx_write_mem strbcc, 0
736 FUNCTION(jump_handler_write16):
737 add r3, #0x1000/4*4 @ shift to r16 part
738 pcsx_write_mem strhcc, 1
740 FUNCTION(jump_handler_write32):
741 pcsx_write_mem strcc, 2
743 FUNCTION(jump_handler_write_h):
744 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
745 ldr r12, [fp, #LO_last_count]
746 str r0, [fp, #LO_address] @ some handlers still need it..
750 str r2, [fp, #LO_cycle]
753 ldr r0, [fp, #LO_next_interupt]
755 str r0, [fp, #LO_last_count]
759 FUNCTION(jump_handle_swl):
760 /* r0 = address, r1 = data, r2 = cycles */
761 ldr r3, [fp, #LO_mem_wtab]
763 ldr r3, [r3, r12, lsl #2]
784 lsreq r12, r1, #24 @ 0
794 FUNCTION(jump_handle_swr):
795 /* r0 = address, r1 = data, r2 = cycles */
796 ldr r3, [fp, #LO_mem_wtab]
798 ldr r3, [r3, r12, lsl #2]
820 .macro rcntx_read_mode0 num
821 /* r0 = address, r2 = cycles */
822 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
824 sub r0, r0, r3, lsl #16
829 FUNCTION(rcnt0_read_count_m0):
832 FUNCTION(rcnt1_read_count_m0):
835 FUNCTION(rcnt2_read_count_m0):
838 FUNCTION(rcnt0_read_count_m1):
839 /* r0 = address, r2 = cycles */
840 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
843 mul r0, r1, r2 @ /= 5
847 FUNCTION(rcnt1_read_count_m1):
848 /* r0 = address, r2 = cycles */
849 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
852 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
855 FUNCTION(rcnt2_read_count_m1):
856 /* r0 = address, r2 = cycles */
857 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
858 mov r0, r2, lsl #16-3
859 sub r0, r0, r3, lsl #16-3
863 @ vim:filetype=armasm