2 # --register-prefix-optional --bitwise-or
4 .macro ldarg arg, stacksz, reg
5 move.l (4 + \arg * 4 + \stacksz)(%sp), \reg
9 .global read_joy_responses /* u8 *rbuf */
59 0: /* wait for special code */
70 0: /* wait for special code to end */
75 move.l #8000000/50/18, d2
77 0: /* wait enough for teensy to setup it's stuff */
86 * when communicating with 3.3V teensy:
87 * - no nops: see old value on multiple pins randomly
88 * - 1 nop: only TR often shows old value
96 .global test_joy_read_log /* u8 *dest, int size, int do_sync */
102 movea.l #0xa10003, a0
129 /* broken on Mega-ED v9?? */
143 /* delay for teensy, 128 not enough.. */
155 .global test_joy_read_log_vsync /* u8 *dest, int size */
156 test_joy_read_log_vsync:
159 movem.l d2-d7/a2, -(sp)
160 movea.l #0xa10003, a0
161 movea.l #0xc00005, a2
179 /* wait for next vsync */
191 movem.l (sp)+, d2-d7/a2
195 .global test_byte_write /* u8 *dest, int size, int seed */
237 .global run_game /* u16 mapper, int tas_sync */
242 movea.l #0xa10000, a6
243 movea.l #0xc00000, a5
244 movea.l #0xc00005, a4
245 movea.l #0xc00004, a3
247 move.b #0x40, d1 /* d2 is tmp */
248 move.b #0xff, d3 /* d4 is temp */
249 moveq.l #0x00, d5 /* progress cnt */
251 move.b d1, (0x09,a6) /* CtrlA */
252 move.b d0, (0x0b,a6) /* CtrlB */
253 move.b d0, (0x0d,a6) /* CtrlC */
254 move.b d0, (0x13,a6) /* S-CtrlA */
255 move.b d3, (0x0f,a6) /* TxDataA */
256 move.b d0, (0x19,a6) /* S-CtrlB */
257 move.b d3, (0x15,a6) /* TxDataB */
258 move.b d0, (0x1f,a6) /* S-CtrlC */
259 move.b d3, (0x1b,a6) /* TxDataC */
261 move.w #0xcbaf, (0xA13006) /* some scratch area */
264 move.l #0x10000/4/4-1, d2
272 lea (run_game_r,pc), a0
274 move.l #(run_game_r_end - run_game_r)/2-1, d2
282 movea.l #0xa10003, a0
283 bsr sync_with_teensy /* trashes d3 */
287 addq.l #1, d6 /* attempt counter */
289 /* set up for progress vram write (x,y - tile #) */
290 /* GFX_WRITE_VRAM_ADDR(0xc000 + (x + 64 * y) * 2) */
291 /* d = d5 + '0' - 32 + 0xB000/32 - 128 = d5 + 0x510 */
292 move.l #(0x40000003 | ((36 + 64*1) << 17)), (a3)
295 move.w #('/'+0x4e0), (a5)
296 move.w #('4'+0x4e0), (a5)
299 move.l #(0x40000003 | ((31 + 64*2) << 17)), (a3)
310 movea.l #0xc00008, a0
311 movea.l #0x3ff000, a1
312 movea.l #0xffffe0, a2
314 /* wait for active display */
317 btst d2, (a4) /* 8 */
323 /* flood the VDP FIFO */
328 /* these seem stable for both 50Hz/60Hz */
329 move.l (a0), (a1)+ /* #0xff07ff09 */
330 move.l (a0), (a1)+ /* #0xff00ff11 */
331 move.l (a0), (a1)+ /* #0xff18ff1a */
332 move.l (a0), (a1)+ /* #0xff21ff23 */
333 move.l (a0), (a1)+ /* #0xff2aff28 */
334 move.l (a0), (a1)+ /* #0xff33ff34 */
335 move.l (a0), (a1)+ /* #0xff3cff3e */
336 move.l (a0), (a1)+ /* #0xff45ff47 */
338 /* as long as exactly 8 or more RAM writes are performed here, */
339 /* after multiple tries RAM refresh somehow eventually syncs */
340 /* after cold boot, only 50Hz syncs to always same values though, */
341 /* so values below are 50Hz */
342 move.l (a0), (a2)+ /* #0xff4eff4f */
343 move.l (a0), (a2)+ /* #0xff58ff59 */
344 move.l (a0), (a2)+ /* #0xff60ff62 */
345 move.l (a0), (a2)+ /* #0xff69ff6b */
346 move.l (a0), (a2)+ /* #0xff72ff74 */
347 move.l (a0), (a2)+ /* #0xff7bff7c */
348 move.l (a0), (a2)+ /* #0xff83ff85 */
349 move.l (a0), (a2)+ /* #0xff8eff8f */
356 cmp.l #0xff07ff09, d3
361 cmp.l #0xff00ff11, d3 /* mystery value */
366 cmp.l #0xff45ff47, d3
369 btst.b #6, (0xa10001)
373 /* unable to get stable RAM between cold boots :( */
376 cmp.l #0xff8dff8f, d3 /* unstable */
378 cmp.l #0xff8cff8e, d3 /* stable? */
380 cmp.l #0xff8eff90, d3
387 cmp.l #0xff8eff8f, d3 /* RAM */
392 movea.l #0xA13000, a1
394 move.b d0, (0x09,a6) /* CtrlA */
400 move.w #0x3210, (0x06,a1) /* 0xA13006 */
401 move.w d7, (0x10,a1) /* 0xA13010 */
402 move.w d0, (a1) /* 0xA13000 */
411 dc.b '0','1','2','3','4','5','6','7'
412 dc.b '8','9','a','b','c','d','e','f'
414 # vim:filetype=asmM68k:ts=4:sw=4:expandtab