1 // Memory I/O handlers for Sega/Mega CD.
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2 // Loosely based on Gens code.
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3 // (c) Copyright 2007, Grazvydas "notaz" Ignotas
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6 #include "../pico_int.h"
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8 #include "../sound/ym2612.h"
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9 #include "../sound/sn76496.h"
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14 #ifndef UTYPES_DEFINED
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15 typedef unsigned char u8;
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16 typedef unsigned short u16;
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17 typedef unsigned int u32;
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18 #define UTYPES_DEFINED
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26 //#define rdprintf dprintf
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27 #define rdprintf(...)
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28 //#define wrdprintf dprintf
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29 #define wrdprintf(...)
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30 #define r3printf(...)
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33 #ifdef EMU_CORE_DEBUG
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34 extern u32 lastread_a, lastread_d[16], lastwrite_cyc_d[16];
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35 extern int lrp_cyc, lwp_cyc;
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36 #undef USE_POLL_DETECT
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39 // -----------------------------------------------------------------
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42 #define POLL_LIMIT 16
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43 #define POLL_CYCLES 124
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44 // int m68k_poll_addr, m68k_poll_cnt;
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45 unsigned int s68k_poll_adclk, s68k_poll_cnt;
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47 #ifndef _ASM_CD_MEMORY_C
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48 static u32 m68k_reg_read16(u32 a)
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52 // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);
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56 d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens
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59 d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
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60 // the DMNA delay must only be visible on s68k side (Lunar2, Silpheed)
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61 if (Pico_mcd->m.state_flags&2) { d &= ~1; d |= 2; }
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62 r3printf(EL_STATUS, "m68k_regs r3: %02x @%06x", (u8)d, SekPc);
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65 d = Pico_mcd->s68k_regs[4]<<8;
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68 d = *(u16 *)(Pico_mcd->bios + 0x72);
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71 d = Read_CDC_Host(0);
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74 elprintf(EL_UIO, "m68k FIXME: reserved read");
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77 d = Pico_mcd->m.timer_stopwatch >> 16;
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78 dprintf("m68k stopwatch timer read (%04x)", d);
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83 // comm flag/cmd/status (0xE-0x2F)
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84 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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88 elprintf(EL_UIO, "m68k_regs FIXME invalid read @ %02x", a);
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96 #ifndef _ASM_CD_MEMORY_C
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99 void m68k_reg_write8(u32 a, u32 d)
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102 // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);
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107 if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { elprintf(EL_INTS, "m68k: s68k irq 2"); SekInterruptS68k(2); }
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111 if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset
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112 if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));
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113 if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);
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114 if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {
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115 SekResetS68k(); // S68k comes out of RESET or BRQ state
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116 Pico_mcd->m.state_flags&=~1;
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117 dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);
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119 Pico_mcd->m.busreq = d;
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122 dprintf("m68k: prg wp=%02x", d);
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123 Pico_mcd->s68k_regs[2] = d; // really use s68k side register
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126 u32 dold = Pico_mcd->s68k_regs[3]&0x1f;
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127 r3printf(EL_STATUS, "m68k_regs w3: %02x @%06x", (u8)d, SekPc);
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129 if ((dold>>6) != ((d>>6)&3))
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130 dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
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131 //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);
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132 //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :
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133 // ((d&2) ? "word ram to s68k" : "word ram to m68k"));
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135 d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing
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137 //dold &= ~2; // ??
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139 if (d & (d ^ dold) & 2) { // DMNA is being set
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140 Pico_mcd->m.state_flags |= 2; // we must delay setting DMNA bit (needed for Silpheed)
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144 Pico_mcd->m.state_flags &= ~2;
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146 if (d & 2) dold &= ~1; // return word RAM to s68k in 2M mode
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149 Pico_mcd->s68k_regs[3] = d | dold; // really use s68k side register
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150 #ifdef USE_POLL_DETECT
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151 if ((s68k_poll_adclk&0xfe) == 2 && s68k_poll_cnt > POLL_LIMIT) {
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152 SekSetStopS68k(0); s68k_poll_adclk = 0;
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153 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
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159 Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer
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162 Pico_mcd->bios[0x72] = d;
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163 dprintf("hint vector set to %08x", PicoRead32(0x70));
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166 d = (d << 1) | ((d >> 7) & 1); // rol8 1 (special case)
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168 //dprintf("m68k: comm flag: %02x", d);
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169 Pico_mcd->s68k_regs[0xe] = d;
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170 #ifdef USE_POLL_DETECT
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171 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {
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172 SekSetStopS68k(0); s68k_poll_adclk = 0;
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173 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
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179 if ((a&0xf0) == 0x10) {
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180 Pico_mcd->s68k_regs[a] = d;
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181 #ifdef USE_POLL_DETECT
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182 if ((a&0xfe) == (s68k_poll_adclk&0xfe) && s68k_poll_cnt > POLL_LIMIT) {
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183 SekSetStopS68k(0); s68k_poll_adclk = 0;
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184 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
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190 elprintf(EL_UIO, "m68k FIXME: invalid write? [%02x] %02x", a, d);
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193 #ifndef _ASM_CD_MEMORY_C
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196 u32 s68k_poll_detect(u32 a, u32 d)
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198 #ifdef USE_POLL_DETECT
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199 // needed mostly for Cyclone, which doesn't always check it's cycle counter
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200 if (SekIsStoppedS68k()) return d;
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201 // polling detection
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202 if (a == (s68k_poll_adclk&0xff)) {
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203 unsigned int clkdiff = SekCyclesDoneS68k() - (s68k_poll_adclk>>8);
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204 if (clkdiff <= POLL_CYCLES) {
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206 //printf("-- diff: %u, cnt = %i\n", clkdiff, s68k_poll_cnt);
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207 if (s68k_poll_cnt > POLL_LIMIT) {
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209 elprintf(EL_CDPOLL, "s68k poll detected @ %06x, a=%02x", SekPcS68k, a);
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211 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;
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215 s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;
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221 #define READ_FONT_DATA(basemask) \
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223 unsigned int fnt = *(unsigned int *)(Pico_mcd->s68k_regs + 0x4c); \
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224 unsigned int col0 = (fnt >> 8) & 0x0f, col1 = (fnt >> 12) & 0x0f; \
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225 if (fnt & (basemask << 0)) d = col1 ; else d = col0; \
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226 if (fnt & (basemask << 1)) d |= col1 << 4; else d |= col0 << 4; \
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227 if (fnt & (basemask << 2)) d |= col1 << 8; else d |= col0 << 8; \
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228 if (fnt & (basemask << 3)) d |= col1 << 12; else d |= col0 << 12; \
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232 #ifndef _ASM_CD_MEMORY_C
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235 u32 s68k_reg_read16(u32 a)
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239 // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);
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243 return ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state
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245 d = (Pico_mcd->s68k_regs[2]<<8) | (Pico_mcd->s68k_regs[3]&0x1f);
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246 r3printf(EL_STATUS, "s68k_regs r3: %02x @%06x", (u8)d, SekPcS68k);
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247 return s68k_poll_detect(a, d);
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249 return CDC_Read_Reg();
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251 return Read_CDC_Host(1); // Gens returns 0 here on byte reads
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253 d = Pico_mcd->m.timer_stopwatch >> 16;
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254 dprintf("s68k stopwatch timer read (%04x)", d);
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257 dprintf("s68k int3 timer read (%02x)", Pico_mcd->s68k_regs[31]);
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258 return Pico_mcd->s68k_regs[31];
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259 case 0x34: // fader
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260 return 0; // no busy bit
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261 case 0x50: // font data (check: Lunar 2, Silpheed)
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262 READ_FONT_DATA(0x00100000);
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265 READ_FONT_DATA(0x00010000);
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268 READ_FONT_DATA(0x10000000);
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271 READ_FONT_DATA(0x01000000);
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275 d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
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277 if (a >= 0x0e && a < 0x30)
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278 return s68k_poll_detect(a, d);
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283 #ifndef _ASM_CD_MEMORY_C
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286 void s68k_reg_write8(u32 a, u32 d)
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288 //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);
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290 // Warning: d might have upper bits set
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293 return; // only m68k can change WP
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295 int dold = Pico_mcd->s68k_regs[3];
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296 r3printf(EL_STATUS, "s68k_regs w3: %02x @%06x", (u8)d, SekPcS68k);
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301 if ((d ^ dold) & 5) {
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302 d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
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305 #ifdef _ASM_CD_MEMORY_C
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306 if ((d ^ dold) & 0x1d)
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307 PicoMemResetCDdecode(d);
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310 r3printf(EL_STATUS, "wram mode 2M->1M");
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311 wram_2M_to_1M(Pico_mcd->word_ram2M);
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317 r3printf(EL_STATUS, "wram mode 1M->2M");
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318 if (!(d&1)) { // it didn't set the ret bit, which means it doesn't want to give WRAM to m68k
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320 d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode
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322 wram_1M_to_2M(Pico_mcd->word_ram2M);
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327 if (d&1) d &= ~2; // return word RAM to m68k in 2M mode
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329 Pico_mcd->m.state_flags &= ~2;
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333 dprintf("s68k CDC dest: %x", d&7);
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334 Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode
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337 //dprintf("s68k CDC reg addr: %x", d&0xf);
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343 dprintf("s68k set CDC dma addr");
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347 dprintf("s68k set stopwatch timer");
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348 Pico_mcd->m.timer_stopwatch = 0;
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351 Pico_mcd->s68k_regs[0xf] = (d>>1) | (d<<7); // ror8 1, Gens note: Dragons lair
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354 dprintf("s68k set int3 timer: %02x", d);
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355 Pico_mcd->m.timer_int3 = (d & 0xff) << 16;
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357 case 0x33: // IRQ mask
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358 dprintf("s68k irq mask: %02x", d);
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359 if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {
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360 CDD_Export_Status();
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363 case 0x34: // fader
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364 Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;
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367 return; // d/m bit is unsetable
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369 u32 d_old = Pico_mcd->s68k_regs[0x37];
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370 Pico_mcd->s68k_regs[0x37] = d&7;
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371 if ((d&4) && !(d_old&4)) {
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372 CDD_Export_Status();
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377 Pico_mcd->s68k_regs[a] = (u8) d;
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378 CDD_Import_Command();
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382 if ((a&0x1f0) == 0x10 || (a >= 0x38 && a < 0x42))
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384 elprintf(EL_UIO, "s68k FIXME: invalid write @ %02x?", a);
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388 Pico_mcd->s68k_regs[a] = (u8) d;
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392 static u32 OtherRead16End(u32 a, int realsize)
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396 #ifndef _ASM_CD_MEMORY_C
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397 if ((a&0xffffc0)==0xa12000) {
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398 d=m68k_reg_read16(a);
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403 if (SRam.data != NULL) d=3; // 64k cart
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407 if ((a&0xfe0000)==0x600000) {
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408 if (SRam.data != NULL) {
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409 d=SRam.data[((a>>1)&0xffff)+0x2000];
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410 if (realsize == 8) d|=d<<8;
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416 d=Pico_mcd->m.bcram_reg;
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421 elprintf(EL_UIO, "m68k FIXME: unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);
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423 #ifndef _ASM_CD_MEMORY_C
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430 static void OtherWrite8End(u32 a, u32 d, int realsize)
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432 #ifndef _ASM_CD_MEMORY_C
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433 if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }
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435 if ((a&0xfe0000)==0x600000) {
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436 if (SRam.data != NULL && (Pico_mcd->m.bcram_reg&1)) {
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437 SRam.data[((a>>1)&0xffff)+0x2000]=d;
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444 Pico_mcd->m.bcram_reg=d;
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449 elprintf(EL_UIO, "m68k FIXME: strange w%i: [%06x], %08x @%06x", realsize, a&0xffffff, d, SekPc);
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452 #ifndef _ASM_CD_MEMORY_C
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453 #define _CD_MEMORY_C
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454 #undef _ASM_MEMORY_C
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455 #include "../memory_cmn.c"
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456 #include "cell_map.c"
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460 // -----------------------------------------------------------------
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461 // Read Rom and read Ram
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463 #ifdef _ASM_CD_MEMORY_C
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464 u32 PicoReadM68k8(u32 a);
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466 u32 PicoReadM68k8(u32 a)
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474 case 0x00>>1: // BIOS: 000000 - 020000
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475 d = *(u8 *)(Pico_mcd->bios+(a^1));
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477 case 0x02>>1: // prg RAM
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478 if ((Pico_mcd->m.busreq&3)!=1) {
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479 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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480 d = *(prg_bank+((a^1)&0x1ffff));
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483 case 0x20>>1: // word RAM: 200000 - 220000
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484 wrdprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
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486 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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487 int bank = Pico_mcd->s68k_regs[3]&1;
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488 d = Pico_mcd->word_ram1M[bank][a^1];
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490 // allow access in any mode, like Gens does
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491 d = Pico_mcd->word_ram2M[a^1];
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493 wrdprintf("ret = %02x", (u8)d);
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495 case 0x22>>1: // word RAM: 220000 - 240000
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496 wrdprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);
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497 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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498 int bank = Pico_mcd->s68k_regs[3]&1;
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499 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged
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500 d = Pico_mcd->word_ram1M[bank][a^1];
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502 // allow access in any mode, like Gens does
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503 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];
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505 wrdprintf("ret = %02x", (u8)d);
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507 case 0xc0>>1: case 0xc2>>1: case 0xc4>>1: case 0xc6>>1:
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508 case 0xc8>>1: case 0xca>>1: case 0xcc>>1: case 0xce>>1:
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509 case 0xd0>>1: case 0xd2>>1: case 0xd4>>1: case 0xd6>>1:
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510 case 0xd8>>1: case 0xda>>1: case 0xdc>>1: case 0xde>>1:
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512 if ((a&0xe700e0)==0xc00000)
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513 d=PicoVideoRead8(a);
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515 case 0xe0>>1: case 0xe2>>1: case 0xe4>>1: case 0xe6>>1:
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516 case 0xe8>>1: case 0xea>>1: case 0xec>>1: case 0xee>>1:
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517 case 0xf0>>1: case 0xf2>>1: case 0xf4>>1: case 0xf6>>1:
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518 case 0xf8>>1: case 0xfa>>1: case 0xfc>>1: case 0xfe>>1:
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520 d = *(u8 *)(Pico.ram+((a^1)&0xffff));
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523 if ((a&0xff4000)==0xa00000) { d=z80Read8(a); break; } // Z80 Ram
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524 if ((a&0xffffc0)==0xa12000)
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525 rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);
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527 d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;
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529 if ((a&0xffffc0)==0xa12000)
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530 rdprintf("ret = %02x", (u8)d);
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535 elprintf(EL_IO, "r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);
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536 #ifdef EMU_CORE_DEBUG
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537 if (a>=Pico.romsize) {
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539 lastread_d[lrp_cyc++&15] = d;
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547 #ifdef _ASM_CD_MEMORY_C
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548 u32 PicoReadM68k16(u32 a);
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550 static u32 PicoReadM68k16(u32 a)
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558 case 0x00>>1: // BIOS: 000000 - 020000
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559 d = *(u16 *)(Pico_mcd->bios+a);
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561 case 0x02>>1: // prg RAM
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562 if ((Pico_mcd->m.busreq&3)!=1) {
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563 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
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564 wrdprintf("m68k_prgram r16: [%i,%06x] @%06x", Pico_mcd->s68k_regs[3]>>6, a, SekPc);
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565 d = *(u16 *)(prg_bank+(a&0x1fffe));
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566 wrdprintf("ret = %04x", d);
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569 case 0x20>>1: // word RAM: 200000 - 220000
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570 wrdprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
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572 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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573 int bank = Pico_mcd->s68k_regs[3]&1;
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574 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a);
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576 // allow access in any mode, like Gens does
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577 d = *(u16 *)(Pico_mcd->word_ram2M+a);
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579 wrdprintf("ret = %04x", d);
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581 case 0x22>>1: // word RAM: 220000 - 240000
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582 wrdprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);
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583 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
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584 int bank = Pico_mcd->s68k_regs[3]&1;
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585 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged
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586 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a);
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588 // allow access in any mode, like Gens does
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589 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
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591 wrdprintf("ret = %04x", d);
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593 case 0xc0>>1: case 0xc2>>1: case 0xc4>>1: case 0xc6>>1:
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594 case 0xc8>>1: case 0xca>>1: case 0xcc>>1: case 0xce>>1:
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595 case 0xd0>>1: case 0xd2>>1: case 0xd4>>1: case 0xd6>>1:
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596 case 0xd8>>1: case 0xda>>1: case 0xdc>>1: case 0xde>>1:
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598 if ((a&0xe700e0)==0xc00000)
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599 d=PicoVideoRead(a);
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601 case 0xe0>>1: case 0xe2>>1: case 0xe4>>1: case 0xe6>>1:
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602 case 0xe8>>1: case 0xea>>1: case 0xec>>1: case 0xee>>1:
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603 case 0xf0>>1: case 0xf2>>1: case 0xf4>>1: case 0xf6>>1:
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604 case 0xf8>>1: case 0xfa>>1: case 0xfc>>1: case 0xfe>>1:
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606 d=*(u16 *)(Pico.ram+(a&0xfffe));
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609 if ((a&0xffffc0)==0xa12000)
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610 rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);
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612 d = OtherRead16(a, 16);
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614 if ((a&0xffffc0)==0xa12000)
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615 rdprintf("ret = %04x", d);
\r
620 elprintf(EL_IO, "r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
\r
621 #ifdef EMU_CORE_DEBUG
\r
622 if (a>=Pico.romsize) {
\r
624 lastread_d[lrp_cyc++&15] = d;
\r
632 #ifdef _ASM_CD_MEMORY_C
\r
633 u32 PicoReadM68k32(u32 a);
\r
635 static u32 PicoReadM68k32(u32 a)
\r
643 case 0x00>>1: { // BIOS: 000000 - 020000
\r
644 u16 *pm=(u16 *)(Pico_mcd->bios+a);
\r
645 d = (pm[0]<<16)|pm[1];
\r
648 case 0x02>>1: // prg RAM
\r
649 if ((Pico_mcd->m.busreq&3)!=1) {
\r
650 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
651 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
652 d = (pm[0]<<16)|pm[1];
\r
655 case 0x20>>1: // word RAM: 200000 - 220000
\r
656 wrdprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
\r
658 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
659 int bank = Pico_mcd->s68k_regs[3]&1;
\r
660 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+a);
\r
661 d = (pm[0]<<16)|pm[1];
\r
663 // allow access in any mode, like Gens does
\r
664 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+a);
\r
665 d = (pm[0]<<16)|pm[1];
\r
667 wrdprintf("ret = %08x", d);
\r
669 case 0x22>>1: // word RAM: 220000 - 240000
\r
670 wrdprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);
\r
671 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode, cell arranged?
\r
673 int bank = Pico_mcd->s68k_regs[3]&1;
\r
674 a1 = (a&2) | (cell_map(a >> 2) << 2);
\r
675 if (a&2) a2 = cell_map((a+2) >> 2) << 2;
\r
677 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) << 16;
\r
678 d |= *(u16 *)(Pico_mcd->word_ram1M[bank]+a2);
\r
680 // allow access in any mode, like Gens does
\r
681 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
682 d = (pm[0]<<16)|pm[1];
\r
684 wrdprintf("ret = %08x", d);
\r
686 case 0xc0>>1: case 0xc2>>1: case 0xc4>>1: case 0xc6>>1:
\r
687 case 0xc8>>1: case 0xca>>1: case 0xcc>>1: case 0xce>>1:
\r
688 case 0xd0>>1: case 0xd2>>1: case 0xd4>>1: case 0xd6>>1:
\r
689 case 0xd8>>1: case 0xda>>1: case 0xdc>>1: case 0xde>>1:
\r
691 d = (PicoVideoRead(a)<<16)|PicoVideoRead(a+2);
\r
693 case 0xe0>>1: case 0xe2>>1: case 0xe4>>1: case 0xe6>>1:
\r
694 case 0xe8>>1: case 0xea>>1: case 0xec>>1: case 0xee>>1:
\r
695 case 0xf0>>1: case 0xf2>>1: case 0xf4>>1: case 0xf6>>1:
\r
696 case 0xf8>>1: case 0xfa>>1: case 0xfc>>1: case 0xfe>>1: {
\r
698 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
699 d = (pm[0]<<16)|pm[1];
\r
703 if ((a&0xffffc0)==0xa12000)
\r
704 rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);
\r
706 d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
\r
708 if ((a&0xffffc0)==0xa12000)
\r
709 rdprintf("ret = %08x", d);
\r
714 elprintf(EL_IO, "r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
\r
715 #ifdef EMU_CORE_DEBUG
\r
716 if (a>=Pico.romsize) {
\r
718 lastread_d[lrp_cyc++&15] = d;
\r
726 // -----------------------------------------------------------------
\r
728 #ifdef _ASM_CD_MEMORY_C
\r
729 void PicoWriteM68k8(u32 a,u8 d);
\r
731 void PicoWriteM68k8(u32 a,u8 d)
\r
733 elprintf(EL_IO, "w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
\r
734 #ifdef EMU_CORE_DEBUG
\r
735 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
738 if ((a&0xe00000)==0xe00000) { // Ram
\r
739 *(u8 *)(Pico.ram+((a^1)&0xffff)) = d;
\r
744 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
\r
745 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
746 *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;
\r
753 if ((a&0xfc0000)==0x200000) {
\r
754 wrdprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);
\r
755 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
756 int bank = Pico_mcd->s68k_regs[3]&1;
\r
758 a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged
\r
760 *(u8 *)(Pico_mcd->word_ram1M[bank]+(a^1))=d;
\r
762 // allow access in any mode, like Gens does
\r
763 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;
\r
768 if ((a&0xffffc0)==0xa12000) {
\r
769 rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);
\r
770 m68k_reg_write8(a, d);
\r
779 #ifdef _ASM_CD_MEMORY_C
\r
780 void PicoWriteM68k16(u32 a,u16 d);
\r
782 static void PicoWriteM68k16(u32 a,u16 d)
\r
784 elprintf(EL_IO, "w16: %06x, %04x", a&0xffffff, d);
\r
785 #ifdef EMU_CORE_DEBUG
\r
786 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
789 if ((a&0xe00000)==0xe00000) { // Ram
\r
790 *(u16 *)(Pico.ram+(a&0xfffe))=d;
\r
795 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
\r
796 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
797 wrdprintf("m68k_prgram w16: [%i,%06x] %04x @%06x", Pico_mcd->s68k_regs[3]>>6, a, d, SekPc);
\r
798 *(u16 *)(prg_bank+(a&0x1fffe))=d;
\r
805 if ((a&0xfc0000)==0x200000) {
\r
806 wrdprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);
\r
807 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
808 int bank = Pico_mcd->s68k_regs[3]&1;
\r
810 a = (a&2) | (cell_map(a >> 2) << 2); // cell arranged
\r
812 *(u16 *)(Pico_mcd->word_ram1M[bank]+a)=d;
\r
814 // allow access in any mode, like Gens does
\r
815 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;
\r
821 if ((a&0xffffc0)==0xa12000) {
\r
822 rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);
\r
823 if (a == 0xe) { // special case, 2 byte writes would be handled differently
\r
824 Pico_mcd->s68k_regs[0xe] = d >> 8;
\r
825 #ifdef USE_POLL_DETECT
\r
826 if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {
\r
827 SekSetStopS68k(0); s68k_poll_adclk = 0;
\r
828 elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
\r
833 m68k_reg_write8(a, d>>8);
\r
834 m68k_reg_write8(a+1,d&0xff);
\r
839 if ((a&0xe700e0)==0xc00000) {
\r
840 PicoVideoWrite(a,(u16)d);
\r
849 #ifdef _ASM_CD_MEMORY_C
\r
850 void PicoWriteM68k32(u32 a,u32 d);
\r
852 static void PicoWriteM68k32(u32 a,u32 d)
\r
854 elprintf(EL_IO, "w32: %06x, %08x", a&0xffffff, d);
\r
855 #ifdef EMU_CORE_DEBUG
\r
856 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
859 if ((a&0xe00000)==0xe00000)
\r
862 u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));
\r
863 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
868 if ((a&0xfe0000)==0x020000 && (Pico_mcd->m.busreq&3)!=1) {
\r
869 u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];
\r
870 u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));
\r
871 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
878 if ((a&0xfc0000)==0x200000) {
\r
879 if (d != 0) // don't log clears
\r
880 wrdprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);
\r
881 if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?
\r
882 int bank = Pico_mcd->s68k_regs[3]&1;
\r
883 if (a >= 0x220000) { // cell arranged
\r
885 a1 = (a&2) | (cell_map(a >> 2) << 2);
\r
886 if (a&2) a2 = cell_map((a+2) >> 2) << 2;
\r
888 *(u16 *)(Pico_mcd->word_ram1M[bank]+a1) = d >> 16;
\r
889 *(u16 *)(Pico_mcd->word_ram1M[bank]+a2) = d;
\r
891 u16 *pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
892 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
895 // allow access in any mode, like Gens does
\r
896 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
897 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
902 if ((a&0xffffc0)==0xa12000) {
\r
903 rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);
\r
904 if ((a&0x3e) == 0xe) dprintf("m68k FIXME: w32 [%02x]", a&0x3f);
\r
908 if ((a&0xe700e0)==0xc00000)
\r
910 PicoVideoWrite(a, (u16)(d>>16));
\r
911 PicoVideoWrite(a+2,(u16)d);
\r
915 OtherWrite16(a, (u16)(d>>16));
\r
916 OtherWrite16(a+2,(u16)d);
\r
921 // -----------------------------------------------------------------
\r
923 // -----------------------------------------------------------------
\r
925 #ifdef _ASM_CD_MEMORY_C
\r
926 u32 PicoReadS68k8(u32 a);
\r
928 static u32 PicoReadS68k8(u32 a)
\r
932 #ifdef EMU_CORE_DEBUG
\r
939 d = *(Pico_mcd->prg_ram+(a^1));
\r
944 if ((a&0xfffe00) == 0xff8000) {
\r
946 rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);
\r
947 if (a >= 0x0e && a < 0x30) {
\r
948 d = Pico_mcd->s68k_regs[a];
\r
949 s68k_poll_detect(a, d);
\r
950 rdprintf("ret = %02x", (u8)d);
\r
953 else if (a >= 0x58 && a < 0x68)
\r
954 d = gfx_cd_read(a&~1);
\r
955 else d = s68k_reg_read16(a&~1);
\r
956 if ((a&1)==0) d>>=8;
\r
957 rdprintf("ret = %02x", (u8)d);
\r
961 // word RAM (2M area)
\r
962 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
963 // test: batman returns
\r
964 wrdprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPcS68k);
\r
965 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?
\r
966 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
967 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];
\r
968 if (a&1) d &= 0x0f;
\r
971 // allow access in any mode, like Gens does
\r
972 d = Pico_mcd->word_ram2M[(a^1)&0x3ffff];
\r
974 wrdprintf("ret = %02x", (u8)d);
\r
978 // word RAM (1M area)
\r
979 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
981 wrdprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPcS68k);
\r
982 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
983 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
984 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
985 d = Pico_mcd->word_ram1M[bank][(a^1)&0x1ffff];
\r
986 wrdprintf("ret = %02x", (u8)d);
\r
991 if ((a&0xff8000)==0xff0000) {
\r
992 elprintf(EL_IO, "s68k_pcm r8: [%06x] @%06x", a, SekPcS68k);
\r
995 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];
\r
996 else if (a >= 0x20) {
\r
998 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
999 if (a & 2) d >>= 8;
\r
1001 elprintf(EL_IO, "ret = %02x", (u8)d);
\r
1006 if ((a&0xff0000)==0xfe0000) {
\r
1007 d = Pico_mcd->bram[(a>>1)&0x1fff];
\r
1011 elprintf(EL_UIO, "s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
1015 elprintf(EL_IO, "s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);
\r
1016 #ifdef EMU_CORE_DEBUG
\r
1018 lastread_d[lrp_cyc++&15] = d;
\r
1025 #ifdef _ASM_CD_MEMORY_C
\r
1026 u32 PicoReadS68k16(u32 a);
\r
1028 static u32 PicoReadS68k16(u32 a)
\r
1032 #ifdef EMU_CORE_DEBUG
\r
1033 u32 ab=a&0xfffffe;
\r
1038 if (a < 0x80000) {
\r
1039 wrdprintf("s68k_prgram r16: [%06x] @%06x", a, SekPcS68k);
\r
1040 d = *(u16 *)(Pico_mcd->prg_ram+a);
\r
1041 wrdprintf("ret = %04x", d);
\r
1046 if ((a&0xfffe00) == 0xff8000) {
\r
1048 rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);
\r
1049 if (a >= 0x58 && a < 0x68)
\r
1050 d = gfx_cd_read(a);
\r
1051 else d = s68k_reg_read16(a);
\r
1052 rdprintf("ret = %04x", d);
\r
1056 // word RAM (2M area)
\r
1057 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1058 wrdprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPcS68k);
\r
1059 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?
\r
1060 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1061 d = Pico_mcd->word_ram1M[bank][((a>>1)^1)&0x1ffff];
\r
1062 d |= d << 4; d &= ~0xf0;
\r
1064 // allow access in any mode, like Gens does
\r
1065 d = *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1067 wrdprintf("ret = %04x", d);
\r
1071 // word RAM (1M area)
\r
1072 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1074 wrdprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPcS68k);
\r
1075 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1076 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1077 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1078 d = *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1079 wrdprintf("ret = %04x", d);
\r
1084 if ((a&0xff0000)==0xfe0000) {
\r
1085 dprintf("FIXME: s68k_bram r16: [%06x] @%06x", a, SekPcS68k);
\r
1086 a = (a>>1)&0x1fff;
\r
1087 d = Pico_mcd->bram[a++]; // Gens does little endian here, and so do we..
\r
1088 d|= Pico_mcd->bram[a++] << 8; // This is most likely wrong
\r
1089 dprintf("ret = %04x", d);
\r
1094 if ((a&0xff8000)==0xff0000) {
\r
1095 dprintf("FIXME: s68k_pcm r16: [%06x] @%06x", a, SekPcS68k);
\r
1098 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff];
\r
1099 else if (a >= 0x20) {
\r
1101 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
1102 if (a & 2) d >>= 8;
\r
1104 dprintf("ret = %04x", d);
\r
1108 elprintf(EL_UIO, "s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1112 elprintf(EL_IO, "s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1113 #ifdef EMU_CORE_DEBUG
\r
1115 lastread_d[lrp_cyc++&15] = d;
\r
1122 #ifdef _ASM_CD_MEMORY_C
\r
1123 u32 PicoReadS68k32(u32 a);
\r
1125 static u32 PicoReadS68k32(u32 a)
\r
1129 #ifdef EMU_CORE_DEBUG
\r
1130 u32 ab=a&0xfffffe;
\r
1135 if (a < 0x80000) {
\r
1136 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1137 d = (pm[0]<<16)|pm[1];
\r
1142 if ((a&0xfffe00) == 0xff8000) {
\r
1144 rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);
\r
1145 if (a >= 0x58 && a < 0x68)
\r
1146 d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);
\r
1147 else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);
\r
1148 rdprintf("ret = %08x", d);
\r
1152 // word RAM (2M area)
\r
1153 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1154 wrdprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPcS68k);
\r
1155 if (Pico_mcd->s68k_regs[3]&4) { // 1M decode mode?
\r
1156 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1158 d = Pico_mcd->word_ram1M[bank][((a+0)^1)&0x1ffff] << 16;
\r
1159 d |= Pico_mcd->word_ram1M[bank][((a+1)^1)&0x1ffff];
\r
1160 d |= d << 4; d &= 0x0f0f0f0f;
\r
1162 // allow access in any mode, like Gens does
\r
1163 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];
\r
1165 wrdprintf("ret = %08x", d);
\r
1169 // word RAM (1M area)
\r
1170 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1173 wrdprintf("s68k_wram1M r32: [%06x] @%06x", a, SekPcS68k);
\r
1174 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1175 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1176 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1177 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe)); d = (pm[0]<<16)|pm[1];
\r
1178 wrdprintf("ret = %08x", d);
\r
1183 if ((a&0xff8000)==0xff0000) {
\r
1184 dprintf("s68k_pcm r32: [%06x] @%06x", a, SekPcS68k);
\r
1186 if (a >= 0x2000) {
\r
1188 d = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] << 16;
\r
1189 d |= Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff];
\r
1190 } else if (a >= 0x20) {
\r
1194 d = (Pico_mcd->pcm.ch[a].addr >> (PCM_STEP_SHIFT-8)) & 0xff0000;
\r
1195 d |= (Pico_mcd->pcm.ch[(a+1)&7].addr >> PCM_STEP_SHIFT) & 0xff;
\r
1197 d = Pico_mcd->pcm.ch[a>>2].addr >> PCM_STEP_SHIFT;
\r
1198 d = ((d<<16)&0xff0000) | ((d>>8)&0xff); // PCM chip is LE
\r
1201 dprintf("ret = %08x", d);
\r
1206 if ((a&0xff0000)==0xfe0000) {
\r
1207 dprintf("FIXME: s68k_bram r32: [%06x] @%06x", a, SekPcS68k);
\r
1208 a = (a>>1)&0x1fff;
\r
1209 d = Pico_mcd->bram[a++] << 16; // middle endian? TODO: verify against Fusion..
\r
1210 d|= Pico_mcd->bram[a++] << 24;
\r
1211 d|= Pico_mcd->bram[a++];
\r
1212 d|= Pico_mcd->bram[a++] << 8;
\r
1213 dprintf("ret = %08x", d);
\r
1217 elprintf(EL_UIO, "s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1221 elprintf(EL_IO, "s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1222 #ifdef EMU_CORE_DEBUG
\r
1223 if (ab > 0x78) { // not vectors and stuff
\r
1225 lastread_d[lrp_cyc++&15] = d;
\r
1233 #ifndef _ASM_CD_MEMORY_C
\r
1234 /* check: jaguar xj 220 (draws entire world using decode) */
\r
1235 static void decode_write8(u32 a, u8 d, int r3)
\r
1237 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);
\r
1238 u8 oldmask = (a&1) ? 0xf0 : 0x0f;
\r
1242 if (!(a&1)) d <<= 4;
\r
1245 if ((!(*pd & (~oldmask))) && d) goto do_it;
\r
1246 } else if (r3 > 8) {
\r
1247 if (d) goto do_it;
\r
1254 *pd = d | (*pd & oldmask);
\r
1258 static void decode_write16(u32 a, u16 d, int r3)
\r
1260 u8 *pd = Pico_mcd->word_ram1M[(r3 & 1)^1] + (((a>>1)^1)&0x1ffff);
\r
1262 //if ((a & 0x3ffff) < 0x28000) return;
\r
1270 if (!(dold & 0xf0)) dold |= d & 0xf0;
\r
1271 if (!(dold & 0x0f)) dold |= d & 0x0f;
\r
1273 } else if (r3 > 8) {
\r
1275 if (!(d & 0xf0)) d |= dold & 0xf0;
\r
1276 if (!(d & 0x0f)) d |= dold & 0x0f;
\r
1284 // -----------------------------------------------------------------
\r
1286 #ifdef _ASM_CD_MEMORY_C
\r
1287 void PicoWriteS68k8(u32 a,u8 d);
\r
1289 static void PicoWriteS68k8(u32 a,u8 d)
\r
1291 elprintf(EL_IO, "s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1295 #ifdef EMU_CORE_DEBUG
\r
1296 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
1300 if (a < 0x80000) {
\r
1301 u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));
\r
1302 if (a >= (Pico_mcd->s68k_regs[2]<<8)) *pm=d;
\r
1307 if ((a&0xfffe00) == 0xff8000) {
\r
1309 rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);
\r
1310 if (a >= 0x58 && a < 0x68)
\r
1311 gfx_cd_write16(a&~1, (d<<8)|d);
\r
1312 else s68k_reg_write8(a,d);
\r
1316 // word RAM (2M area)
\r
1317 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1318 int r3 = Pico_mcd->s68k_regs[3];
\r
1319 wrdprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPcS68k);
\r
1320 if (r3 & 4) { // 1M decode mode?
\r
1321 decode_write8(a, d, r3);
\r
1323 // allow access in any mode, like Gens does
\r
1324 *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff))=d;
\r
1329 // word RAM (1M area)
\r
1330 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1331 // Wing Commander tries to write here in wrong mode
\r
1334 wrdprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPcS68k);
\r
1335 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1336 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1337 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1338 *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff))=d;
\r
1343 if ((a&0xff8000)==0xff0000) {
\r
1346 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;
\r
1347 else if (a < 0x12)
\r
1348 pcm_write(a>>1, d);
\r
1353 if ((a&0xff0000)==0xfe0000) {
\r
1354 Pico_mcd->bram[(a>>1)&0x1fff] = d;
\r
1359 elprintf(EL_UIO, "s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);
\r
1364 #ifdef _ASM_CD_MEMORY_C
\r
1365 void PicoWriteS68k16(u32 a,u16 d);
\r
1367 static void PicoWriteS68k16(u32 a,u16 d)
\r
1369 elprintf(EL_IO, "s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1373 #ifdef EMU_CORE_DEBUG
\r
1374 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
1378 if (a < 0x80000) {
\r
1379 wrdprintf("s68k_prgram w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1380 if (a >= (Pico_mcd->s68k_regs[2]<<8)) // needed for Dungeon Explorer
\r
1381 *(u16 *)(Pico_mcd->prg_ram+a)=d;
\r
1386 if ((a&0xfffe00) == 0xff8000) {
\r
1388 rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);
\r
1389 if (a >= 0x58 && a < 0x68)
\r
1390 gfx_cd_write16(a, d);
\r
1392 if (a == 0xe) { // special case, 2 byte writes would be handled differently
\r
1393 Pico_mcd->s68k_regs[0xf] = d;
\r
1396 s68k_reg_write8(a, d>>8);
\r
1397 s68k_reg_write8(a+1,d&0xff);
\r
1402 // word RAM (2M area)
\r
1403 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1404 int r3 = Pico_mcd->s68k_regs[3];
\r
1405 wrdprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1406 if (r3 & 4) { // 1M decode mode?
\r
1407 decode_write16(a, d, r3);
\r
1409 // allow access in any mode, like Gens does
\r
1410 *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe))=d;
\r
1415 // word RAM (1M area)
\r
1416 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1419 wrdprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1420 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1421 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1422 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1423 *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe))=d;
\r
1428 if ((a&0xff8000)==0xff0000) {
\r
1431 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a>>1)&0xfff] = d;
\r
1432 else if (a < 0x12)
\r
1433 pcm_write(a>>1, d & 0xff);
\r
1438 if ((a&0xff0000)==0xfe0000) {
\r
1439 dprintf("s68k_bram w16: [%06x] %04x @%06x", a, d, SekPcS68k);
\r
1440 a = (a>>1)&0x1fff;
\r
1441 Pico_mcd->bram[a++] = d; // Gens does little endian here, an so do we..
\r
1442 Pico_mcd->bram[a++] = d >> 8;
\r
1447 elprintf(EL_UIO, "s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);
\r
1452 #ifdef _ASM_CD_MEMORY_C
\r
1453 void PicoWriteS68k32(u32 a,u32 d);
\r
1455 static void PicoWriteS68k32(u32 a,u32 d)
\r
1457 elprintf(EL_IO, "s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1461 #ifdef EMU_CORE_DEBUG
\r
1462 lastwrite_cyc_d[lwp_cyc++&15] = d;
\r
1466 if (a < 0x80000) {
\r
1467 if (a >= (Pico_mcd->s68k_regs[2]<<8)) {
\r
1468 u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);
\r
1469 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1475 if ((a&0xfffe00) == 0xff8000) {
\r
1477 rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);
\r
1478 if (a >= 0x58 && a < 0x68) {
\r
1479 gfx_cd_write16(a, d>>16);
\r
1480 gfx_cd_write16(a+2, d&0xffff);
\r
1482 if ((a&0x1fe) == 0xe) dprintf("s68k FIXME: w32 [%02x]", a&0x3f);
\r
1483 s68k_reg_write8(a, d>>24);
\r
1484 s68k_reg_write8(a+1,(d>>16)&0xff);
\r
1485 s68k_reg_write8(a+2,(d>>8) &0xff);
\r
1486 s68k_reg_write8(a+3, d &0xff);
\r
1491 // word RAM (2M area)
\r
1492 if ((a&0xfc0000)==0x080000) { // 080000-0bffff
\r
1493 int r3 = Pico_mcd->s68k_regs[3];
\r
1494 wrdprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPcS68k);
\r
1495 if (r3 & 4) { // 1M decode mode?
\r
1496 decode_write16(a , d >> 16, r3);
\r
1497 decode_write16(a+2, d , r3);
\r
1499 // allow access in any mode, like Gens does
\r
1500 u16 *pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1501 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1506 // word RAM (1M area)
\r
1507 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff
\r
1511 wrdprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPcS68k);
\r
1512 // if (!(Pico_mcd->s68k_regs[3]&4))
\r
1513 // dprintf("s68k_wram1M FIXME: wrong mode");
\r
1514 bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1515 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1516 pm[0]=(u16)(d>>16); pm[1]=(u16)d;
\r
1521 if ((a&0xff8000)==0xff0000) {
\r
1523 if (a >= 0x2000) {
\r
1525 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][a&0xfff] = (d >> 16);
\r
1526 Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank][(a+1)&0xfff] = d;
\r
1527 } else if (a < 0x12) {
\r
1529 pcm_write(a, (d>>16) & 0xff);
\r
1530 pcm_write(a+1, d & 0xff);
\r
1536 if ((a&0xff0000)==0xfe0000) {
\r
1537 dprintf("s68k_bram w32: [%06x] %08x @%06x", a, d, SekPcS68k);
\r
1538 a = (a>>1)&0x1fff;
\r
1539 Pico_mcd->bram[a++] = d >> 16; // middle endian? verify?
\r
1540 Pico_mcd->bram[a++] = d >> 24;
\r
1541 Pico_mcd->bram[a++] = d;
\r
1542 Pico_mcd->bram[a++] = d >> 8;
\r
1547 elprintf(EL_UIO, "s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);
\r
1552 // -----------------------------------------------------------------
\r
1556 static __inline int PicoMemBaseM68k(u32 pc)
\r
1558 if ((pc&0xe00000)==0xe00000)
\r
1559 return (int)Pico.ram-(pc&0xff0000); // Program Counter in Ram
\r
1562 return (int)Pico_mcd->bios; // Program Counter in BIOS
\r
1564 if ((pc&0xfc0000)==0x200000)
\r
1566 if (!(Pico_mcd->s68k_regs[3]&4))
\r
1567 return (int)Pico_mcd->word_ram2M - 0x200000; // Program Counter in Word Ram
\r
1568 if (pc < 0x220000) {
\r
1569 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1570 return (int)Pico_mcd->word_ram1M[bank] - 0x200000;
\r
1574 // Error - Program Counter is invalid
\r
1575 elprintf(EL_ANOMALY, "m68k FIXME: unhandled jump to %06x", pc);
\r
1577 return (int)Pico_mcd->bios;
\r
1581 static u32 PicoCheckPcM68k(u32 pc)
\r
1583 pc-=PicoCpuCM68k.membase; // Get real pc
\r
1586 PicoCpuCM68k.membase=PicoMemBaseM68k(pc);
\r
1588 return PicoCpuCM68k.membase+pc;
\r
1592 static __inline int PicoMemBaseS68k(u32 pc)
\r
1594 if (pc < 0x80000) // PRG RAM
\r
1595 return (int)Pico_mcd->prg_ram;
\r
1597 if ((pc&0xfc0000)==0x080000) // WORD RAM 2M area (assume we are in the right mode..)
\r
1598 return (int)Pico_mcd->word_ram2M - 0x080000;
\r
1600 if ((pc&0xfe0000)==0x0c0000) { // word RAM 1M area
\r
1601 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1602 return (int)Pico_mcd->word_ram1M[bank] - 0x0c0000;
\r
1605 // Error - Program Counter is invalid
\r
1606 elprintf(EL_ANOMALY, "s68k FIXME: unhandled jump to %06x", pc);
\r
1608 return (int)Pico_mcd->prg_ram;
\r
1612 static u32 PicoCheckPcS68k(u32 pc)
\r
1614 pc-=PicoCpuCS68k.membase; // Get real pc
\r
1617 PicoCpuCS68k.membase=PicoMemBaseS68k(pc);
\r
1619 return PicoCpuCS68k.membase+pc;
\r
1623 #ifndef _ASM_CD_MEMORY_C
\r
1624 void PicoMemResetCD(int r3)
\r
1627 // update fetchmap..
\r
1631 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x240000; i++)
\r
1632 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x200000;
\r
1636 for (i = M68K_FETCHBANK1*2/16; (i<<(24-FAMEC_FETCHBITS)) < 0x220000; i++)
\r
1637 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[r3 & 1] - 0x200000;
\r
1638 for (i = M68K_FETCHBANK1*0x0c/0x100; (i<<(24-FAMEC_FETCHBITS)) < 0x0e0000; i++)
\r
1639 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram1M[(r3&1)^1] - 0x0c0000;
\r
1646 static void m68k_mem_setup_cd(void);
\r
1649 PICO_INTERNAL void PicoMemSetupCD(void)
\r
1651 // additional handlers for common code
\r
1652 PicoRead16Hook = OtherRead16End;
\r
1653 PicoWrite8Hook = OtherWrite8End;
\r
1656 // Setup m68k memory callbacks:
\r
1657 PicoCpuCM68k.checkpc=PicoCheckPcM68k;
\r
1658 PicoCpuCM68k.fetch8 =PicoCpuCM68k.read8 =PicoReadM68k8;
\r
1659 PicoCpuCM68k.fetch16=PicoCpuCM68k.read16=PicoReadM68k16;
\r
1660 PicoCpuCM68k.fetch32=PicoCpuCM68k.read32=PicoReadM68k32;
\r
1661 PicoCpuCM68k.write8 =PicoWriteM68k8;
\r
1662 PicoCpuCM68k.write16=PicoWriteM68k16;
\r
1663 PicoCpuCM68k.write32=PicoWriteM68k32;
\r
1665 PicoCpuCS68k.checkpc=PicoCheckPcS68k;
\r
1666 PicoCpuCS68k.fetch8 =PicoCpuCS68k.read8 =PicoReadS68k8;
\r
1667 PicoCpuCS68k.fetch16=PicoCpuCS68k.read16=PicoReadS68k16;
\r
1668 PicoCpuCS68k.fetch32=PicoCpuCS68k.read32=PicoReadS68k32;
\r
1669 PicoCpuCS68k.write8 =PicoWriteS68k8;
\r
1670 PicoCpuCS68k.write16=PicoWriteS68k16;
\r
1671 PicoCpuCS68k.write32=PicoWriteS68k32;
\r
1675 PicoCpuFM68k.read_byte =PicoReadM68k8;
\r
1676 PicoCpuFM68k.read_word =PicoReadM68k16;
\r
1677 PicoCpuFM68k.read_long =PicoReadM68k32;
\r
1678 PicoCpuFM68k.write_byte=PicoWriteM68k8;
\r
1679 PicoCpuFM68k.write_word=PicoWriteM68k16;
\r
1680 PicoCpuFM68k.write_long=PicoWriteM68k32;
\r
1682 PicoCpuFS68k.read_byte =PicoReadS68k8;
\r
1683 PicoCpuFS68k.read_word =PicoReadS68k16;
\r
1684 PicoCpuFS68k.read_long =PicoReadS68k32;
\r
1685 PicoCpuFS68k.write_byte=PicoWriteS68k8;
\r
1686 PicoCpuFS68k.write_word=PicoWriteS68k16;
\r
1687 PicoCpuFS68k.write_long=PicoWriteS68k32;
\r
1689 // setup FAME fetchmap
\r
1693 // by default, point everything to fitst 64k of ROM (BIOS)
\r
1694 for (i = 0; i < M68K_FETCHBANK1; i++)
\r
1695 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom - (i<<(24-FAMEC_FETCHBITS));
\r
1696 // now real ROM (BIOS)
\r
1697 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)
\r
1698 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.rom;
\r
1700 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)
\r
1701 PicoCpuFM68k.Fetch[i] = (unsigned int)Pico.ram - (i<<(24-FAMEC_FETCHBITS));
\r
1703 // PRG RAM is default
\r
1704 for (i = 0; i < M68K_FETCHBANK1; i++)
\r
1705 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram - (i<<(24-FAMEC_FETCHBITS));
\r
1707 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0x80000; i++)
\r
1708 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->prg_ram;
\r
1709 // WORD RAM 2M area
\r
1710 for (i = M68K_FETCHBANK1*0x08/0x100; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0xc0000; i++)
\r
1711 PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x80000;
\r
1712 // PicoMemResetCD() will setup word ram for both
\r
1716 m68k_mem_setup_cd();
\r
1719 // m68k_poll_addr = m68k_poll_cnt = 0;
\r
1720 s68k_poll_adclk = s68k_poll_cnt = 0;
\r
1725 static unsigned int PicoReadCD8w (unsigned int a) {
\r
1726 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k8(a) : PicoReadM68k8(a);
\r
1728 static unsigned int PicoReadCD16w(unsigned int a) {
\r
1729 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k16(a) : PicoReadM68k16(a);
\r
1731 static unsigned int PicoReadCD32w(unsigned int a) {
\r
1732 return m68ki_cpu_p == &PicoCpuMS68k ? PicoReadS68k32(a) : PicoReadM68k32(a);
\r
1734 static void PicoWriteCD8w (unsigned int a, unsigned char d) {
\r
1735 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);
\r
1737 static void PicoWriteCD16w(unsigned int a, unsigned short d) {
\r
1738 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);
\r
1740 static void PicoWriteCD32w(unsigned int a, unsigned int d) {
\r
1741 if (m68ki_cpu_p == &PicoCpuMS68k) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);
\r
1744 // these are allowed to access RAM
\r
1745 static unsigned int m68k_read_pcrelative_CD8 (unsigned int a)
\r
1748 if(m68ki_cpu_p == &PicoCpuMS68k) {
\r
1749 if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram
\r
1750 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)
\r
1751 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));
\r
1752 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)
\r
1753 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1754 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));
\r
1756 elprintf(EL_ANOMALY, "s68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);
\r
1758 if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram
\r
1759 if(a<0x20000) return *(u8 *)(Pico.rom+(a^1)); // Bios
\r
1760 if((a&0xfc0000)==0x200000) { // word RAM
\r
1761 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?
\r
1762 return *(u8 *)(Pico_mcd->word_ram2M+((a^1)&0x3ffff));
\r
1763 else if (a < 0x220000) {
\r
1764 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1765 return *(u8 *)(Pico_mcd->word_ram1M[bank]+((a^1)&0x1ffff));
\r
1768 elprintf(EL_ANOMALY, "m68k_read_pcrelative_CD8 FIXME: can't handle %06x", a);
\r
1770 return 0;//(u8) lastread_d;
\r
1772 static unsigned int m68k_read_pcrelative_CD16(unsigned int a)
\r
1775 if(m68ki_cpu_p == &PicoCpuMS68k) {
\r
1776 if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram
\r
1777 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)
\r
1778 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1779 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)
\r
1780 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1781 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1783 elprintf(EL_ANOMALY, "s68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);
\r
1785 if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram
\r
1786 if(a<0x20000) return *(u16 *)(Pico.rom+(a&~1)); // Bios
\r
1787 if((a&0xfc0000)==0x200000) { // word RAM
\r
1788 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?
\r
1789 return *(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe));
\r
1790 else if (a < 0x220000) {
\r
1791 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1792 return *(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1795 elprintf(EL_ANOMALY, "m68k_read_pcrelative_CD16 FIXME: can't handle %06x", a);
\r
1799 static unsigned int m68k_read_pcrelative_CD32(unsigned int a)
\r
1803 if(m68ki_cpu_p == &PicoCpuMS68k) {
\r
1804 if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram
\r
1805 if ((a&0xfc0000)==0x080000 && !(Pico_mcd->s68k_regs[3]&4)) // word RAM (2M area: 080000-0bffff)
\r
1806 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
\r
1807 if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // word RAM (1M area: 0c0000-0dffff)
\r
1808 int bank = (Pico_mcd->s68k_regs[3]&1)^1;
\r
1809 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1810 return (pm[0]<<16)|pm[1];
\r
1812 elprintf(EL_ANOMALY, "s68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);
\r
1814 if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram
\r
1815 if(a<0x20000) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }
\r
1816 if((a&0xfc0000)==0x200000) { // word RAM
\r
1817 if(!(Pico_mcd->s68k_regs[3]&4)) // 2M?
\r
1818 { pm=(u16 *)(Pico_mcd->word_ram2M+(a&0x3fffe)); return (pm[0]<<16)|pm[1]; }
\r
1819 else if (a < 0x220000) {
\r
1820 int bank = Pico_mcd->s68k_regs[3]&1;
\r
1821 pm=(u16 *)(Pico_mcd->word_ram1M[bank]+(a&0x1fffe));
\r
1822 return (pm[0]<<16)|pm[1];
\r
1825 elprintf(EL_ANOMALY, "m68k_read_pcrelative_CD32 FIXME: can't handle %06x", a);
\r
1830 extern unsigned int (*pm68k_read_memory_8) (unsigned int address);
\r
1831 extern unsigned int (*pm68k_read_memory_16)(unsigned int address);
\r
1832 extern unsigned int (*pm68k_read_memory_32)(unsigned int address);
\r
1833 extern void (*pm68k_write_memory_8) (unsigned int address, unsigned char value);
\r
1834 extern void (*pm68k_write_memory_16)(unsigned int address, unsigned short value);
\r
1835 extern void (*pm68k_write_memory_32)(unsigned int address, unsigned int value);
\r
1836 extern unsigned int (*pm68k_read_memory_pcr_8) (unsigned int address);
\r
1837 extern unsigned int (*pm68k_read_memory_pcr_16)(unsigned int address);
\r
1838 extern unsigned int (*pm68k_read_memory_pcr_32)(unsigned int address);
\r
1840 static void m68k_mem_setup_cd(void)
\r
1842 pm68k_read_memory_8 = PicoReadCD8w;
\r
1843 pm68k_read_memory_16 = PicoReadCD16w;
\r
1844 pm68k_read_memory_32 = PicoReadCD32w;
\r
1845 pm68k_write_memory_8 = PicoWriteCD8w;
\r
1846 pm68k_write_memory_16 = PicoWriteCD16w;
\r
1847 pm68k_write_memory_32 = PicoWriteCD32w;
\r
1848 pm68k_read_memory_pcr_8 = m68k_read_pcrelative_CD8;
\r
1849 pm68k_read_memory_pcr_16 = m68k_read_pcrelative_CD16;
\r
1850 pm68k_read_memory_pcr_32 = m68k_read_pcrelative_CD32;
\r
1852 #endif // EMU_M68K
\r