3 * (C) notaz, 2006-2009
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5 * This work is licensed under the terms of MAME license.
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6 * See COPYING file in the top-level directory.
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9 @@ .include "port_config.s"
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11 .equ SRR_MAPPED, (1 << 0)
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12 .equ SRR_READONLY, (1 << 1)
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13 .equ SRF_EEPROM, (1 << 1)
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14 .equ POPT_6BTN_PAD, (1 << 5)
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15 .equ POPT_EN_32X, (1 << 20)
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20 .global PicoRead8_sram
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21 .global PicoRead8_io
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22 .global PicoRead16_sram
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23 .global PicoRead16_io
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24 .global PicoWrite8_io
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25 .global PicoWrite16_io
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27 PicoRead8_sram: @ u32 a, u32 d
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29 ldr r3, =(Pico+0x22200)
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30 ldr r1, [r2, #8] @ SRam.end
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33 ldr r1, [r2, #4] @ SRam.start
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36 ldrb r1, [r3, #0x11] @ Pico.m.sram_reg
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42 ldr r1, [r2, #4] @ SRam.start
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43 ldr r2, [r2] @ SRam.data
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50 ldr r1, [r3, #4] @ romsize
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53 bxgt lr @ bad location
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54 @ XXX: banking unfriendly
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65 moveq r0, r0, lsr #8
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69 PicoRead8_io: @ u32 a, u32 d
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70 bic r2, r0, #0x001f @ most commonly we get i/o port read,
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71 cmp r2, #0xa10000 @ so check for it first
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76 beq m_read8_misc_hwreg
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81 ldr r3, =(Pico+0x22000)
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82 mov r0, r0, lsr #1 @ other IO ports (Pico.ioports[a])
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87 ldr r3, =(Pico+0x22200)
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88 ldrb r0, [r3, #0x0f] @ Pico.m.hardware
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96 ldr r3, =(Pico+0x22200)
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98 ldr r0, [r3, #8] @ Pico.m.rotate
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101 eor r0, r0, r0, lsl #6
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104 bxne lr @ odd addr -> open bus
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105 bic r0, r0, #1 @ bit0 defined in this area
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106 and r2, r1, #0xff00
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108 bxne lr @ not busreq
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110 ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run
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111 ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset
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119 tst r2, #POPT_EN_32X
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124 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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126 PicoRead16_sram: @ u32 a, u32 d
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128 ldr r3, =(Pico+0x22200)
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129 ldr r1, [r2, #8] @ SRam.end
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131 bgt m_read16_nosram
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132 ldr r1, [r2, #4] @ SRam.start
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134 blt m_read16_nosram
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135 ldrb r1, [r3, #0x11] @ Pico.m.sram_reg
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136 tst r1, #SRR_MAPPED
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137 beq m_read16_nosram
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138 ldr r1, [r2, #0x0c]
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139 tst r1, #SRF_EEPROM
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141 ldr r1, [r2, #4] @ SRam.start
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142 ldr r2, [r2] @ SRam.data
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147 orr r0, r0, r1, lsl #8
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151 ldr r1, [r3, #4] @ romsize
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154 bxgt lr @ bad location
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155 @ XXX: banking unfriendly
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161 PicoRead16_io: @ u32 a, u32 d
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162 bic r2, r0, #0x001f @ most commonly we get i/o port read,
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163 cmp r2, #0xa10000 @ so check for it first
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164 bne m_read16_not_io
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166 bl m_read8_misc_io @ same as read8
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167 orr r0, r0, r0, lsl #8 @ only has bytes mirrored
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171 and r2, r0, #0xfc00
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173 bne m_read16_not_brq
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175 ldr r3, =(Pico+0x22200)
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176 and r2, r0, #0xff00
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177 ldr r0, [r3, #8] @ Pico.m.rotate
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180 eor r0, r0, r0, lsl #5
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181 eor r0, r0, r0, lsl #8
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182 bic r0, r0, #0x100 @ bit8 defined in this area
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184 bxne lr @ not busreq
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186 ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run
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187 ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset
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188 orr r0, r0, r1, lsl #8
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189 orr r0, r0, r2, lsl #8
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195 tst r2, #POPT_EN_32X
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200 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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202 PicoWrite8_io: @ u32 a, u32 d
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203 bic r2, r0, #0x1e @ most commonly we get i/o port write,
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204 eor r2, r2, #0xa10000 @ so check for it first
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206 bne m_write8_not_io
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212 ldr r3, =(Pico+0x22000) @ Pico.ioports
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213 tst r2, #POPT_6BTN_PAD
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214 beq m_write8_io_done
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217 bne m_write8_io_done @ not likely to happen
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218 add r2, r3, #0x200 @ Pico+0x22200
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221 streqb r12,[r2,#0x18]
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222 strneb r12,[r2,#0x19] @ Pico.m.padDelay[i] = 0
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224 beq m_write8_io_done
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225 ldrb r12,[r3, r0, lsr #1]
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227 bne m_write8_io_done
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229 ldreqb r12,[r2,#0x0a]
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230 ldrneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
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232 streqb r12,[r2,#0x0a]
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233 strneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
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235 strb r1, [r3, r0, lsr #1]
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240 bne m_write8_not_z80ctl @ even addrs only
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241 and r2, r0, #0xff00
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244 beq ctl_write_z80busreq
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247 beq ctl_write_z80reset
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249 m_write8_not_z80ctl:
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251 eor r2, r0, #0xa10000
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252 eor r2, r2, #0x003000
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253 eors r2, r2, #0x0000f1
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254 bne m_write8_not_sreg
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255 ldr r3, =(Pico+0x22200)
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256 ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg
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257 and r1, r1, #(SRR_MAPPED|SRR_READONLY)
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258 bic r2, r2, #(SRR_MAPPED|SRR_READONLY)
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260 strb r2, [r3, #(8+9)]
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266 tst r2, #POPT_EN_32X
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270 @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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272 PicoWrite16_io: @ u32 a, u32 d
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273 bic r2, r0, #0x1f @ most commonly we get i/o port write,
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274 cmp r2, #0xa10000 @ so check for it first
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278 and r2, r0, #0xff00
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280 moveq r0, r1, lsr #8
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281 beq ctl_write_z80busreq
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283 moveq r0, r1, lsr #8
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284 beq ctl_write_z80reset
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286 m_write16_not_z80ctl:
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288 eor r2, r0, #0xa10000
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289 eor r2, r2, #0x003000
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290 eors r2, r2, #0x0000f0
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291 bne m_write16_not_sreg
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292 ldr r3, =(Pico+0x22200)
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293 ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg
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294 and r1, r1, #(SRR_MAPPED|SRR_READONLY)
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295 bic r2, r2, #(SRR_MAPPED|SRR_READONLY)
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297 strb r2, [r3, #(8+9)]
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300 m_write16_not_sreg:
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303 tst r2, #POPT_EN_32X
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304 bne PicoWrite16_32x
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309 @ vim:filetype=armasm
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