1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - assem_arm.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21 extern int cycle_count;
22 extern int last_count;
24 extern int pending_exception;
25 extern int branch_target;
26 extern uint64_t readmem_dword;
28 extern precomp_instr fake_pc;
30 extern void *dynarec_local;
31 extern u_int memory_map[1048576];
32 extern u_int mini_ht[32][2];
33 extern u_int rounding_modes[4];
35 void indirect_jump_indexed();
48 void jump_vaddr_r10();
49 void jump_vaddr_r12();
51 const u_int jump_vaddr_reg[16] = {
73 void set_jump_target(int addr,u_int target)
75 u_char *ptr=(u_char *)addr;
76 u_int *ptr2=(u_int *)ptr;
78 assert((target-(u_int)ptr2-8)<1024);
80 assert((target&3)==0);
81 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
82 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
84 else if(ptr[3]==0x72) {
85 // generated by emit_jno_unlikely
86 if((target-(u_int)ptr2-8)<1024) {
88 assert((target&3)==0);
89 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
91 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
93 assert((target&3)==0);
94 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
96 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
99 assert((ptr[3]&0x0e)==0xa);
100 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
104 // This optionally copies the instruction from the target of the branch into
105 // the space before the branch. Works, but the difference in speed is
106 // usually insignificant.
107 void set_jump_target_fillslot(int addr,u_int target,int copy)
109 u_char *ptr=(u_char *)addr;
110 u_int *ptr2=(u_int *)ptr;
111 assert(!copy||ptr2[-1]==0xe28dd000);
114 assert((target-(u_int)ptr2-8)<4096);
115 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
118 assert((ptr[3]&0x0e)==0xa);
119 u_int target_insn=*(u_int *)target;
120 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
123 if((target_insn&0x0c100000)==0x04100000) { // Load
126 if(target_insn&0x08000000) {
130 ptr2[-1]=target_insn;
133 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
138 add_literal(int addr,int val)
140 literals[literalcount][0]=addr;
141 literals[literalcount][1]=val;
145 void *kill_pointer(void *stub)
147 int *ptr=(int *)(stub+4);
148 assert((*ptr&0x0ff00000)==0x05900000);
149 u_int offset=*ptr&0xfff;
150 int **l_ptr=(void *)ptr+offset+8;
152 set_jump_target((int)i_ptr,(int)stub);
156 int get_pointer(void *stub)
158 //printf("get_pointer(%x)\n",(int)stub);
159 int *ptr=(int *)(stub+4);
160 assert((*ptr&0x0ff00000)==0x05900000);
161 u_int offset=*ptr&0xfff;
162 int **l_ptr=(void *)ptr+offset+8;
164 assert((*i_ptr&0x0f000000)==0x0a000000);
165 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
168 // Find the "clean" entry point from a "dirty" entry point
169 // by skipping past the call to verify_code
170 u_int get_clean_addr(int addr)
172 int *ptr=(int *)addr;
178 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
179 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
181 if((*ptr&0xFF000000)==0xea000000) {
182 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
187 int verify_dirty(int addr)
189 u_int *ptr=(u_int *)addr;
191 // get from literal pool
192 assert((*ptr&0xFFF00000)==0xe5900000);
193 u_int offset=*ptr&0xfff;
194 u_int *l_ptr=(void *)ptr+offset+8;
195 u_int source=l_ptr[0];
201 assert((*ptr&0xFFF00000)==0xe3000000);
202 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
203 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
204 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
207 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
208 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
209 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
210 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
211 unsigned int page=source>>12;
212 unsigned int map_value=memory_map[page];
213 if(map_value>=0x80000000) return 0;
214 while(page<((source+len-1)>>12)) {
215 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
217 source = source+(map_value<<2);
219 //printf("verify_dirty: %x %x %x\n",source,copy,len);
220 return !memcmp((void *)source,(void *)copy,len);
223 // This doesn't necessarily find all clean entry points, just
224 // guarantees that it's not dirty
225 int isclean(int addr)
228 int *ptr=((u_int *)addr)+4;
230 int *ptr=((u_int *)addr)+6;
232 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
233 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
234 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
235 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
236 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
240 void get_bounds(int addr,u_int *start,u_int *end)
242 u_int *ptr=(u_int *)addr;
244 // get from literal pool
245 assert((*ptr&0xFFF00000)==0xe5900000);
246 u_int offset=*ptr&0xfff;
247 u_int *l_ptr=(void *)ptr+offset+8;
248 u_int source=l_ptr[0];
249 //u_int copy=l_ptr[1];
254 assert((*ptr&0xFFF00000)==0xe3000000);
255 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
256 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
257 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
260 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
261 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
262 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
263 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
264 if(memory_map[source>>12]>=0x80000000) source = 0;
265 else source = source+(memory_map[source>>12]<<2);
271 /* Register allocation */
273 // Note: registers are allocated clean (unmodified state)
274 // if you intend to modify the register, you must call dirty_reg().
275 void alloc_reg(struct regstat *cur,int i,signed char reg)
278 int preferred_reg = (reg&7);
279 if(reg==CCREG) preferred_reg=HOST_CCREG;
280 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
282 // Don't allocate unused registers
283 if((cur->u>>reg)&1) return;
285 // see if it's already allocated
286 for(hr=0;hr<HOST_REGS;hr++)
288 if(cur->regmap[hr]==reg) return;
291 // Keep the same mapping if the register was already allocated in a loop
292 preferred_reg = loop_reg(i,reg,preferred_reg);
294 // Try to allocate the preferred register
295 if(cur->regmap[preferred_reg]==-1) {
296 cur->regmap[preferred_reg]=reg;
297 cur->dirty&=~(1<<preferred_reg);
298 cur->isconst&=~(1<<preferred_reg);
301 r=cur->regmap[preferred_reg];
302 if(r<64&&((cur->u>>r)&1)) {
303 cur->regmap[preferred_reg]=reg;
304 cur->dirty&=~(1<<preferred_reg);
305 cur->isconst&=~(1<<preferred_reg);
308 if(r>=64&&((cur->uu>>(r&63))&1)) {
309 cur->regmap[preferred_reg]=reg;
310 cur->dirty&=~(1<<preferred_reg);
311 cur->isconst&=~(1<<preferred_reg);
315 // Clear any unneeded registers
316 // We try to keep the mapping consistent, if possible, because it
317 // makes branches easier (especially loops). So we try to allocate
318 // first (see above) before removing old mappings. If this is not
319 // possible then go ahead and clear out the registers that are no
321 for(hr=0;hr<HOST_REGS;hr++)
326 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
330 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
334 // Try to allocate any available register, but prefer
335 // registers that have not been used recently.
337 for(hr=0;hr<HOST_REGS;hr++) {
338 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
339 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
341 cur->dirty&=~(1<<hr);
342 cur->isconst&=~(1<<hr);
348 // Try to allocate any available register
349 for(hr=0;hr<HOST_REGS;hr++) {
350 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
352 cur->dirty&=~(1<<hr);
353 cur->isconst&=~(1<<hr);
358 // Ok, now we have to evict someone
359 // Pick a register we hopefully won't need soon
360 u_char hsn[MAXREG+1];
361 memset(hsn,10,sizeof(hsn));
363 lsn(hsn,i,&preferred_reg);
364 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
365 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
367 // Don't evict the cycle count at entry points, otherwise the entry
368 // stub will have to write it.
369 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
370 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
373 // Alloc preferred register if available
374 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
375 for(hr=0;hr<HOST_REGS;hr++) {
376 // Evict both parts of a 64-bit register
377 if((cur->regmap[hr]&63)==r) {
379 cur->dirty&=~(1<<hr);
380 cur->isconst&=~(1<<hr);
383 cur->regmap[preferred_reg]=reg;
386 for(r=1;r<=MAXREG;r++)
388 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
389 for(hr=0;hr<HOST_REGS;hr++) {
390 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
391 if(cur->regmap[hr]==r+64) {
393 cur->dirty&=~(1<<hr);
394 cur->isconst&=~(1<<hr);
399 for(hr=0;hr<HOST_REGS;hr++) {
400 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
401 if(cur->regmap[hr]==r) {
403 cur->dirty&=~(1<<hr);
404 cur->isconst&=~(1<<hr);
415 for(r=1;r<=MAXREG;r++)
418 for(hr=0;hr<HOST_REGS;hr++) {
419 if(cur->regmap[hr]==r+64) {
421 cur->dirty&=~(1<<hr);
422 cur->isconst&=~(1<<hr);
426 for(hr=0;hr<HOST_REGS;hr++) {
427 if(cur->regmap[hr]==r) {
429 cur->dirty&=~(1<<hr);
430 cur->isconst&=~(1<<hr);
437 printf("This shouldn't happen (alloc_reg)");exit(1);
440 void alloc_reg64(struct regstat *cur,int i,signed char reg)
442 int preferred_reg = 8+(reg&1);
445 // allocate the lower 32 bits
446 alloc_reg(cur,i,reg);
448 // Don't allocate unused registers
449 if((cur->uu>>reg)&1) return;
451 // see if the upper half is already allocated
452 for(hr=0;hr<HOST_REGS;hr++)
454 if(cur->regmap[hr]==reg+64) return;
457 // Keep the same mapping if the register was already allocated in a loop
458 preferred_reg = loop_reg(i,reg,preferred_reg);
460 // Try to allocate the preferred register
461 if(cur->regmap[preferred_reg]==-1) {
462 cur->regmap[preferred_reg]=reg|64;
463 cur->dirty&=~(1<<preferred_reg);
464 cur->isconst&=~(1<<preferred_reg);
467 r=cur->regmap[preferred_reg];
468 if(r<64&&((cur->u>>r)&1)) {
469 cur->regmap[preferred_reg]=reg|64;
470 cur->dirty&=~(1<<preferred_reg);
471 cur->isconst&=~(1<<preferred_reg);
474 if(r>=64&&((cur->uu>>(r&63))&1)) {
475 cur->regmap[preferred_reg]=reg|64;
476 cur->dirty&=~(1<<preferred_reg);
477 cur->isconst&=~(1<<preferred_reg);
481 // Clear any unneeded registers
482 // We try to keep the mapping consistent, if possible, because it
483 // makes branches easier (especially loops). So we try to allocate
484 // first (see above) before removing old mappings. If this is not
485 // possible then go ahead and clear out the registers that are no
487 for(hr=HOST_REGS-1;hr>=0;hr--)
492 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
496 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
500 // Try to allocate any available register, but prefer
501 // registers that have not been used recently.
503 for(hr=0;hr<HOST_REGS;hr++) {
504 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
505 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
506 cur->regmap[hr]=reg|64;
507 cur->dirty&=~(1<<hr);
508 cur->isconst&=~(1<<hr);
514 // Try to allocate any available register
515 for(hr=0;hr<HOST_REGS;hr++) {
516 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
517 cur->regmap[hr]=reg|64;
518 cur->dirty&=~(1<<hr);
519 cur->isconst&=~(1<<hr);
524 // Ok, now we have to evict someone
525 // Pick a register we hopefully won't need soon
526 u_char hsn[MAXREG+1];
527 memset(hsn,10,sizeof(hsn));
529 lsn(hsn,i,&preferred_reg);
530 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
531 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
533 // Don't evict the cycle count at entry points, otherwise the entry
534 // stub will have to write it.
535 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
536 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
539 // Alloc preferred register if available
540 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
541 for(hr=0;hr<HOST_REGS;hr++) {
542 // Evict both parts of a 64-bit register
543 if((cur->regmap[hr]&63)==r) {
545 cur->dirty&=~(1<<hr);
546 cur->isconst&=~(1<<hr);
549 cur->regmap[preferred_reg]=reg|64;
552 for(r=1;r<=MAXREG;r++)
554 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
555 for(hr=0;hr<HOST_REGS;hr++) {
556 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
557 if(cur->regmap[hr]==r+64) {
558 cur->regmap[hr]=reg|64;
559 cur->dirty&=~(1<<hr);
560 cur->isconst&=~(1<<hr);
565 for(hr=0;hr<HOST_REGS;hr++) {
566 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
567 if(cur->regmap[hr]==r) {
568 cur->regmap[hr]=reg|64;
569 cur->dirty&=~(1<<hr);
570 cur->isconst&=~(1<<hr);
581 for(r=1;r<=MAXREG;r++)
584 for(hr=0;hr<HOST_REGS;hr++) {
585 if(cur->regmap[hr]==r+64) {
586 cur->regmap[hr]=reg|64;
587 cur->dirty&=~(1<<hr);
588 cur->isconst&=~(1<<hr);
592 for(hr=0;hr<HOST_REGS;hr++) {
593 if(cur->regmap[hr]==r) {
594 cur->regmap[hr]=reg|64;
595 cur->dirty&=~(1<<hr);
596 cur->isconst&=~(1<<hr);
603 printf("This shouldn't happen");exit(1);
606 // Allocate a temporary register. This is done without regard to
607 // dirty status or whether the register we request is on the unneeded list
608 // Note: This will only allocate one register, even if called multiple times
609 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
612 int preferred_reg = -1;
614 // see if it's already allocated
615 for(hr=0;hr<HOST_REGS;hr++)
617 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
620 // Try to allocate any available register
621 for(hr=HOST_REGS-1;hr>=0;hr--) {
622 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
624 cur->dirty&=~(1<<hr);
625 cur->isconst&=~(1<<hr);
630 // Find an unneeded register
631 for(hr=HOST_REGS-1;hr>=0;hr--)
637 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
639 cur->dirty&=~(1<<hr);
640 cur->isconst&=~(1<<hr);
647 if((cur->uu>>(r&63))&1) {
648 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
650 cur->dirty&=~(1<<hr);
651 cur->isconst&=~(1<<hr);
659 // Ok, now we have to evict someone
660 // Pick a register we hopefully won't need soon
661 // TODO: we might want to follow unconditional jumps here
662 // TODO: get rid of dupe code and make this into a function
663 u_char hsn[MAXREG+1];
664 memset(hsn,10,sizeof(hsn));
666 lsn(hsn,i,&preferred_reg);
667 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
669 // Don't evict the cycle count at entry points, otherwise the entry
670 // stub will have to write it.
671 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
672 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
675 for(r=1;r<=MAXREG;r++)
677 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
678 for(hr=0;hr<HOST_REGS;hr++) {
679 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
680 if(cur->regmap[hr]==r+64) {
682 cur->dirty&=~(1<<hr);
683 cur->isconst&=~(1<<hr);
688 for(hr=0;hr<HOST_REGS;hr++) {
689 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
690 if(cur->regmap[hr]==r) {
692 cur->dirty&=~(1<<hr);
693 cur->isconst&=~(1<<hr);
704 for(r=1;r<=MAXREG;r++)
707 for(hr=0;hr<HOST_REGS;hr++) {
708 if(cur->regmap[hr]==r+64) {
710 cur->dirty&=~(1<<hr);
711 cur->isconst&=~(1<<hr);
715 for(hr=0;hr<HOST_REGS;hr++) {
716 if(cur->regmap[hr]==r) {
718 cur->dirty&=~(1<<hr);
719 cur->isconst&=~(1<<hr);
726 printf("This shouldn't happen");exit(1);
728 // Allocate a specific ARM register.
729 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
733 // see if it's already allocated (and dealloc it)
734 for(n=0;n<HOST_REGS;n++)
736 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {cur->regmap[n]=-1;}
740 cur->dirty&=~(1<<hr);
741 cur->isconst&=~(1<<hr);
744 // Alloc cycle count into dedicated register
745 alloc_cc(struct regstat *cur,int i)
747 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
755 char regname[16][4] = {
773 void output_byte(u_char byte)
777 void output_modrm(u_char mod,u_char rm,u_char ext)
782 u_char byte=(mod<<6)|(ext<<3)|rm;
785 void output_sib(u_char scale,u_char index,u_char base)
790 u_char byte=(scale<<6)|(index<<3)|base;
793 void output_w32(u_int word)
795 *((u_int *)out)=word;
798 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
803 return((rn<<16)|(rd<<12)|rm);
805 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
810 assert((shift&1)==0);
811 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
813 u_int genimm(u_int imm,u_int *encoded)
815 if(imm==0) {*encoded=0;return 1;}
820 *encoded=((i&30)<<7)|imm;
823 imm=(imm>>2)|(imm<<30);i-=2;
827 u_int genjmp(u_int addr)
829 int offset=addr-(int)out-8;
830 if(offset<-33554432||offset>=33554432) {
832 printf("genjmp: out of range: %08x\n", offset);
837 return ((u_int)offset>>2)&0xffffff;
840 void emit_mov(int rs,int rt)
842 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
843 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
846 void emit_movs(int rs,int rt)
848 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
849 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
852 void emit_add(int rs1,int rs2,int rt)
854 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
855 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
858 void emit_adds(int rs1,int rs2,int rt)
860 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
861 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
864 void emit_adcs(int rs1,int rs2,int rt)
866 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
867 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
870 void emit_sbc(int rs1,int rs2,int rt)
872 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
873 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
876 void emit_sbcs(int rs1,int rs2,int rt)
878 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
879 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
882 void emit_neg(int rs, int rt)
884 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
885 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
888 void emit_negs(int rs, int rt)
890 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
891 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
894 void emit_sub(int rs1,int rs2,int rt)
896 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
897 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
900 void emit_subs(int rs1,int rs2,int rt)
902 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
903 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
906 void emit_zeroreg(int rt)
908 assem_debug("mov %s,#0\n",regname[rt]);
909 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
912 void emit_loadreg(int r, int hr)
916 printf("64bit load in 32bit mode!\n");
923 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
924 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
925 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
926 if(r==CCREG) addr=(int)&cycle_count;
927 if(r==CSREG) addr=(int)&Status;
928 if(r==FSREG) addr=(int)&FCR31;
929 if(r==INVCP) addr=(int)&invc_ptr;
930 u_int offset = addr-(u_int)&dynarec_local;
932 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
933 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
936 void emit_storereg(int r, int hr)
940 printf("64bit store in 32bit mode!\n");
944 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
945 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
946 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
947 if(r==CCREG) addr=(int)&cycle_count;
948 if(r==FSREG) addr=(int)&FCR31;
949 u_int offset = addr-(u_int)&dynarec_local;
951 assem_debug("str %s,fp+%d\n",regname[hr],offset);
952 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
955 void emit_test(int rs, int rt)
957 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
958 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
961 void emit_testimm(int rs,int imm)
964 assem_debug("tst %s,$%d\n",regname[rs],imm);
965 assert(genimm(imm,&armval));
966 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
969 void emit_testeqimm(int rs,int imm)
972 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
973 assert(genimm(imm,&armval));
974 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
977 void emit_not(int rs,int rt)
979 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
980 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
983 void emit_mvnmi(int rs,int rt)
985 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
986 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
989 void emit_and(u_int rs1,u_int rs2,u_int rt)
991 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
992 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
995 void emit_or(u_int rs1,u_int rs2,u_int rt)
997 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
998 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1000 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1002 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1003 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1006 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1011 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1012 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1015 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1017 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1018 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1021 void emit_loadlp(u_int imm,u_int rt)
1023 add_literal((int)out,imm);
1024 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
1025 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
1027 void emit_movw(u_int imm,u_int rt)
1030 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
1031 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
1033 void emit_movt(u_int imm,u_int rt)
1035 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
1036 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
1038 void emit_movimm(u_int imm,u_int rt)
1041 if(genimm(imm,&armval)) {
1042 assem_debug("mov %s,#%d\n",regname[rt],imm);
1043 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
1044 }else if(genimm(~imm,&armval)) {
1045 assem_debug("mvn %s,#%d\n",regname[rt],imm);
1046 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
1047 }else if(imm<65536) {
1049 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
1050 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
1051 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1052 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1058 emit_loadlp(imm,rt);
1060 emit_movw(imm&0x0000FFFF,rt);
1061 emit_movt(imm&0xFFFF0000,rt);
1065 void emit_pcreladdr(u_int rt)
1067 assem_debug("add %s,pc,#?\n",regname[rt]);
1068 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1071 void emit_addimm(u_int rs,int imm,u_int rt)
1076 assert(imm>-65536&&imm<65536);
1078 if(genimm(imm,&armval)) {
1079 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1080 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1081 }else if(genimm(-imm,&armval)) {
1082 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1083 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1085 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1086 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1087 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1088 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1090 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1091 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1092 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1093 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1096 else if(rs!=rt) emit_mov(rs,rt);
1099 void emit_addimm_and_set_flags(int imm,int rt)
1101 assert(imm>-65536&&imm<65536);
1103 if(genimm(imm,&armval)) {
1104 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1105 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1106 }else if(genimm(-imm,&armval)) {
1107 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1108 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1110 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1111 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1112 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1113 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1115 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1116 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1117 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1118 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1121 void emit_addimm_no_flags(u_int imm,u_int rt)
1123 emit_addimm(rt,imm,rt);
1126 void emit_addnop(u_int r)
1129 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1130 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1133 void emit_adcimm(u_int rs,int imm,u_int rt)
1136 assert(genimm(imm,&armval));
1137 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1138 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1140 /*void emit_sbcimm(int imm,u_int rt)
1143 assert(genimm(imm,&armval));
1144 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1145 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1147 void emit_sbbimm(int imm,u_int rt)
1149 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1151 if(imm<128&&imm>=-128) {
1153 output_modrm(3,rt,3);
1159 output_modrm(3,rt,3);
1163 void emit_rscimm(int rs,int imm,u_int rt)
1167 assert(genimm(imm,&armval));
1168 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1169 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1172 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1174 // TODO: if(genimm(imm,&armval)) ...
1176 emit_movimm(imm,HOST_TEMPREG);
1177 emit_adds(HOST_TEMPREG,rsl,rtl);
1178 emit_adcimm(rsh,0,rth);
1181 void emit_sbb(int rs1,int rs2)
1183 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1185 output_modrm(3,rs1,rs2);
1188 void emit_andimm(int rs,int imm,int rt)
1191 if(genimm(imm,&armval)) {
1192 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1193 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1194 }else if(genimm(~imm,&armval)) {
1195 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1196 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1197 }else if(imm==65535) {
1199 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1200 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1201 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1202 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1204 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1205 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1208 assert(imm>0&&imm<65535);
1210 assem_debug("mov r14,#%d\n",imm&0xFF00);
1211 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1212 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1213 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1215 emit_movw(imm,HOST_TEMPREG);
1217 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1218 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1222 void emit_orimm(int rs,int imm,int rt)
1225 if(genimm(imm,&armval)) {
1226 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1227 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1229 assert(imm>0&&imm<65536);
1230 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1231 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1232 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1233 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1237 void emit_xorimm(int rs,int imm,int rt)
1240 if(genimm(imm,&armval)) {
1241 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1242 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1244 assert(imm>0&&imm<65536);
1245 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1246 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1247 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1248 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1252 void emit_shlimm(int rs,u_int imm,int rt)
1257 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1258 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1261 void emit_shrimm(int rs,u_int imm,int rt)
1265 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1266 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1269 void emit_sarimm(int rs,u_int imm,int rt)
1273 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1274 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1277 void emit_rorimm(int rs,u_int imm,int rt)
1281 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1282 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1285 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1287 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1291 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1292 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1293 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1294 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1297 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1299 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1303 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1304 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1305 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1306 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1309 void emit_signextend16(int rs,int rt)
1312 emit_shlimm(rs,16,rt);
1313 emit_sarimm(rt,16,rt);
1315 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1316 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1320 void emit_shl(u_int rs,u_int shift,u_int rt)
1326 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1327 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1329 void emit_shr(u_int rs,u_int shift,u_int rt)
1334 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1335 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1337 void emit_sar(u_int rs,u_int shift,u_int rt)
1342 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1343 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1345 void emit_shlcl(int r)
1347 assem_debug("shl %%%s,%%cl\n",regname[r]);
1350 void emit_shrcl(int r)
1352 assem_debug("shr %%%s,%%cl\n",regname[r]);
1355 void emit_sarcl(int r)
1357 assem_debug("sar %%%s,%%cl\n",regname[r]);
1361 void emit_shldcl(int r1,int r2)
1363 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1366 void emit_shrdcl(int r1,int r2)
1368 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1371 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1376 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1377 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1379 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1384 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1385 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1388 void emit_cmpimm(int rs,int imm)
1391 if(genimm(imm,&armval)) {
1392 assem_debug("cmp %s,$%d\n",regname[rs],imm);
1393 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1394 }else if(genimm(-imm,&armval)) {
1395 assem_debug("cmn %s,$%d\n",regname[rs],imm);
1396 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1400 emit_movimm(imm,HOST_TEMPREG);
1402 emit_movw(imm,HOST_TEMPREG);
1404 assem_debug("cmp %s,r14\n",regname[rs]);
1405 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1409 emit_movimm(-imm,HOST_TEMPREG);
1411 emit_movw(-imm,HOST_TEMPREG);
1413 assem_debug("cmn %s,r14\n",regname[rs]);
1414 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1418 void emit_cmovne(u_int *addr,int rt)
1420 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1423 void emit_cmovl(u_int *addr,int rt)
1425 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1428 void emit_cmovs(u_int *addr,int rt)
1430 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1433 void emit_cmovne_imm(int imm,int rt)
1435 assem_debug("movne %s,#%d\n",regname[rt],imm);
1437 assert(genimm(imm,&armval));
1438 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1440 void emit_cmovl_imm(int imm,int rt)
1442 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1444 assert(genimm(imm,&armval));
1445 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1447 void emit_cmovb_imm(int imm,int rt)
1449 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1451 assert(genimm(imm,&armval));
1452 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1454 void emit_cmovs_imm(int imm,int rt)
1456 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1458 assert(genimm(imm,&armval));
1459 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1461 void emit_cmove_reg(int rs,int rt)
1463 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1464 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1466 void emit_cmovne_reg(int rs,int rt)
1468 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1469 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1471 void emit_cmovl_reg(int rs,int rt)
1473 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1474 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1476 void emit_cmovs_reg(int rs,int rt)
1478 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1479 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1482 void emit_slti32(int rs,int imm,int rt)
1484 if(rs!=rt) emit_zeroreg(rt);
1485 emit_cmpimm(rs,imm);
1486 if(rs==rt) emit_movimm(0,rt);
1487 emit_cmovl_imm(1,rt);
1489 void emit_sltiu32(int rs,int imm,int rt)
1491 if(rs!=rt) emit_zeroreg(rt);
1492 emit_cmpimm(rs,imm);
1493 if(rs==rt) emit_movimm(0,rt);
1494 emit_cmovb_imm(1,rt);
1496 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1499 emit_slti32(rsl,imm,rt);
1503 emit_cmovne_imm(0,rt);
1504 emit_cmovs_imm(1,rt);
1508 emit_cmpimm(rsh,-1);
1509 emit_cmovne_imm(0,rt);
1510 emit_cmovl_imm(1,rt);
1513 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1516 emit_sltiu32(rsl,imm,rt);
1520 emit_cmovne_imm(0,rt);
1524 emit_cmpimm(rsh,-1);
1525 emit_cmovne_imm(1,rt);
1529 void emit_cmp(int rs,int rt)
1531 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1532 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1534 void emit_set_gz32(int rs, int rt)
1536 //assem_debug("set_gz32\n");
1539 emit_cmovl_imm(0,rt);
1541 void emit_set_nz32(int rs, int rt)
1543 //assem_debug("set_nz32\n");
1544 if(rs!=rt) emit_movs(rs,rt);
1545 else emit_test(rs,rs);
1546 emit_cmovne_imm(1,rt);
1548 void emit_set_gz64_32(int rsh, int rsl, int rt)
1550 //assem_debug("set_gz64\n");
1551 emit_set_gz32(rsl,rt);
1553 emit_cmovne_imm(1,rt);
1554 emit_cmovs_imm(0,rt);
1556 void emit_set_nz64_32(int rsh, int rsl, int rt)
1558 //assem_debug("set_nz64\n");
1559 emit_or_and_set_flags(rsh,rsl,rt);
1560 emit_cmovne_imm(1,rt);
1562 void emit_set_if_less32(int rs1, int rs2, int rt)
1564 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1565 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1567 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1568 emit_cmovl_imm(1,rt);
1570 void emit_set_if_carry32(int rs1, int rs2, int rt)
1572 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1573 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1575 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1576 emit_cmovb_imm(1,rt);
1578 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1580 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1585 emit_sbcs(u1,u2,HOST_TEMPREG);
1586 emit_cmovl_imm(1,rt);
1588 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1590 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1595 emit_sbcs(u1,u2,HOST_TEMPREG);
1596 emit_cmovb_imm(1,rt);
1599 void emit_call(int a)
1601 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1602 u_int offset=genjmp(a);
1603 output_w32(0xeb000000|offset);
1605 void emit_jmp(int a)
1607 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1608 u_int offset=genjmp(a);
1609 output_w32(0xea000000|offset);
1611 void emit_jne(int a)
1613 assem_debug("bne %x\n",a);
1614 u_int offset=genjmp(a);
1615 output_w32(0x1a000000|offset);
1617 void emit_jeq(int a)
1619 assem_debug("beq %x\n",a);
1620 u_int offset=genjmp(a);
1621 output_w32(0x0a000000|offset);
1625 assem_debug("bmi %x\n",a);
1626 u_int offset=genjmp(a);
1627 output_w32(0x4a000000|offset);
1629 void emit_jns(int a)
1631 assem_debug("bpl %x\n",a);
1632 u_int offset=genjmp(a);
1633 output_w32(0x5a000000|offset);
1637 assem_debug("blt %x\n",a);
1638 u_int offset=genjmp(a);
1639 output_w32(0xba000000|offset);
1641 void emit_jge(int a)
1643 assem_debug("bge %x\n",a);
1644 u_int offset=genjmp(a);
1645 output_w32(0xaa000000|offset);
1647 void emit_jno(int a)
1649 assem_debug("bvc %x\n",a);
1650 u_int offset=genjmp(a);
1651 output_w32(0x7a000000|offset);
1655 assem_debug("bcs %x\n",a);
1656 u_int offset=genjmp(a);
1657 output_w32(0x2a000000|offset);
1659 void emit_jcc(int a)
1661 assem_debug("bcc %x\n",a);
1662 u_int offset=genjmp(a);
1663 output_w32(0x3a000000|offset);
1666 void emit_pushimm(int imm)
1668 assem_debug("push $%x\n",imm);
1673 assem_debug("pusha\n");
1678 assem_debug("popa\n");
1681 void emit_pushreg(u_int r)
1683 assem_debug("push %%%s\n",regname[r]);
1686 void emit_popreg(u_int r)
1688 assem_debug("pop %%%s\n",regname[r]);
1691 void emit_callreg(u_int r)
1693 assem_debug("call *%%%s\n",regname[r]);
1696 void emit_jmpreg(u_int r)
1698 assem_debug("mov pc,%s\n",regname[r]);
1699 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1702 void emit_readword_indexed(int offset, int rs, int rt)
1704 assert(offset>-4096&&offset<4096);
1705 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1707 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1709 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1712 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1714 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1715 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1717 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1719 if(map<0) emit_readword_indexed(addr, rs, rt);
1722 emit_readword_dualindexedx4(rs, map, rt);
1725 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1728 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1729 emit_readword_indexed(addr+4, rs, rl);
1732 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1733 emit_addimm(map,1,map);
1734 emit_readword_indexed_tlb(addr, rs, map, rl);
1737 void emit_movsbl_indexed(int offset, int rs, int rt)
1739 assert(offset>-256&&offset<256);
1740 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1742 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1744 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1747 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1749 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1752 emit_shlimm(map,2,map);
1753 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1754 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1756 assert(addr>-256&&addr<256);
1757 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1758 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1759 emit_movsbl_indexed(addr, rt, rt);
1763 void emit_movswl_indexed(int offset, int rs, int rt)
1765 assert(offset>-256&&offset<256);
1766 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1768 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1770 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1773 void emit_movzbl_indexed(int offset, int rs, int rt)
1775 assert(offset>-4096&&offset<4096);
1776 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1778 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1780 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1783 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1785 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1786 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1788 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1790 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1793 emit_movzbl_dualindexedx4(rs, map, rt);
1795 emit_addimm(rs,addr,rt);
1796 emit_movzbl_dualindexedx4(rt, map, rt);
1800 void emit_movzwl_indexed(int offset, int rs, int rt)
1802 assert(offset>-256&&offset<256);
1803 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1805 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1807 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1810 void emit_readword(int addr, int rt)
1812 u_int offset = addr-(u_int)&dynarec_local;
1813 assert(offset<4096);
1814 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1815 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1817 void emit_movsbl(int addr, int rt)
1819 u_int offset = addr-(u_int)&dynarec_local;
1821 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1822 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1824 void emit_movswl(int addr, int rt)
1826 u_int offset = addr-(u_int)&dynarec_local;
1828 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1829 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1831 void emit_movzbl(int addr, int rt)
1833 u_int offset = addr-(u_int)&dynarec_local;
1834 assert(offset<4096);
1835 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1836 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1838 void emit_movzwl(int addr, int rt)
1840 u_int offset = addr-(u_int)&dynarec_local;
1842 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1843 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1845 void emit_movzwl_reg(int rs, int rt)
1847 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1851 void emit_xchg(int rs, int rt)
1853 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1856 void emit_writeword_indexed(int rt, int offset, int rs)
1858 assert(offset>-4096&&offset<4096);
1859 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1861 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1863 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1866 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1868 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1869 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1871 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1873 if(map<0) emit_writeword_indexed(rt, addr, rs);
1876 emit_writeword_dualindexedx4(rt, rs, map);
1879 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1882 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1883 emit_writeword_indexed(rl, addr+4, rs);
1886 if(temp!=rs) emit_addimm(map,1,temp);
1887 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1888 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1890 emit_addimm(rs,4,rs);
1891 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1895 void emit_writehword_indexed(int rt, int offset, int rs)
1897 assert(offset>-256&&offset<256);
1898 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1900 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1902 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1905 void emit_writebyte_indexed(int rt, int offset, int rs)
1907 assert(offset>-4096&&offset<4096);
1908 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
1910 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
1912 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
1915 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
1917 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1918 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1920 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1922 if(map<0) emit_writebyte_indexed(rt, addr, rs);
1925 emit_writebyte_dualindexedx4(rt, rs, map);
1927 emit_addimm(rs,addr,temp);
1928 emit_writebyte_dualindexedx4(rt, temp, map);
1932 void emit_writeword(int rt, int addr)
1934 u_int offset = addr-(u_int)&dynarec_local;
1935 assert(offset<4096);
1936 assem_debug("str %s,fp+%d\n",regname[rt],offset);
1937 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
1939 void emit_writehword(int rt, int addr)
1941 u_int offset = addr-(u_int)&dynarec_local;
1943 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
1944 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1946 void emit_writebyte(int rt, int addr)
1948 u_int offset = addr-(u_int)&dynarec_local;
1949 assert(offset<4096);
1950 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
1951 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
1953 void emit_writeword_imm(int imm, int addr)
1955 assem_debug("movl $%x,%x\n",imm,addr);
1958 void emit_writebyte_imm(int imm, int addr)
1960 assem_debug("movb $%x,%x\n",imm,addr);
1964 void emit_mul(int rs)
1966 assem_debug("mul %%%s\n",regname[rs]);
1969 void emit_imul(int rs)
1971 assem_debug("imul %%%s\n",regname[rs]);
1974 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
1976 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
1981 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
1983 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
1985 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
1990 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
1993 void emit_div(int rs)
1995 assem_debug("div %%%s\n",regname[rs]);
1998 void emit_idiv(int rs)
2000 assem_debug("idiv %%%s\n",regname[rs]);
2005 assem_debug("cdq\n");
2009 void emit_clz(int rs,int rt)
2011 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2012 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2015 void emit_subcs(int rs1,int rs2,int rt)
2017 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2018 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2021 void emit_shrcc_imm(int rs,u_int imm,int rt)
2025 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2026 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2029 void emit_negmi(int rs, int rt)
2031 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2032 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2035 void emit_negsmi(int rs, int rt)
2037 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2038 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2041 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2043 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2044 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2047 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2049 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2050 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2053 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2055 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2056 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2059 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2061 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2062 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2065 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2067 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2068 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2071 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2073 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2074 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2077 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2079 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2080 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2083 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2085 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2086 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2089 void emit_teq(int rs, int rt)
2091 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2092 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2095 void emit_rsbimm(int rs, int imm, int rt)
2098 assert(genimm(imm,&armval));
2099 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2100 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2103 // Load 2 immediates optimizing for small code size
2104 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2106 emit_movimm(imm1,rt1);
2108 if(genimm(imm2-imm1,&armval)) {
2109 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2110 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2111 }else if(genimm(imm1-imm2,&armval)) {
2112 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2113 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2115 else emit_movimm(imm2,rt2);
2118 // Conditionally select one of two immediates, optimizing for small code size
2119 // This will only be called if HAVE_CMOV_IMM is defined
2120 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2123 if(genimm(imm2-imm1,&armval)) {
2124 emit_movimm(imm1,rt);
2125 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2126 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2127 }else if(genimm(imm1-imm2,&armval)) {
2128 emit_movimm(imm1,rt);
2129 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2130 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2134 emit_movimm(imm1,rt);
2135 add_literal((int)out,imm2);
2136 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2137 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2139 emit_movw(imm1&0x0000FFFF,rt);
2140 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2141 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2142 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2144 emit_movt(imm1&0xFFFF0000,rt);
2145 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2146 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2147 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2153 // special case for checking invalid_code
2154 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2159 // special case for checking invalid_code
2160 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2162 assert(imm<128&&imm>=0);
2164 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2165 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2166 emit_cmpimm(HOST_TEMPREG,imm);
2169 // special case for tlb mapping
2170 void emit_addsr12(int rs1,int rs2,int rt)
2172 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2173 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2176 // Used to preload hash table entries
2177 void emit_prefetch(void *addr)
2179 assem_debug("prefetch %x\n",(int)addr);
2182 output_modrm(0,5,1);
2183 output_w32((int)addr);
2185 void emit_prefetchreg(int r)
2187 assem_debug("pld %s\n",regname[r]);
2188 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2191 // Special case for mini_ht
2192 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2194 assert(offset<4096);
2195 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2196 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2199 void emit_flds(int r,int sr)
2201 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2202 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2205 void emit_vldr(int r,int vr)
2207 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2208 output_w32(0xed900b00|(vr<<12)|(r<<16));
2211 void emit_fsts(int sr,int r)
2213 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2214 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2217 void emit_vstr(int vr,int r)
2219 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2220 output_w32(0xed800b00|(vr<<12)|(r<<16));
2223 void emit_ftosizs(int s,int d)
2225 assem_debug("ftosizs s%d,s%d\n",d,s);
2226 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2229 void emit_ftosizd(int s,int d)
2231 assem_debug("ftosizd s%d,d%d\n",d,s);
2232 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2235 void emit_fsitos(int s,int d)
2237 assem_debug("fsitos s%d,s%d\n",d,s);
2238 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2241 void emit_fsitod(int s,int d)
2243 assem_debug("fsitod d%d,s%d\n",d,s);
2244 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2247 void emit_fcvtds(int s,int d)
2249 assem_debug("fcvtds d%d,s%d\n",d,s);
2250 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2253 void emit_fcvtsd(int s,int d)
2255 assem_debug("fcvtsd s%d,d%d\n",d,s);
2256 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2259 void emit_fsqrts(int s,int d)
2261 assem_debug("fsqrts d%d,s%d\n",d,s);
2262 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2265 void emit_fsqrtd(int s,int d)
2267 assem_debug("fsqrtd s%d,d%d\n",d,s);
2268 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2271 void emit_fabss(int s,int d)
2273 assem_debug("fabss d%d,s%d\n",d,s);
2274 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2277 void emit_fabsd(int s,int d)
2279 assem_debug("fabsd s%d,d%d\n",d,s);
2280 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2283 void emit_fnegs(int s,int d)
2285 assem_debug("fnegs d%d,s%d\n",d,s);
2286 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2289 void emit_fnegd(int s,int d)
2291 assem_debug("fnegd s%d,d%d\n",d,s);
2292 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2295 void emit_fadds(int s1,int s2,int d)
2297 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2298 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2301 void emit_faddd(int s1,int s2,int d)
2303 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2304 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2307 void emit_fsubs(int s1,int s2,int d)
2309 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2310 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2313 void emit_fsubd(int s1,int s2,int d)
2315 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2316 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2319 void emit_fmuls(int s1,int s2,int d)
2321 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2322 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2325 void emit_fmuld(int s1,int s2,int d)
2327 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2328 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2331 void emit_fdivs(int s1,int s2,int d)
2333 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2334 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2337 void emit_fdivd(int s1,int s2,int d)
2339 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2340 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2343 void emit_fcmps(int x,int y)
2345 assem_debug("fcmps s14, s15\n");
2346 output_w32(0xeeb47a67);
2349 void emit_fcmpd(int x,int y)
2351 assem_debug("fcmpd d6, d7\n");
2352 output_w32(0xeeb46b47);
2357 assem_debug("fmstat\n");
2358 output_w32(0xeef1fa10);
2361 void emit_bicne_imm(int rs,int imm,int rt)
2364 assert(genimm(imm,&armval));
2365 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2366 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2369 void emit_biccs_imm(int rs,int imm,int rt)
2372 assert(genimm(imm,&armval));
2373 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2374 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2377 void emit_bicvc_imm(int rs,int imm,int rt)
2380 assert(genimm(imm,&armval));
2381 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2382 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2385 void emit_bichi_imm(int rs,int imm,int rt)
2388 assert(genimm(imm,&armval));
2389 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2390 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2393 void emit_orrvs_imm(int rs,int imm,int rt)
2396 assert(genimm(imm,&armval));
2397 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2398 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2401 void emit_orrne_imm(int rs,int imm,int rt)
2404 assert(genimm(imm,&armval));
2405 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2406 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2409 void emit_andne_imm(int rs,int imm,int rt)
2412 assert(genimm(imm,&armval));
2413 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2414 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2417 void emit_jno_unlikely(int a)
2420 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2421 output_w32(0x72800000|rd_rn_rm(15,15,0));
2424 // Save registers before function call
2425 void save_regs(u_int reglist)
2427 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2428 if(!reglist) return;
2429 assem_debug("stmia fp,{");
2430 if(reglist&1) assem_debug("r0, ");
2431 if(reglist&2) assem_debug("r1, ");
2432 if(reglist&4) assem_debug("r2, ");
2433 if(reglist&8) assem_debug("r3, ");
2434 if(reglist&0x1000) assem_debug("r12");
2436 output_w32(0xe88b0000|reglist);
2438 // Restore registers after function call
2439 void restore_regs(u_int reglist)
2441 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2442 if(!reglist) return;
2443 assem_debug("ldmia fp,{");
2444 if(reglist&1) assem_debug("r0, ");
2445 if(reglist&2) assem_debug("r1, ");
2446 if(reglist&4) assem_debug("r2, ");
2447 if(reglist&8) assem_debug("r3, ");
2448 if(reglist&0x1000) assem_debug("r12");
2450 output_w32(0xe89b0000|reglist);
2453 // Write back consts using r14 so we don't disturb the other registers
2454 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2457 for(hr=0;hr<HOST_REGS;hr++) {
2458 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2459 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2460 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2461 int value=constmap[i][hr];
2463 emit_zeroreg(HOST_TEMPREG);
2466 emit_movimm(value,HOST_TEMPREG);
2468 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2470 if((i_is32>>i_regmap[hr])&1) {
2471 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2472 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2481 /* Stubs/epilogue */
2483 void literal_pool(int n)
2485 if(!literalcount) return;
2487 if((int)out-literals[0][0]<4096-n) return;
2491 for(i=0;i<literalcount;i++)
2493 ptr=(u_int *)literals[i][0];
2494 u_int offset=(u_int)out-(u_int)ptr-8;
2495 assert(offset<4096);
2496 assert(!(offset&3));
2498 output_w32(literals[i][1]);
2503 void literal_pool_jumpover(int n)
2505 if(!literalcount) return;
2507 if((int)out-literals[0][0]<4096-n) return;
2512 set_jump_target(jaddr,(int)out);
2515 emit_extjump2(int addr, int target, int linker)
2517 u_char *ptr=(u_char *)addr;
2518 assert((ptr[3]&0x0e)==0xa);
2519 emit_loadlp(target,0);
2520 emit_loadlp(addr,1);
2521 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2522 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2524 #ifdef DEBUG_CYCLE_COUNT
2525 emit_readword((int)&last_count,ECX);
2526 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2527 emit_readword((int)&next_interupt,ECX);
2528 emit_writeword(HOST_CCREG,(int)&Count);
2529 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2530 emit_writeword(ECX,(int)&last_count);
2536 emit_extjump(int addr, int target)
2538 emit_extjump2(addr, target, (int)dyna_linker);
2540 emit_extjump_ds(int addr, int target)
2542 emit_extjump2(addr, target, (int)dyna_linker_ds);
2547 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2549 set_jump_target(stubs[n][1],(int)out);
2550 int type=stubs[n][0];
2553 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2554 u_int reglist=stubs[n][7];
2555 signed char *i_regmap=i_regs->regmap;
2556 int addr=get_reg(i_regmap,AGEN1+(i&1));
2559 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2560 rth=get_reg(i_regmap,FTEMP|64);
2561 rt=get_reg(i_regmap,FTEMP);
2563 rth=get_reg(i_regmap,rt1[i]|64);
2564 rt=get_reg(i_regmap,rt1[i]);
2569 // assume dummy read, no alloced reg
2570 addr=get_reg(i_regmap,-1);
2573 if(type==LOADB_STUB||type==LOADBU_STUB)
2574 ftable=(int)readmemb;
2575 if(type==LOADH_STUB||type==LOADHU_STUB)
2576 ftable=(int)readmemh;
2577 if(type==LOADW_STUB)
2578 ftable=(int)readmem;
2580 if(type==LOADD_STUB)
2581 ftable=(int)readmemd;
2584 emit_writeword(rs,(int)&address);
2587 ds=i_regs!=®s[i];
2588 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2589 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2590 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2591 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2592 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2593 emit_shrimm(rs,16,1);
2594 int cc=get_reg(i_regmap,CCREG);
2596 emit_loadreg(CCREG,2);
2598 emit_movimm(ftable,0);
2599 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2600 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2601 //emit_readword((int)&last_count,temp);
2602 //emit_add(cc,temp,cc);
2603 //emit_writeword(cc,(int)&Count);
2605 emit_call((int)&indirect_jump_indexed);
2607 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2608 // We really shouldn't need to update the count here,
2609 // but not doing so causes random crashes...
2610 emit_readword((int)&Count,HOST_TEMPREG);
2611 emit_readword((int)&next_interupt,2);
2612 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2613 emit_writeword(2,(int)&last_count);
2614 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2616 emit_storereg(CCREG,HOST_TEMPREG);
2619 restore_regs(reglist);
2620 //if((cc=get_reg(regmap,CCREG))>=0) {
2621 // emit_loadreg(CCREG,cc);
2623 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2625 if(type==LOADB_STUB)
2626 emit_movsbl((int)&readmem_dword,rt);
2627 if(type==LOADBU_STUB)
2628 emit_movzbl((int)&readmem_dword,rt);
2629 if(type==LOADH_STUB)
2630 emit_movswl((int)&readmem_dword,rt);
2631 if(type==LOADHU_STUB)
2632 emit_movzwl((int)&readmem_dword,rt);
2633 if(type==LOADW_STUB)
2634 emit_readword((int)&readmem_dword,rt);
2635 if(type==LOADD_STUB) {
2636 emit_readword((int)&readmem_dword,rt);
2637 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2640 emit_jmp(stubs[n][2]); // return address
2643 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2645 int rs=get_reg(regmap,target);
2646 int rth=get_reg(regmap,target|64);
2647 int rt=get_reg(regmap,target);
2651 if(type==LOADB_STUB||type==LOADBU_STUB)
2652 ftable=(int)readmemb;
2653 if(type==LOADH_STUB||type==LOADHU_STUB)
2654 ftable=(int)readmemh;
2655 if(type==LOADW_STUB)
2656 ftable=(int)readmem;
2658 if(type==LOADD_STUB)
2659 ftable=(int)readmemd;
2662 emit_writeword(rs,(int)&address);
2665 //emit_shrimm(rs,16,1);
2666 int cc=get_reg(regmap,CCREG);
2668 emit_loadreg(CCREG,2);
2670 //emit_movimm(ftable,0);
2671 emit_movimm(((u_int *)ftable)[addr>>16],0);
2672 //emit_readword((int)&last_count,12);
2673 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2674 if((signed int)addr>=(signed int)0xC0000000) {
2675 // Pagefault address
2676 int ds=regmap!=regs[i].regmap;
2677 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2680 //emit_writeword(2,(int)&Count);
2681 //emit_call(((u_int *)ftable)[addr>>16]);
2682 emit_call((int)&indirect_jump);
2683 // We really shouldn't need to update the count here,
2684 // but not doing so causes random crashes...
2685 emit_readword((int)&Count,HOST_TEMPREG);
2686 emit_readword((int)&next_interupt,2);
2687 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2688 emit_writeword(2,(int)&last_count);
2689 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2691 emit_storereg(CCREG,HOST_TEMPREG);
2694 restore_regs(reglist);
2695 if(type==LOADB_STUB)
2696 emit_movsbl((int)&readmem_dword,rt);
2697 if(type==LOADBU_STUB)
2698 emit_movzbl((int)&readmem_dword,rt);
2699 if(type==LOADH_STUB)
2700 emit_movswl((int)&readmem_dword,rt);
2701 if(type==LOADHU_STUB)
2702 emit_movzwl((int)&readmem_dword,rt);
2703 if(type==LOADW_STUB)
2704 emit_readword((int)&readmem_dword,rt);
2705 if(type==LOADD_STUB) {
2706 emit_readword((int)&readmem_dword,rt);
2707 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2713 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2715 set_jump_target(stubs[n][1],(int)out);
2716 int type=stubs[n][0];
2719 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2720 u_int reglist=stubs[n][7];
2721 signed char *i_regmap=i_regs->regmap;
2722 int addr=get_reg(i_regmap,AGEN1+(i&1));
2725 if(itype[i]==C1LS||itype[i]==C2LS) {
2726 rth=get_reg(i_regmap,FTEMP|64);
2727 rt=get_reg(i_regmap,r=FTEMP);
2729 rth=get_reg(i_regmap,rs2[i]|64);
2730 rt=get_reg(i_regmap,r=rs2[i]);
2734 if(addr<0) addr=get_reg(i_regmap,-1);
2737 if(type==STOREB_STUB)
2738 ftable=(int)writememb;
2739 if(type==STOREH_STUB)
2740 ftable=(int)writememh;
2741 if(type==STOREW_STUB)
2742 ftable=(int)writemem;
2744 if(type==STORED_STUB)
2745 ftable=(int)writememd;
2748 emit_writeword(rs,(int)&address);
2749 //emit_shrimm(rs,16,rs);
2750 //emit_movmem_indexedx4(ftable,rs,rs);
2751 if(type==STOREB_STUB)
2752 emit_writebyte(rt,(int)&byte);
2753 if(type==STOREH_STUB)
2754 emit_writehword(rt,(int)&hword);
2755 if(type==STOREW_STUB)
2756 emit_writeword(rt,(int)&word);
2757 if(type==STORED_STUB) {
2759 emit_writeword(rt,(int)&dword);
2760 emit_writeword(r?rth:rt,(int)&dword+4);
2762 printf("STORED_STUB\n");
2767 ds=i_regs!=®s[i];
2768 int real_rs=get_reg(i_regmap,rs1[i]);
2769 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2770 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2771 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2772 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2773 emit_shrimm(rs,16,1);
2774 int cc=get_reg(i_regmap,CCREG);
2776 emit_loadreg(CCREG,2);
2778 emit_movimm(ftable,0);
2779 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2780 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2781 //emit_readword((int)&last_count,temp);
2782 //emit_addimm(cc,2*stubs[n][5]+2,cc);
2783 //emit_add(cc,temp,cc);
2784 //emit_writeword(cc,(int)&Count);
2785 emit_call((int)&indirect_jump_indexed);
2787 emit_readword((int)&Count,HOST_TEMPREG);
2788 emit_readword((int)&next_interupt,2);
2789 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2790 emit_writeword(2,(int)&last_count);
2791 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2793 emit_storereg(CCREG,HOST_TEMPREG);
2796 restore_regs(reglist);
2797 //if((cc=get_reg(regmap,CCREG))>=0) {
2798 // emit_loadreg(CCREG,cc);
2800 emit_jmp(stubs[n][2]); // return address
2803 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2805 int rs=get_reg(regmap,-1);
2806 int rth=get_reg(regmap,target|64);
2807 int rt=get_reg(regmap,target);
2811 if(type==STOREB_STUB)
2812 ftable=(int)writememb;
2813 if(type==STOREH_STUB)
2814 ftable=(int)writememh;
2815 if(type==STOREW_STUB)
2816 ftable=(int)writemem;
2818 if(type==STORED_STUB)
2819 ftable=(int)writememd;
2822 emit_writeword(rs,(int)&address);
2823 //emit_shrimm(rs,16,rs);
2824 //emit_movmem_indexedx4(ftable,rs,rs);
2825 if(type==STOREB_STUB)
2826 emit_writebyte(rt,(int)&byte);
2827 if(type==STOREH_STUB)
2828 emit_writehword(rt,(int)&hword);
2829 if(type==STOREW_STUB)
2830 emit_writeword(rt,(int)&word);
2831 if(type==STORED_STUB) {
2833 emit_writeword(rt,(int)&dword);
2834 emit_writeword(target?rth:rt,(int)&dword+4);
2836 printf("STORED_STUB\n");
2841 //emit_shrimm(rs,16,1);
2842 int cc=get_reg(regmap,CCREG);
2844 emit_loadreg(CCREG,2);
2846 //emit_movimm(ftable,0);
2847 emit_movimm(((u_int *)ftable)[addr>>16],0);
2848 //emit_readword((int)&last_count,12);
2849 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2850 if((signed int)addr>=(signed int)0xC0000000) {
2851 // Pagefault address
2852 int ds=regmap!=regs[i].regmap;
2853 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2856 //emit_writeword(2,(int)&Count);
2857 //emit_call(((u_int *)ftable)[addr>>16]);
2858 emit_call((int)&indirect_jump);
2859 emit_readword((int)&Count,HOST_TEMPREG);
2860 emit_readword((int)&next_interupt,2);
2861 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2862 emit_writeword(2,(int)&last_count);
2863 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2865 emit_storereg(CCREG,HOST_TEMPREG);
2868 restore_regs(reglist);
2871 do_unalignedwritestub(int n)
2873 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2875 set_jump_target(stubs[n][1],(int)out);
2878 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2879 int addr=stubs[n][5];
2880 u_int reglist=stubs[n][7];
2881 signed char *i_regmap=i_regs->regmap;
2882 int temp2=get_reg(i_regmap,FTEMP);
2885 rt=get_reg(i_regmap,rs2[i]);
2888 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2890 reglist&=~(1<<temp2);
2892 emit_andimm(addr,0xfffffffc,temp2);
2893 emit_writeword(temp2,(int)&address);
2896 ds=i_regs!=®s[i];
2897 real_rs=get_reg(i_regmap,rs1[i]);
2898 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2899 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2900 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2901 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2902 emit_shrimm(addr,16,1);
2903 int cc=get_reg(i_regmap,CCREG);
2905 emit_loadreg(CCREG,2);
2907 emit_movimm((u_int)readmem,0);
2908 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2909 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); // XXX: can be rm'd?
2910 emit_call((int)&indirect_jump_indexed);
2911 restore_regs(reglist);
2913 emit_readword((int)&readmem_dword,temp2);
2914 int temp=addr; //hmh
2915 emit_shlimm(addr,3,temp);
2916 emit_andimm(temp,24,temp);
2917 #ifdef BIG_ENDIAN_MIPS
2918 if (opcode[i]==0x2e) // SWR
2920 if (opcode[i]==0x2a) // SWL
2922 emit_xorimm(temp,24,temp);
2923 emit_movimm(-1,HOST_TEMPREG);
2924 if (opcode[i]==0x2a) { // SWL
2925 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
2926 emit_orrshr(rt,temp,temp2);
2928 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
2929 emit_orrshl(rt,temp,temp2);
2931 emit_readword((int)&address,addr);
2932 emit_writeword(temp2,(int)&word);
2933 //save_regs(reglist); // don't need to, no state changes
2934 emit_shrimm(addr,16,1);
2935 emit_movimm((u_int)writemem,0);
2936 //emit_call((int)&indirect_jump_indexed);
2938 emit_readword_dualindexedx4(0,1,15);
2939 emit_readword((int)&Count,HOST_TEMPREG);
2940 emit_readword((int)&next_interupt,2);
2941 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2942 emit_writeword(2,(int)&last_count);
2943 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2945 emit_storereg(CCREG,HOST_TEMPREG);
2947 restore_regs(reglist);
2948 emit_jmp(stubs[n][2]); // return address
2951 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
2953 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
2959 u_int reglist=stubs[n][3];
2960 set_jump_target(stubs[n][1],(int)out);
2962 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2963 emit_call((int)&invalidate_addr);
2964 restore_regs(reglist);
2965 emit_jmp(stubs[n][2]); // return address
2968 int do_dirty_stub(int i)
2970 assem_debug("do_dirty_stub %x\n",start+i*4);
2971 u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
2975 // Careful about the code output here, verify_dirty needs to parse it.
2977 emit_loadlp(addr,1);
2978 emit_loadlp((int)copy,2);
2979 emit_loadlp(slen*4,3);
2981 emit_movw(addr&0x0000FFFF,1);
2982 emit_movw(((u_int)copy)&0x0000FFFF,2);
2983 emit_movt(addr&0xFFFF0000,1);
2984 emit_movt(((u_int)copy)&0xFFFF0000,2);
2985 emit_movw(slen*4,3);
2987 emit_movimm(start+i*4,0);
2988 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
2991 if(entry==(int)out) entry=instr_addr[i];
2992 emit_jmp(instr_addr[i]);
2996 void do_dirty_stub_ds()
2998 // Careful about the code output here, verify_dirty needs to parse it.
3000 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3001 emit_loadlp((int)copy,2);
3002 emit_loadlp(slen*4,3);
3004 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3005 emit_movw(((u_int)copy)&0x0000FFFF,2);
3006 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3007 emit_movt(((u_int)copy)&0xFFFF0000,2);
3008 emit_movw(slen*4,3);
3010 emit_movimm(start+1,0);
3011 emit_call((int)&verify_code_ds);
3017 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3018 set_jump_target(stubs[n][1],(int)out);
3020 // int rs=stubs[n][4];
3021 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3024 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3025 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3027 //else {printf("fp exception in delay slot\n");}
3028 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3029 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3030 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3031 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3032 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3037 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3040 if((signed int)addr>=(signed int)0xC0000000) {
3041 // address_generation already loaded the const
3042 emit_readword_dualindexedx4(FP,map,map);
3045 return -1; // No mapping
3049 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3050 emit_addsr12(map,s,map);
3051 // Schedule this while we wait on the load
3052 //if(x) emit_xorimm(s,x,ar);
3053 if(shift>=0) emit_shlimm(s,3,shift);
3054 if(~a) emit_andimm(s,a,ar);
3055 emit_readword_dualindexedx4(FP,map,map);
3059 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3061 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3069 int gen_tlb_addr_r(int ar, int map) {
3071 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3072 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3076 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3079 if(addr<0x80800000||addr>=0xC0000000) {
3080 // address_generation already loaded the const
3081 emit_readword_dualindexedx4(FP,map,map);
3084 return -1; // No mapping
3088 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3089 emit_addsr12(map,s,map);
3090 // Schedule this while we wait on the load
3091 //if(x) emit_xorimm(s,x,ar);
3092 emit_readword_dualindexedx4(FP,map,map);
3096 int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
3098 if(!c||addr<0x80800000||addr>=0xC0000000) {
3099 emit_testimm(map,0x40000000);
3105 int gen_tlb_addr_w(int ar, int map) {
3107 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3108 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3112 // Generate the address of the memory_map entry, relative to dynarec_local
3113 generate_map_const(u_int addr,int reg) {
3114 //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
3115 emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
3120 void shift_assemble_arm(int i,struct regstat *i_regs)
3123 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3125 signed char s,t,shift;
3126 t=get_reg(i_regs->regmap,rt1[i]);
3127 s=get_reg(i_regs->regmap,rs1[i]);
3128 shift=get_reg(i_regs->regmap,rs2[i]);
3137 if(s!=t) emit_mov(s,t);
3141 emit_andimm(shift,31,HOST_TEMPREG);
3142 if(opcode2[i]==4) // SLLV
3144 emit_shl(s,HOST_TEMPREG,t);
3146 if(opcode2[i]==6) // SRLV
3148 emit_shr(s,HOST_TEMPREG,t);
3150 if(opcode2[i]==7) // SRAV
3152 emit_sar(s,HOST_TEMPREG,t);
3156 } else { // DSLLV/DSRLV/DSRAV
3157 signed char sh,sl,th,tl,shift;
3158 th=get_reg(i_regs->regmap,rt1[i]|64);
3159 tl=get_reg(i_regs->regmap,rt1[i]);
3160 sh=get_reg(i_regs->regmap,rs1[i]|64);
3161 sl=get_reg(i_regs->regmap,rs1[i]);
3162 shift=get_reg(i_regs->regmap,rs2[i]);
3167 if(th>=0) emit_zeroreg(th);
3172 if(sl!=tl) emit_mov(sl,tl);
3173 if(th>=0&&sh!=th) emit_mov(sh,th);
3177 // FIXME: What if shift==tl ?
3179 int temp=get_reg(i_regs->regmap,-1);
3181 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3184 emit_andimm(shift,31,HOST_TEMPREG);
3185 if(opcode2[i]==0x14) // DSLLV
3187 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3188 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3189 emit_orrshr(sl,HOST_TEMPREG,th);
3190 emit_andimm(shift,31,HOST_TEMPREG);
3191 emit_testimm(shift,32);
3192 emit_shl(sl,HOST_TEMPREG,tl);
3193 if(th>=0) emit_cmovne_reg(tl,th);
3194 emit_cmovne_imm(0,tl);
3196 if(opcode2[i]==0x16) // DSRLV
3199 emit_shr(sl,HOST_TEMPREG,tl);
3200 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3201 emit_orrshl(sh,HOST_TEMPREG,tl);
3202 emit_andimm(shift,31,HOST_TEMPREG);
3203 emit_testimm(shift,32);
3204 emit_shr(sh,HOST_TEMPREG,th);
3205 emit_cmovne_reg(th,tl);
3206 if(real_th>=0) emit_cmovne_imm(0,th);
3208 if(opcode2[i]==0x17) // DSRAV
3211 emit_shr(sl,HOST_TEMPREG,tl);
3212 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3215 emit_sarimm(th,31,temp);
3217 emit_orrshl(sh,HOST_TEMPREG,tl);
3218 emit_andimm(shift,31,HOST_TEMPREG);
3219 emit_testimm(shift,32);
3220 emit_sar(sh,HOST_TEMPREG,th);
3221 emit_cmovne_reg(th,tl);
3222 if(real_th>=0) emit_cmovne_reg(temp,th);
3229 #define shift_assemble shift_assemble_arm
3231 void loadlr_assemble_arm(int i,struct regstat *i_regs)
3233 int s,th,tl,temp,temp2,addr,map=-1;
3238 th=get_reg(i_regs->regmap,rt1[i]|64);
3239 tl=get_reg(i_regs->regmap,rt1[i]);
3240 s=get_reg(i_regs->regmap,rs1[i]);
3241 temp=get_reg(i_regs->regmap,-1);
3242 temp2=get_reg(i_regs->regmap,FTEMP);
3243 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3246 for(hr=0;hr<HOST_REGS;hr++) {
3247 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3250 if(offset||s<0||c) addr=temp2;
3253 c=(i_regs->wasconst>>s)&1;
3254 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3255 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3262 emit_shlimm(addr,3,temp);
3263 if (opcode[i]==0x22||opcode[i]==0x26) {
3264 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3266 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3268 emit_cmpimm(addr,RAM_SIZE);
3273 if (opcode[i]==0x22||opcode[i]==0x26) {
3274 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3276 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3283 }else if (opcode[i]==0x22||opcode[i]==0x26) {
3284 a=0xFFFFFFFC; // LWL/LWR
3286 a=0xFFFFFFF8; // LDL/LDR
3288 map=get_reg(i_regs->regmap,TLREG);
3290 map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
3292 if (opcode[i]==0x22||opcode[i]==0x26) {
3293 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3295 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3298 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
3300 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3302 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3303 emit_readword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2);
3304 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3307 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3308 emit_andimm(temp,24,temp);
3309 #ifdef BIG_ENDIAN_MIPS
3310 if (opcode[i]==0x26) // LWR
3312 if (opcode[i]==0x22) // LWL
3314 emit_xorimm(temp,24,temp);
3315 emit_movimm(-1,HOST_TEMPREG);
3316 if (opcode[i]==0x26) {
3317 emit_shr(temp2,temp,temp2);
3318 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3320 emit_shl(temp2,temp,temp2);
3321 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3323 emit_or(temp2,tl,tl);
3324 //emit_storereg(rt1[i],tl); // DEBUG
3326 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3327 // FIXME: little endian
3328 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3330 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3331 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3332 emit_readdword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2h,temp2);
3333 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3336 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3337 emit_testimm(temp,32);
3338 emit_andimm(temp,24,temp);
3339 if (opcode[i]==0x1A) { // LDL
3340 emit_rsbimm(temp,32,HOST_TEMPREG);
3341 emit_shl(temp2h,temp,temp2h);
3342 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3343 emit_movimm(-1,HOST_TEMPREG);
3344 emit_shl(temp2,temp,temp2);
3345 emit_cmove_reg(temp2h,th);
3346 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3347 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3348 emit_orreq(temp2,tl,tl);
3349 emit_orrne(temp2,th,th);
3351 if (opcode[i]==0x1B) { // LDR
3352 emit_xorimm(temp,24,temp);
3353 emit_rsbimm(temp,32,HOST_TEMPREG);
3354 emit_shr(temp2,temp,temp2);
3355 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3356 emit_movimm(-1,HOST_TEMPREG);
3357 emit_shr(temp2h,temp,temp2h);
3358 emit_cmovne_reg(temp2,tl);
3359 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3360 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3361 emit_orrne(temp2h,th,th);
3362 emit_orreq(temp2h,tl,tl);
3367 #define loadlr_assemble loadlr_assemble_arm
3369 void cop0_assemble(int i,struct regstat *i_regs)
3371 if(opcode2[i]==0) // MFC0
3373 signed char t=get_reg(i_regs->regmap,rt1[i]);
3374 char copr=(source[i]>>11)&0x1f;
3375 //assert(t>=0); // Why does this happen? OOT is weird
3378 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3379 emit_movimm((source[i]>>11)&0x1f,1);
3380 emit_writeword(0,(int)&PC);
3381 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3383 emit_readword((int)&last_count,ECX);
3384 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3385 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3386 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3387 emit_writeword(HOST_CCREG,(int)&Count);
3389 emit_call((int)MFC0);
3390 emit_readword((int)&readmem_dword,t);
3392 emit_readword((int)®_cop0+copr*4,t);
3396 else if(opcode2[i]==4) // MTC0
3398 signed char s=get_reg(i_regs->regmap,rs1[i]);
3399 char copr=(source[i]>>11)&0x1f;
3401 emit_writeword(s,(int)&readmem_dword);
3402 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3403 #ifdef MUPEN64 /// FIXME
3404 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3405 emit_movimm((source[i]>>11)&0x1f,1);
3406 emit_writeword(0,(int)&PC);
3407 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3410 emit_movimm(source[i],0);
3411 emit_writeword(0,(int)&psxRegs.code);
3413 if(copr==9||copr==11||copr==12||copr==13) {
3414 emit_readword((int)&last_count,ECX);
3415 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3416 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3417 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3418 emit_writeword(HOST_CCREG,(int)&Count);
3420 // What a mess. The status register (12) can enable interrupts,
3421 // so needs a special case to handle a pending interrupt.
3422 // The interrupt must be taken immediately, because a subsequent
3423 // instruction might disable interrupts again.
3424 if(copr==12||copr==13) {
3425 emit_movimm(start+i*4+4,0);
3427 emit_writeword(0,(int)&pcaddr);
3428 emit_writeword(1,(int)&pending_exception);
3430 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3432 emit_call((int)MTC0);
3433 if(copr==9||copr==11||copr==12||copr==13) {
3434 emit_readword((int)&Count,HOST_CCREG);
3435 emit_readword((int)&next_interupt,ECX);
3436 emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3437 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
3438 emit_writeword(ECX,(int)&last_count);
3439 emit_storereg(CCREG,HOST_CCREG);
3441 if(copr==12||copr==13) {
3442 assert(!is_delayslot);
3443 emit_readword((int)&pending_exception,14);
3445 emit_loadreg(rs1[i],s);
3446 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3447 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3448 if(copr==12||copr==13) {
3450 emit_jne((int)&do_interrupt);
3456 assert(opcode2[i]==0x10);
3458 if((source[i]&0x3f)==0x01) // TLBR
3459 emit_call((int)TLBR);
3460 if((source[i]&0x3f)==0x02) // TLBWI
3461 emit_call((int)TLBWI_new);
3462 if((source[i]&0x3f)==0x06) { // TLBWR
3463 // The TLB entry written by TLBWR is dependent on the count,
3464 // so update the cycle count
3465 emit_readword((int)&last_count,ECX);
3466 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3467 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3468 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3469 emit_writeword(HOST_CCREG,(int)&Count);
3470 emit_call((int)TLBWR_new);
3472 if((source[i]&0x3f)==0x08) // TLBP
3473 emit_call((int)TLBP);
3476 if((source[i]&0x3f)==0x10) // RFE
3478 emit_readword((int)&Status,0);
3479 emit_andimm(0,0x3c,1);
3480 emit_andimm(0,~0xf,0);
3481 emit_orrshr_imm(1,2,0);
3482 emit_writeword(0,(int)&Status);
3485 if((source[i]&0x3f)==0x18) // ERET
3488 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3489 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*count,HOST_CCREG); // TODO: Should there be an extra cycle here?
3490 emit_jmp((int)jump_eret);
3496 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3506 emit_readword((int)®_cop2d[copr],tl);
3507 emit_signextend16(tl,tl);
3508 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3515 emit_readword((int)®_cop2d[copr],tl);
3516 emit_andimm(tl,0xffff,tl);
3517 emit_writeword(tl,(int)®_cop2d[copr]);
3520 emit_readword((int)®_cop2d[14],tl); // SXY2
3521 emit_writeword(tl,(int)®_cop2d[copr]);
3528 emit_readword((int)®_cop2d[9],temp);
3529 emit_testimm(temp,0x8000); // do we need this?
3530 emit_andimm(temp,0xf80,temp);
3531 emit_andne_imm(temp,0,temp);
3532 emit_shr(temp,7,tl);
3533 emit_readword((int)®_cop2d[10],temp);
3534 emit_testimm(temp,0x8000);
3535 emit_andimm(temp,0xf80,temp);
3536 emit_andne_imm(temp,0,temp);
3537 emit_orrshr(temp,2,tl);
3538 emit_readword((int)®_cop2d[11],temp);
3539 emit_testimm(temp,0x8000);
3540 emit_andimm(temp,0xf80,temp);
3541 emit_andne_imm(temp,0,temp);
3542 emit_orrshl(temp,3,tl);
3543 emit_writeword(tl,(int)®_cop2d[copr]);
3546 emit_readword((int)®_cop2d[copr],tl);
3551 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3555 emit_readword((int)®_cop2d[13],temp); // SXY1
3556 emit_writeword(sl,(int)®_cop2d[copr]);
3557 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3558 emit_readword((int)®_cop2d[14],temp); // SXY2
3559 emit_writeword(sl,(int)®_cop2d[14]);
3560 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3563 emit_andimm(sl,0x001f,temp);
3564 emit_shl(temp,7,temp);
3565 emit_writeword(temp,(int)®_cop2d[9]);
3566 emit_andimm(sl,0x03e0,temp);
3567 emit_shl(temp,2,temp);
3568 emit_writeword(temp,(int)®_cop2d[10]);
3569 emit_andimm(sl,0x7c00,temp);
3570 emit_shr(temp,3,temp);
3571 emit_writeword(temp,(int)®_cop2d[11]);
3572 emit_writeword(sl,(int)®_cop2d[28]);
3576 emit_mvnmi(temp,temp);
3577 emit_clz(temp,temp);
3578 emit_writeword(sl,(int)®_cop2d[30]);
3579 emit_writeword(temp,(int)®_cop2d[31]);
3586 emit_writeword(sl,(int)®_cop2d[copr]);
3591 void cop2_assemble(int i,struct regstat *i_regs)
3593 u_int copr=(source[i]>>11)&0x1f;
3594 signed char temp=get_reg(i_regs->regmap,-1);
3595 if (opcode2[i]==0) { // MFC2
3596 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3598 cop2_get_dreg(copr,tl,temp);
3600 else if (opcode2[i]==4) { // MTC2
3601 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3602 cop2_put_dreg(copr,sl,temp);
3604 else if (opcode2[i]==2) // CFC2
3606 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3608 emit_readword((int)®_cop2c[copr],tl);
3610 else if (opcode2[i]==6) // CTC2
3612 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3621 emit_signextend16(sl,temp);
3624 //value = value & 0x7ffff000;
3625 //if (value & 0x7f87e000) value |= 0x80000000;
3626 emit_shrimm(sl,12,temp);
3627 emit_shlimm(temp,12,temp);
3628 emit_testimm(temp,0x7f000000);
3629 emit_testeqimm(temp,0x00870000);
3630 emit_testeqimm(temp,0x0000e000);
3631 emit_orrne_imm(temp,0x80000000,temp);
3637 emit_writeword(temp,(int)®_cop2c[copr]);
3642 void c2op_assemble(int i,struct regstat *i_regs)
3644 signed char temp=get_reg(i_regs->regmap,-1);
3645 u_int c2op=source[i]&0x3f;
3647 for(hr=0;hr<HOST_REGS;hr++) {
3648 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3650 if(i==0||itype[i-1]!=C2OP)
3653 if (gte_handlers[c2op]!=NULL) {
3654 int cc=get_reg(i_regs->regmap,CCREG);
3655 emit_movimm(source[i],temp); // opcode
3656 if (cc>=0&>e_cycletab[c2op])
3657 emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: cound just adjust ccadj?
3658 emit_writeword(temp,(int)&psxRegs.code);
3659 emit_call((int)gte_handlers[c2op]);
3662 if(i>=slen-1||itype[i+1]!=C2OP)
3663 restore_regs(reglist);
3666 void cop1_unusable(int i,struct regstat *i_regs)
3668 // XXX: should just just do the exception instead
3672 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3677 void cop1_assemble(int i,struct regstat *i_regs)
3679 #ifndef DISABLE_COP1
3680 // Check cop1 unusable
3682 signed char rs=get_reg(i_regs->regmap,CSREG);
3684 emit_testimm(rs,0x20000000);
3687 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3690 if (opcode2[i]==0) { // MFC1
3691 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3693 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],tl);
3694 emit_readword_indexed(0,tl,tl);
3697 else if (opcode2[i]==1) { // DMFC1
3698 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3699 signed char th=get_reg(i_regs->regmap,rt1[i]|64);
3701 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],tl);
3702 if(th>=0) emit_readword_indexed(4,tl,th);
3703 emit_readword_indexed(0,tl,tl);
3706 else if (opcode2[i]==4) { // MTC1
3707 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3708 signed char temp=get_reg(i_regs->regmap,-1);
3709 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3710 emit_writeword_indexed(sl,0,temp);
3712 else if (opcode2[i]==5) { // DMTC1
3713 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3714 signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
3715 signed char temp=get_reg(i_regs->regmap,-1);
3716 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3717 emit_writeword_indexed(sh,4,temp);
3718 emit_writeword_indexed(sl,0,temp);
3720 else if (opcode2[i]==2) // CFC1
3722 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3724 u_int copr=(source[i]>>11)&0x1f;
3725 if(copr==0) emit_readword((int)&FCR0,tl);
3726 if(copr==31) emit_readword((int)&FCR31,tl);
3729 else if (opcode2[i]==6) // CTC1
3731 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3732 u_int copr=(source[i]>>11)&0x1f;
3736 emit_writeword(sl,(int)&FCR31);
3737 // Set the rounding mode
3739 //char temp=get_reg(i_regs->regmap,-1);
3740 //emit_andimm(sl,3,temp);
3741 //emit_fldcw_indexed((int)&rounding_modes,temp);
3745 cop1_unusable(i, i_regs);
3749 void fconv_assemble_arm(int i,struct regstat *i_regs)
3751 #ifndef DISABLE_COP1
3752 signed char temp=get_reg(i_regs->regmap,-1);
3754 // Check cop1 unusable
3756 signed char rs=get_reg(i_regs->regmap,CSREG);
3758 emit_testimm(rs,0x20000000);
3761 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3765 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
3766 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
3767 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3769 emit_ftosizs(15,15); // float->int, truncate
3770 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3771 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3775 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
3776 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3778 emit_ftosizd(7,13); // double->int, truncate
3779 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3784 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
3785 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3787 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3788 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3793 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
3794 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3796 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3802 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
3803 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3805 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3810 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
3811 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3813 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3823 for(hr=0;hr<HOST_REGS;hr++) {
3824 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3828 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
3829 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3830 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3831 emit_call((int)cvt_s_w);
3833 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
3834 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3835 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3836 emit_call((int)cvt_d_w);
3838 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
3839 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3840 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3841 emit_call((int)cvt_s_l);
3843 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
3844 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3845 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3846 emit_call((int)cvt_d_l);
3849 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
3850 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3851 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3852 emit_call((int)cvt_d_s);
3854 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x24) {
3855 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3856 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3857 emit_call((int)cvt_w_s);
3859 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x25) {
3860 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3861 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3862 emit_call((int)cvt_l_s);
3865 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) {
3866 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3867 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3868 emit_call((int)cvt_s_d);
3870 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x24) {
3871 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3872 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3873 emit_call((int)cvt_w_d);
3875 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x25) {
3876 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3877 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3878 emit_call((int)cvt_l_d);
3881 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x08) {
3882 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3883 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3884 emit_call((int)round_l_s);
3886 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x09) {
3887 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3888 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3889 emit_call((int)trunc_l_s);
3891 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0a) {
3892 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3893 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3894 emit_call((int)ceil_l_s);
3896 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0b) {
3897 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3898 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3899 emit_call((int)floor_l_s);
3901 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0c) {
3902 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3903 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3904 emit_call((int)round_w_s);
3906 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) {
3907 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3908 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3909 emit_call((int)trunc_w_s);
3911 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0e) {
3912 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3913 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3914 emit_call((int)ceil_w_s);
3916 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0f) {
3917 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3918 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3919 emit_call((int)floor_w_s);
3922 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x08) {
3923 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3924 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3925 emit_call((int)round_l_d);
3927 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x09) {
3928 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3929 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3930 emit_call((int)trunc_l_d);
3932 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0a) {
3933 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3934 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3935 emit_call((int)ceil_l_d);
3937 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0b) {
3938 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3939 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3940 emit_call((int)floor_l_d);
3942 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0c) {
3943 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3944 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3945 emit_call((int)round_w_d);
3947 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) {
3948 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3949 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3950 emit_call((int)trunc_w_d);
3952 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0e) {
3953 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3954 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3955 emit_call((int)ceil_w_d);
3957 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0f) {
3958 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3959 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3960 emit_call((int)floor_w_d);
3963 restore_regs(reglist);
3965 cop1_unusable(i, i_regs);
3968 #define fconv_assemble fconv_assemble_arm
3970 void fcomp_assemble(int i,struct regstat *i_regs)
3972 #ifndef DISABLE_COP1
3973 signed char fs=get_reg(i_regs->regmap,FSREG);
3974 signed char temp=get_reg(i_regs->regmap,-1);
3976 // Check cop1 unusable
3978 signed char cs=get_reg(i_regs->regmap,CSREG);
3980 emit_testimm(cs,0x20000000);
3983 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
3987 if((source[i]&0x3f)==0x30) {
3988 emit_andimm(fs,~0x800000,fs);
3992 if((source[i]&0x3e)==0x38) {
3993 // sf/ngle - these should throw exceptions for NaNs
3994 emit_andimm(fs,~0x800000,fs);
3998 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
3999 if(opcode2[i]==0x10) {
4000 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4001 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4002 emit_orimm(fs,0x800000,fs);
4004 emit_flds(HOST_TEMPREG,15);
4007 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_s
4008 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_s
4009 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_s
4010 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_s
4011 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_s
4012 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_s
4013 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_s
4014 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_s
4015 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_s
4016 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_s
4017 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_s
4018 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_s
4019 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_s
4022 if(opcode2[i]==0x11) {
4023 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4024 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4025 emit_orimm(fs,0x800000,fs);
4027 emit_vldr(HOST_TEMPREG,7);
4030 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_d
4031 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_d
4032 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_d
4033 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_d
4034 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_d
4035 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_d
4036 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_d
4037 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_d
4038 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_d
4039 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_d
4040 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_d
4041 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_d
4042 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_d
4050 for(hr=0;hr<HOST_REGS;hr++) {
4051 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4055 if(opcode2[i]==0x10) {
4056 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4057 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4058 if((source[i]&0x3f)==0x30) emit_call((int)c_f_s);
4059 if((source[i]&0x3f)==0x31) emit_call((int)c_un_s);
4060 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_s);
4061 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_s);
4062 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_s);
4063 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_s);
4064 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_s);
4065 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_s);
4066 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_s);
4067 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_s);
4068 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_s);
4069 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_s);
4070 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_s);
4071 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_s);
4072 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_s);
4073 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_s);
4075 if(opcode2[i]==0x11) {
4076 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4077 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4078 if((source[i]&0x3f)==0x30) emit_call((int)c_f_d);
4079 if((source[i]&0x3f)==0x31) emit_call((int)c_un_d);
4080 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_d);
4081 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_d);
4082 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_d);
4083 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_d);
4084 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_d);
4085 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_d);
4086 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_d);
4087 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_d);
4088 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_d);
4089 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_d);
4090 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_d);
4091 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_d);
4092 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_d);
4093 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_d);
4095 restore_regs(reglist);
4096 emit_loadreg(FSREG,fs);
4098 cop1_unusable(i, i_regs);
4102 void float_assemble(int i,struct regstat *i_regs)
4104 #ifndef DISABLE_COP1
4105 signed char temp=get_reg(i_regs->regmap,-1);
4107 // Check cop1 unusable
4109 signed char cs=get_reg(i_regs->regmap,CSREG);
4111 emit_testimm(cs,0x20000000);
4114 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4118 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4119 if((source[i]&0x3f)==6) // mov
4121 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4122 if(opcode2[i]==0x10) {
4123 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4124 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],HOST_TEMPREG);
4125 emit_readword_indexed(0,temp,temp);
4126 emit_writeword_indexed(temp,0,HOST_TEMPREG);
4128 if(opcode2[i]==0x11) {
4129 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4130 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],HOST_TEMPREG);
4132 emit_vstr(7,HOST_TEMPREG);
4138 if((source[i]&0x3f)>3)
4140 if(opcode2[i]==0x10) {
4141 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4143 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4144 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4146 if((source[i]&0x3f)==4) // sqrt
4148 if((source[i]&0x3f)==5) // abs
4150 if((source[i]&0x3f)==7) // neg
4154 if(opcode2[i]==0x11) {
4155 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4157 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4158 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4160 if((source[i]&0x3f)==4) // sqrt
4162 if((source[i]&0x3f)==5) // abs
4164 if((source[i]&0x3f)==7) // neg
4170 if((source[i]&0x3f)<4)
4172 if(opcode2[i]==0x10) {
4173 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4175 if(opcode2[i]==0x11) {
4176 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4178 if(((source[i]>>11)&0x1f)!=((source[i]>>16)&0x1f)) {
4179 if(opcode2[i]==0x10) {
4180 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4182 emit_flds(HOST_TEMPREG,13);
4183 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4184 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4185 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4188 if((source[i]&0x3f)==0) emit_fadds(15,13,15);
4189 if((source[i]&0x3f)==1) emit_fsubs(15,13,15);
4190 if((source[i]&0x3f)==2) emit_fmuls(15,13,15);
4191 if((source[i]&0x3f)==3) emit_fdivs(15,13,15);
4192 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4193 emit_fsts(15,HOST_TEMPREG);
4198 else if(opcode2[i]==0x11) {
4199 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4201 emit_vldr(HOST_TEMPREG,6);
4202 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4203 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4204 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4207 if((source[i]&0x3f)==0) emit_faddd(7,6,7);
4208 if((source[i]&0x3f)==1) emit_fsubd(7,6,7);
4209 if((source[i]&0x3f)==2) emit_fmuld(7,6,7);
4210 if((source[i]&0x3f)==3) emit_fdivd(7,6,7);
4211 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4212 emit_vstr(7,HOST_TEMPREG);
4219 if(opcode2[i]==0x10) {
4221 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4222 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4224 if((source[i]&0x3f)==0) emit_fadds(15,15,15);
4225 if((source[i]&0x3f)==1) emit_fsubs(15,15,15);
4226 if((source[i]&0x3f)==2) emit_fmuls(15,15,15);
4227 if((source[i]&0x3f)==3) emit_fdivs(15,15,15);
4230 else if(opcode2[i]==0x11) {
4232 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4233 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4235 if((source[i]&0x3f)==0) emit_faddd(7,7,7);
4236 if((source[i]&0x3f)==1) emit_fsubd(7,7,7);
4237 if((source[i]&0x3f)==2) emit_fmuld(7,7,7);
4238 if((source[i]&0x3f)==3) emit_fdivd(7,7,7);
4247 for(hr=0;hr<HOST_REGS;hr++) {
4248 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4250 if(opcode2[i]==0x10) { // Single precision
4252 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4253 if((source[i]&0x3f)<4) {
4254 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4255 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG3_REG);
4257 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4259 switch(source[i]&0x3f)
4261 case 0x00: emit_call((int)add_s);break;
4262 case 0x01: emit_call((int)sub_s);break;
4263 case 0x02: emit_call((int)mul_s);break;
4264 case 0x03: emit_call((int)div_s);break;
4265 case 0x04: emit_call((int)sqrt_s);break;
4266 case 0x05: emit_call((int)abs_s);break;
4267 case 0x06: emit_call((int)mov_s);break;
4268 case 0x07: emit_call((int)neg_s);break;
4270 restore_regs(reglist);
4272 if(opcode2[i]==0x11) { // Double precision
4274 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4275 if((source[i]&0x3f)<4) {
4276 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4277 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG3_REG);
4279 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4281 switch(source[i]&0x3f)
4283 case 0x00: emit_call((int)add_d);break;
4284 case 0x01: emit_call((int)sub_d);break;
4285 case 0x02: emit_call((int)mul_d);break;
4286 case 0x03: emit_call((int)div_d);break;
4287 case 0x04: emit_call((int)sqrt_d);break;
4288 case 0x05: emit_call((int)abs_d);break;
4289 case 0x06: emit_call((int)mov_d);break;
4290 case 0x07: emit_call((int)neg_d);break;
4292 restore_regs(reglist);
4295 cop1_unusable(i, i_regs);
4299 void multdiv_assemble_arm(int i,struct regstat *i_regs)
4306 // case 0x1D: DMULTU
4311 if((opcode2[i]&4)==0) // 32-bit
4313 if(opcode2[i]==0x18) // MULT
4315 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4316 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4317 signed char hi=get_reg(i_regs->regmap,HIREG);
4318 signed char lo=get_reg(i_regs->regmap,LOREG);
4323 emit_smull(m1,m2,hi,lo);
4325 if(opcode2[i]==0x19) // MULTU
4327 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4328 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4329 signed char hi=get_reg(i_regs->regmap,HIREG);
4330 signed char lo=get_reg(i_regs->regmap,LOREG);
4335 emit_umull(m1,m2,hi,lo);
4337 if(opcode2[i]==0x1A) // DIV
4339 signed char d1=get_reg(i_regs->regmap,rs1[i]);
4340 signed char d2=get_reg(i_regs->regmap,rs2[i]);
4343 signed char quotient=get_reg(i_regs->regmap,LOREG);
4344 signed char remainder=get_reg(i_regs->regmap,HIREG);
4345 assert(quotient>=0);
4346 assert(remainder>=0);
4347 emit_movs(d1,remainder);
4348 emit_negmi(remainder,remainder);
4349 emit_movs(d2,HOST_TEMPREG);
4350 emit_jeq((int)out+52); // Division by zero
4351 emit_negmi(HOST_TEMPREG,HOST_TEMPREG);
4352 emit_clz(HOST_TEMPREG,quotient);
4353 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
4354 emit_orimm(quotient,1<<31,quotient);
4355 emit_shr(quotient,quotient,quotient);
4356 emit_cmp(remainder,HOST_TEMPREG);
4357 emit_subcs(remainder,HOST_TEMPREG,remainder);
4358 emit_adcs(quotient,quotient,quotient);
4359 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
4360 emit_jcc((int)out-16); // -4
4362 emit_negmi(quotient,quotient);
4364 emit_negmi(remainder,remainder);
4366 if(opcode2[i]==0x1B) // DIVU
4368 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
4369 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
4372 signed char quotient=get_reg(i_regs->regmap,LOREG);
4373 signed char remainder=get_reg(i_regs->regmap,HIREG);
4374 assert(quotient>=0);
4375 assert(remainder>=0);
4377 emit_jeq((int)out+44); // Division by zero
4378 emit_clz(d2,HOST_TEMPREG);
4379 emit_movimm(1<<31,quotient);
4380 emit_shl(d2,HOST_TEMPREG,d2);
4381 emit_mov(d1,remainder);
4382 emit_shr(quotient,HOST_TEMPREG,quotient);
4383 emit_cmp(remainder,d2);
4384 emit_subcs(remainder,d2,remainder);
4385 emit_adcs(quotient,quotient,quotient);
4386 emit_shrcc_imm(d2,1,d2);
4387 emit_jcc((int)out-16); // -4
4392 if(opcode2[i]==0x1C) // DMULT
4394 assert(opcode2[i]!=0x1C);
4395 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4396 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4397 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4398 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4407 emit_call((int)&mult64);
4412 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4413 signed char hil=get_reg(i_regs->regmap,HIREG);
4414 if(hih>=0) emit_loadreg(HIREG|64,hih);
4415 if(hil>=0) emit_loadreg(HIREG,hil);
4416 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4417 signed char lol=get_reg(i_regs->regmap,LOREG);
4418 if(loh>=0) emit_loadreg(LOREG|64,loh);
4419 if(lol>=0) emit_loadreg(LOREG,lol);
4421 if(opcode2[i]==0x1D) // DMULTU
4423 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4424 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4425 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4426 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4432 if(m1l!=0) emit_mov(m1l,0);
4433 if(m1h==0) emit_readword((int)&dynarec_local,1);
4434 else if(m1h>1) emit_mov(m1h,1);
4435 if(m2l<2) emit_readword((int)&dynarec_local+m2l*4,2);
4436 else if(m2l>2) emit_mov(m2l,2);
4437 if(m2h<3) emit_readword((int)&dynarec_local+m2h*4,3);
4438 else if(m2h>3) emit_mov(m2h,3);
4439 emit_call((int)&multu64);
4440 restore_regs(0x100f);
4441 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4442 signed char hil=get_reg(i_regs->regmap,HIREG);
4443 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4444 signed char lol=get_reg(i_regs->regmap,LOREG);
4445 /*signed char temp=get_reg(i_regs->regmap,-1);
4446 signed char rh=get_reg(i_regs->regmap,HIREG|64);
4447 signed char rl=get_reg(i_regs->regmap,HIREG);
4453 //emit_mov(m1l,EAX);
4455 emit_umull(rl,rh,m1l,m2l);
4456 emit_storereg(LOREG,rl);
4458 //emit_mov(m1h,EAX);
4460 emit_umull(rl,rh,m1h,m2l);
4461 emit_adds(rl,temp,temp);
4462 emit_adcimm(rh,0,rh);
4463 emit_storereg(HIREG,rh);
4464 //emit_mov(m2h,EAX);
4466 emit_umull(rl,rh,m1l,m2h);
4467 emit_adds(rl,temp,temp);
4468 emit_adcimm(rh,0,rh);
4469 emit_storereg(LOREG|64,temp);
4471 //emit_mov(m2h,EAX);
4473 emit_umull(rl,rh,m1h,m2h);
4474 emit_adds(rl,temp,rl);
4475 emit_loadreg(HIREG,temp);
4476 emit_adcimm(rh,0,rh);
4477 emit_adds(rl,temp,rl);
4478 emit_adcimm(rh,0,rh);
4485 emit_call((int)&multu64);
4490 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4491 signed char hil=get_reg(i_regs->regmap,HIREG);
4492 if(hih>=0) emit_loadreg(HIREG|64,hih); // DEBUG
4493 if(hil>=0) emit_loadreg(HIREG,hil); // DEBUG
4495 // Shouldn't be necessary
4496 //char loh=get_reg(i_regs->regmap,LOREG|64);
4497 //char lol=get_reg(i_regs->regmap,LOREG);
4498 //if(loh>=0) emit_loadreg(LOREG|64,loh);
4499 //if(lol>=0) emit_loadreg(LOREG,lol);
4501 if(opcode2[i]==0x1E) // DDIV
4503 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4504 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4505 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4506 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4512 if(d1l!=0) emit_mov(d1l,0);
4513 if(d1h==0) emit_readword((int)&dynarec_local,1);
4514 else if(d1h>1) emit_mov(d1h,1);
4515 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4516 else if(d2l>2) emit_mov(d2l,2);
4517 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4518 else if(d2h>3) emit_mov(d2h,3);
4519 emit_call((int)&div64);
4520 restore_regs(0x100f);
4521 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4522 signed char hil=get_reg(i_regs->regmap,HIREG);
4523 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4524 signed char lol=get_reg(i_regs->regmap,LOREG);
4525 if(hih>=0) emit_loadreg(HIREG|64,hih);
4526 if(hil>=0) emit_loadreg(HIREG,hil);
4527 if(loh>=0) emit_loadreg(LOREG|64,loh);
4528 if(lol>=0) emit_loadreg(LOREG,lol);
4530 if(opcode2[i]==0x1F) // DDIVU
4532 //u_int hr,reglist=0;
4533 //for(hr=0;hr<HOST_REGS;hr++) {
4534 // if(i_regs->regmap[hr]>=0 && (i_regs->regmap[hr]&62)!=HIREG) reglist|=1<<hr;
4536 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4537 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4538 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4539 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4545 if(d1l!=0) emit_mov(d1l,0);
4546 if(d1h==0) emit_readword((int)&dynarec_local,1);
4547 else if(d1h>1) emit_mov(d1h,1);
4548 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4549 else if(d2l>2) emit_mov(d2l,2);
4550 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4551 else if(d2h>3) emit_mov(d2h,3);
4552 emit_call((int)&divu64);
4553 restore_regs(0x100f);
4554 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4555 signed char hil=get_reg(i_regs->regmap,HIREG);
4556 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4557 signed char lol=get_reg(i_regs->regmap,LOREG);
4558 if(hih>=0) emit_loadreg(HIREG|64,hih);
4559 if(hil>=0) emit_loadreg(HIREG,hil);
4560 if(loh>=0) emit_loadreg(LOREG|64,loh);
4561 if(lol>=0) emit_loadreg(LOREG,lol);
4567 // Multiply by zero is zero.
4568 // MIPS does not have a divide by zero exception.
4569 // The result is undefined, we return zero.
4570 signed char hr=get_reg(i_regs->regmap,HIREG);
4571 signed char lr=get_reg(i_regs->regmap,LOREG);
4572 if(hr>=0) emit_zeroreg(hr);
4573 if(lr>=0) emit_zeroreg(lr);
4576 #define multdiv_assemble multdiv_assemble_arm
4578 void do_preload_rhash(int r) {
4579 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
4580 // register. On ARM the hash can be done with a single instruction (below)
4583 void do_preload_rhtbl(int ht) {
4584 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
4587 void do_rhash(int rs,int rh) {
4588 emit_andimm(rs,0xf8,rh);
4591 void do_miniht_load(int ht,int rh) {
4592 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
4593 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
4596 void do_miniht_jump(int rs,int rh,int ht) {
4598 emit_ldreq_indexed(ht,4,15);
4599 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4601 emit_jmp(jump_vaddr_reg[7]);
4603 emit_jmp(jump_vaddr_reg[rs]);
4607 void do_miniht_insert(u_int return_address,int rt,int temp) {
4609 emit_movimm(return_address,rt); // PC into link register
4610 add_to_linker((int)out,return_address,1);
4611 emit_pcreladdr(temp);
4612 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4613 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4615 emit_movw(return_address&0x0000FFFF,rt);
4616 add_to_linker((int)out,return_address,1);
4617 emit_pcreladdr(temp);
4618 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4619 emit_movt(return_address&0xFFFF0000,rt);
4620 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4624 // Sign-extend to 64 bits and write out upper half of a register
4625 // This is useful where we have a 32-bit value in a register, and want to
4626 // keep it in a 32-bit register, but can't guarantee that it won't be read
4627 // as a 64-bit value later.
4628 void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
4631 if(is32_pre==is32) return;
4633 for(hr=0;hr<HOST_REGS;hr++) {
4634 if(hr!=EXCLUDE_REG) {
4635 //if(pre[hr]==entry[hr]) {
4636 if((reg=pre[hr])>=0) {
4638 if( ((is32_pre&~is32&~uu)>>reg)&1 ) {
4639 emit_sarimm(hr,31,HOST_TEMPREG);
4640 emit_storereg(reg|64,HOST_TEMPREG);
4650 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4652 //if(dirty_pre==dirty) return;
4654 for(hr=0;hr<HOST_REGS;hr++) {
4655 if(hr!=EXCLUDE_REG) {
4657 if(((~u)>>(reg&63))&1) {
4658 if(reg==entry[hr]||(reg>0&&entry[hr]<0)) {
4659 if(((dirty_pre&~dirty)>>hr)&1) {
4661 emit_storereg(reg,hr);
4662 if( ((is32_pre&~uu)>>reg)&1 ) {
4663 emit_sarimm(hr,31,HOST_TEMPREG);
4664 emit_storereg(reg|64,HOST_TEMPREG);
4668 emit_storereg(reg,hr);
4672 else // Check if register moved to a different register
4673 if((new_hr=get_reg(entry,reg))>=0) {
4674 if((dirty_pre>>hr)&(~dirty>>new_hr)&1) {
4676 emit_storereg(reg,hr);
4677 if( ((is32_pre&~uu)>>reg)&1 ) {
4678 emit_sarimm(hr,31,HOST_TEMPREG);
4679 emit_storereg(reg|64,HOST_TEMPREG);
4683 emit_storereg(reg,hr);
4693 /* using strd could possibly help but you'd have to allocate registers in pairs
4694 void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4698 for(hr=HOST_REGS-1;hr>=0;hr--) {
4699 if(hr!=EXCLUDE_REG) {
4700 if(pre[hr]!=entry[hr]) {
4703 if(get_reg(entry,pre[hr])<0) {
4705 if(!((u>>pre[hr])&1)) {
4706 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4707 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4708 emit_sarimm(hr,31,hr+1);
4709 emit_strdreg(pre[hr],hr);
4712 emit_storereg(pre[hr],hr);
4714 emit_storereg(pre[hr],hr);
4715 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4716 emit_sarimm(hr,31,hr);
4717 emit_storereg(pre[hr]|64,hr);
4722 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4723 emit_storereg(pre[hr],hr);
4733 for(hr=0;hr<HOST_REGS;hr++) {
4734 if(hr!=EXCLUDE_REG) {
4735 if(pre[hr]!=entry[hr]) {
4738 if((nr=get_reg(entry,pre[hr]))>=0) {
4746 #define wb_invalidate wb_invalidate_arm
4749 // CPU-architecture-specific initialization
4751 #ifndef DISABLE_COP1
4752 rounding_modes[0]=0x0<<22; // round
4753 rounding_modes[1]=0x3<<22; // trunc
4754 rounding_modes[2]=0x1<<22; // ceil
4755 rounding_modes[3]=0x2<<22; // floor
4759 // vim:shiftwidth=2:expandtab