3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
8 #include "../pico_int.h"
9 #include "../sound/ym2612.h"
10 #include "../../cpu/sh2/compiler.h"
12 struct Pico32x Pico32x;
15 #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
17 static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
19 if (sh2->pending_irl > sh2->pending_int_irq) {
20 elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
22 return 64 + sh2->pending_irl / 2;
24 elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
25 level, sh2->pending_int_vector, sh2_pc(sh2));
26 sh2->pending_int_irq = 0; // auto-clear
27 sh2->pending_level = sh2->pending_irl;
28 return sh2->pending_int_vector;
32 // MUST specify active_sh2 when called from sh2 memhandlers
33 void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
35 int irqs, mlvl = 0, slvl = 0;
38 if (active_sh2 != NULL)
39 m68k_cycles = sh2_cycles_done_m68k(active_sh2);
42 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
48 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
53 mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2);
55 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
56 if (active_sh2 == &msh2)
57 sh2_end_run(active_sh2, 1);
60 srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2);
62 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
63 if (active_sh2 == &ssh2)
64 sh2_end_run(active_sh2, 1);
67 elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
70 void Pico32xStartup(void)
72 elprintf(EL_STATUS|EL_32X, "32X startup");
76 sh2_init(&msh2, 0, &ssh2);
77 msh2.irq_callback = sh2_irq_cb;
78 sh2_init(&ssh2, 1, &msh2);
79 ssh2.irq_callback = sh2_irq_cb;
82 p32x_pwm_ctl_changed();
86 Pico32x.vdp_regs[0] |= P32XV_nPAL;
93 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
94 void p32x_reset_sh2s(void)
96 elprintf(EL_32X, "sh2 reset");
100 sh2_peripheral_reset(&msh2);
101 sh2_peripheral_reset(&ssh2);
103 // if we don't have BIOS set, perform it's work here.
105 if (p32x_bios_m == NULL) {
106 unsigned int idl_src, idl_dst, idl_size; // initial data load
110 idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
111 idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
112 idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
113 if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
114 idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
115 elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
116 idl_src, idl_dst, idl_size);
119 memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
122 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
123 sh2_set_gbr(0, 0x20004000);
127 Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
128 // program will set M_OK
132 if (p32x_bios_s == NULL) {
136 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
137 sh2_set_gbr(1, 0x20004000);
139 // program will set S_OK
142 msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
145 void Pico32xInit(void)
147 if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
148 Pico32xSetClocks(PICO_MSH2_HZ, 0);
149 if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
150 Pico32xSetClocks(0, PICO_MSH2_HZ);
153 void PicoPower32x(void)
155 memset(&Pico32x, 0, sizeof(Pico32x));
157 Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
158 Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
159 Pico32x.sh2_regs[0] = P32XS2_ADEN;
162 void PicoUnload32x(void)
164 if (Pico32xMem != NULL)
165 plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
170 PicoAHW &= ~PAHW_32X;
173 void PicoReset32x(void)
175 if (PicoAHW & PAHW_32X) {
176 msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
177 Pico32x.sh2irqs |= P32XI_VRES;
178 p32x_update_irls(NULL, SekCyclesDoneT2());
179 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
180 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
181 p32x_pwm_ctl_changed();
182 p32x_timers_recalc();
186 static void p32x_start_blank(void)
188 if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) {
193 offs = 8; lines = 224;
194 if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) {
199 // XXX: no proper handling of 32col mode..
200 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
201 (Pico.video.reg[12] & 1) && // 40col mode
202 (PicoDrawMask & PDRAW_32X_ON))
204 int md_bg = Pico.video.reg[7] & 0x3f;
206 // we draw full layer (not line-by-line)
207 PicoDraw32xLayer(offs, lines, md_bg);
209 else if (Pico32xDrawMode != PDM32X_32X_ONLY)
210 PicoDraw32xLayerMdOnly(offs, lines);
216 Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
218 // FB swap waits until vblank
219 if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
220 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
221 Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
222 Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
225 Pico32x.sh2irqs |= P32XI_VINT;
226 p32x_update_irls(NULL, SekCyclesDoneT2());
227 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
228 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
231 void p32x_schedule_hint(SH2 *sh2, int m68k_cycles)
233 // rather rough, 32x hint is useless in practice
236 if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
237 return; // nobody cares
238 // note: when Pico.m.scanline is 224, SH2s might
239 // still be at scanline 93 (or so)
240 if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224)
243 after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
245 p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
247 p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
250 // compare cycles, handling overflows
252 #define CYCLES_GT(a, b) \
253 ((int)((a) - (b)) > 0)
255 #define CYCLES_GE(a, b) \
256 ((int)((a) - (b)) >= 0)
259 static void fillend_event(unsigned int now)
261 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
262 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
263 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
266 static void hint_event(unsigned int now)
268 Pico32x.sh2irqs |= P32XI_HINT;
269 p32x_update_irls(NULL, now);
270 p32x_schedule_hint(NULL, now);
273 typedef void (event_cb)(unsigned int now);
275 unsigned int event_times[P32X_EVENT_COUNT];
276 static unsigned int event_time_next;
277 static event_cb *event_cbs[] = {
278 [P32X_EVENT_PWM] = p32x_pwm_irq_event,
279 [P32X_EVENT_FILLEND] = fillend_event,
280 [P32X_EVENT_HINT] = hint_event,
283 // schedule event at some time 'after', in m68k clocks
284 void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
288 when = (now + after) | 1;
290 elprintf(EL_32X, "new event #%u %u->%u", event, now, when);
291 event_times[event] = when;
293 if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
294 event_time_next = when;
297 void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
299 unsigned int now = sh2_cycles_done_m68k(sh2);
302 p32x_event_schedule(now, event, after);
304 left_to_next = (event_time_next - now) * 3;
305 sh2_end_run(sh2, left_to_next);
308 static void run_events(unsigned int until)
310 int oldest, oldest_diff, time;
314 oldest = -1, oldest_diff = 0x7fffffff;
316 for (i = 0; i < P32X_EVENT_COUNT; i++) {
317 if (event_times[i]) {
318 diff = event_times[i] - until;
319 if (diff < oldest_diff) {
326 if (oldest_diff <= 0) {
327 time = event_times[oldest];
328 event_times[oldest] = 0;
329 elprintf(EL_32X, "run event #%d %u", oldest, time);
330 event_cbs[oldest](time);
332 else if (oldest_diff < 0x7fffffff) {
333 event_time_next = event_times[oldest];
343 elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next);
346 static inline void run_sh2(SH2 *sh2, int m68k_cycles)
350 pevt_log_sh2_o(sh2, EVT_RUN_START);
351 sh2->state |= SH2_STATE_RUN;
352 cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
353 elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
354 sh2->m68krcycles_done, cycles, sh2->pc);
356 done = sh2_execute(sh2, cycles);
358 sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
359 sh2->state &= ~SH2_STATE_RUN;
360 pevt_log_sh2_o(sh2, EVT_RUN_END);
361 elprintf_sh2(sh2, EL_32X, "-run %u %d",
362 sh2->m68krcycles_done, done);
365 // sync other sh2 to this one
366 // note: recursive call
367 void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
369 SH2 *osh2 = sh2->other_sh2;
373 if (osh2->state & SH2_STATE_RUN)
376 m68k_cycles = m68k_target - osh2->m68krcycles_done;
377 if (m68k_cycles < 200)
380 if (osh2->state & SH2_IDLE_STATES) {
381 osh2->m68krcycles_done = m68k_target;
385 elprintf_sh2(osh2, EL_32X, "sync to %u %d",
386 m68k_target, m68k_cycles);
388 run_sh2(osh2, m68k_cycles);
390 // there might be new event to schedule current sh2 to
391 if (event_time_next) {
392 left_to_event = event_time_next - m68k_target;
394 if (sh2_cycles_left(sh2) > left_to_event) {
395 if (left_to_event < 1)
397 sh2_end_run(sh2, left_to_event);
402 #define sync_sh2s_normal p32x_sync_sh2s
403 //#define sync_sh2s_lockstep p32x_sync_sh2s
405 /* most timing is in 68k clock */
406 void sync_sh2s_normal(unsigned int m68k_target)
408 unsigned int now, target, timer_cycles;
411 elprintf(EL_32X, "sh2 sync to %u", m68k_target);
413 if (!(Pico32x.regs[0] & P32XS_nRES)) {
414 msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
418 now = msh2.m68krcycles_done;
419 if (CYCLES_GT(now, ssh2.m68krcycles_done))
420 now = ssh2.m68krcycles_done;
423 while (CYCLES_GT(m68k_target, now))
425 if (event_time_next && CYCLES_GE(now, event_time_next))
428 target = m68k_target;
429 if (event_time_next && CYCLES_GT(target, event_time_next))
430 target = event_time_next;
432 while (CYCLES_GT(target, now))
434 elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
435 target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
436 m68k_target - now, Pico32x.emu_flags);
438 if (!(ssh2.state & SH2_IDLE_STATES)) {
439 cycles = target - ssh2.m68krcycles_done;
441 run_sh2(&ssh2, cycles);
443 if (event_time_next && CYCLES_GT(target, event_time_next))
444 target = event_time_next;
448 if (!(msh2.state & SH2_IDLE_STATES)) {
449 cycles = target - msh2.m68krcycles_done;
451 run_sh2(&msh2, cycles);
453 if (event_time_next && CYCLES_GT(target, event_time_next))
454 target = event_time_next;
459 if (!(msh2.state & SH2_IDLE_STATES)) {
460 if (CYCLES_GT(now, msh2.m68krcycles_done))
461 now = msh2.m68krcycles_done;
463 if (!(ssh2.state & SH2_IDLE_STATES)) {
464 if (CYCLES_GT(now, ssh2.m68krcycles_done))
465 now = ssh2.m68krcycles_done;
469 p32x_timers_do(now - timer_cycles);
474 if (msh2.state & SH2_IDLE_STATES) {
475 if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
476 msh2.m68krcycles_done = m68k_target;
478 if (ssh2.state & SH2_IDLE_STATES) {
479 if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
480 ssh2.m68krcycles_done = m68k_target;
486 void sync_sh2s_lockstep(unsigned int m68k_target)
488 unsigned int mcycles;
490 mcycles = msh2.m68krcycles_done;
491 if (ssh2.m68krcycles_done < mcycles)
492 mcycles = ssh2.m68krcycles_done;
494 while (mcycles < m68k_target) {
496 sync_sh2s_normal(mcycles);
500 #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
501 SekRunM68k(m68k_cycles); \
502 if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
503 p32x_sync_sh2s(SekCyclesDoneT2()); \
507 #include "../pico_cmn.c"
509 void PicoFrame32x(void)
513 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
514 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
515 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
517 if (!(Pico32x.sh2_regs[0] & 0x80))
518 p32x_schedule_hint(NULL, SekCyclesDoneT2());
519 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
520 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
526 elprintf(EL_32X, "poll: %02x %02x %02x",
527 Pico32x.emu_flags & 3, msh2.state, ssh2.state);
530 // calculate multipliers against 68k clock (7670442)
531 // normally * 3, but effectively slower due to high latencies everywhere
532 // however using something lower breaks MK2 animations
533 void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
535 float m68k_clk = (float)(OSC_NTSC / 7);
537 msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
538 msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
541 ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
542 ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
546 void Pico32xStateLoaded(int is_early)
549 Pico32xMemStateLoaded();
554 sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
555 p32x_update_irls(NULL, SekCycleCntT);
556 p32x_pwm_state_loaded();
557 run_events(SekCycleCntT);
560 // vim:shiftwidth=2:ts=2:expandtab