3 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
4 * a15102 ........ ......SM ? 4002 // intS intM
5 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
6 * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
7 * a15108 (32bit DREQ src) 4008
8 * a1510c (32bit DREQ dst) 400c
9 * a15110 llllllll llllll00 4010 // DREQ Len
10 * a15112 (16bit FIFO reg) 4012
11 * a15114 ? (16bit VRES clr) 4014
12 * a15116 ? (16bit Vint clr) 4016
13 * a15118 ? (16bit Hint clr) 4018
14 * a1511a ........ .......C (16bit CMD clr) 401a // Cm
15 * a1511c ? (16bit PWM clr) 401c
17 * a15120 (16 bytes comm) 2020
20 #include "../pico_int.h"
21 #include "../memory.h"
26 #define ash2_end_run(x)
30 static const char str_mars[] = "MARS";
32 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
33 struct Pico32xMem *Pico32xMem;
35 static void bank_switch(int b);
38 #define POLL_THRESHOLD 6
41 u32 addr, cycles, cyc_max;
44 static struct poll_det m68k_poll, sh2_poll[2];
46 static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
48 int ret = 0, flag = pd->flag;
53 if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
55 if (pd->cnt > POLL_THRESHOLD) {
56 if (!(Pico32x.emu_flags & flag)) {
57 elprintf(EL_32X, "%s poll addr %08x, cyc %u",
58 flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
59 (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
62 Pico32x.emu_flags |= flag;
74 static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
76 int ret = 0, flag = pd->flag;
78 flag <<= 3; // VDP only
80 flag |= flag << 3; // both
81 if (Pico32x.emu_flags & flag) {
82 elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
85 Pico32x.emu_flags &= ~flag;
86 pd->addr = pd->cnt = 0;
90 void p32x_poll_event(int cpu_mask, int is_vdp)
93 p32x_poll_undetect(&sh2_poll[0], is_vdp);
95 p32x_poll_undetect(&sh2_poll[1], is_vdp);
102 static const u16 comm_fakevals[] = {
103 0x4d5f, 0x4f4b, // M_OK
104 0x535f, 0x4f4b, // S_OK
105 0x4D41, 0x5346, // MASF - Brutal Unleashed
106 0x5331, 0x4d31, // Darxide
109 0x0000, 0x0000, // eq for doom
110 0x0002, // Mortal Kombat
114 static u32 sh2_comm_faker(u32 a)
117 if (a == 0x28 && !p32x_csum_faked) {
119 return *(unsigned short *)(Pico.rom + 0x18e);
121 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
123 return comm_fakevals[f++];
129 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
130 unsigned int chcr0; // chan ctl
131 unsigned int sar1, dar1, tcr1; // same for chan 1
137 static void dma_68k2sh2_do(void)
139 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
142 if (dmac0->tcr0 != *dreqlen)
143 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
145 // HACK: assume bus is busy and SH2 is halted
146 // XXX: use different mechanism for this, not poll det
147 Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
149 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
150 extern void p32x_sh2_write16(u32 a, u32 d, int id);
151 elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
152 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0);
158 Pico32x.dmac_ptr = 0; // HACK
159 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
161 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
162 if (dmac0->tcr0 == 0) {
163 dmac0->chcr0 |= 2; // DMA has ended normally
164 p32x_poll_undetect(&sh2_poll[0], 0);
168 // ------------------------------------------------------------------
171 static u32 p32x_reg_read16(u32 a)
175 if (a == 2) // INTM, INTS
176 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
178 if ((a & 0x30) == 0x20)
179 return sh2_comm_faker(a);
181 if ((a & 0x30) == 0x20) {
182 // evil X-Men proto polls in a dbra loop and expects it to expire..
184 if (SekDar(2) != dr2)
188 if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
196 if ((a & 0x30) == 0x30)
197 return p32x_pwm_read16(a);
199 return Pico32x.regs[a / 2];
202 static void p32x_reg_write8(u32 a, u32 d)
204 u16 *r = Pico32x.regs;
207 // for things like bset on comm port
211 case 0: // adapter ctl
212 r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
214 case 1: // adapter ctl, RES bit writeable
215 if ((d ^ r[0]) & d & P32XS_nRES)
217 r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
220 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
221 Pico32x.sh2irqi[0] |= P32XI_CMD;
225 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
226 Pico32x.sh2irqi[1] |= P32XI_CMD;
239 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
246 if ((a & 0x30) == 0x20) {
249 p32x_poll_undetect(&sh2_poll[0], 0);
250 p32x_poll_undetect(&sh2_poll[1], 0);
251 // if some SH2 is busy waiting, it needs to see the result ASAP
252 if (SekCyclesLeftNoMCD > 32)
258 static void p32x_reg_write16(u32 a, u32 d)
260 u16 *r = Pico32x.regs;
263 // for things like bset on comm port
267 case 0x00: // adapter ctl
268 if ((d ^ r[0]) & d & P32XS_nRES)
270 r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
272 case 0x10: // DREQ len
275 case 0x12: // FIFO reg
276 if (!(r[6 / 2] & P32XS_68S)) {
277 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
280 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
281 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
282 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
284 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
285 r[6 / 2] |= P32XS_FULL;
291 if ((a & 0x38) == 0x08) {
296 else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
298 p32x_poll_undetect(&sh2_poll[0], 0);
299 p32x_poll_undetect(&sh2_poll[1], 0);
301 if (SekCyclesLeftNoMCD > 32)
306 else if ((a & 0x30) == 0x30) {
307 p32x_pwm_write16(a, d);
311 p32x_reg_write8(a + 1, d);
314 // ------------------------------------------------------------------
316 static u32 p32x_vdp_read16(u32 a)
320 return Pico32x.vdp_regs[a / 2];
323 static void p32x_vdp_write8(u32 a, u32 d)
325 u16 *r = Pico32x.vdp_regs;
328 // for FEN checks between writes
331 // TODO: verify what's writeable
334 // priority inversion is handled in palette
335 if ((r[0] ^ d) & P32XV_PRI)
336 Pico32x.dirty_pal = 1;
337 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
339 case 0x05: // fill len
344 Pico32x.pending_fb = d;
345 // if we are blanking and FS bit is changing
346 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
348 Pico32xSwapDRAM(d ^ 1);
349 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
355 static void p32x_vdp_write16(u32 a, u32 d)
358 if (a == 6) { // fill start
359 Pico32x.vdp_regs[6 / 2] = d;
362 if (a == 8) { // fill data
363 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
364 int len = Pico32x.vdp_regs[4 / 2] + 1;
365 a = Pico32x.vdp_regs[6 / 2];
368 a = (a & 0xff00) | ((a + 1) & 0xff);
370 Pico32x.vdp_regs[6 / 2] = a;
371 Pico32x.vdp_regs[8 / 2] = d;
375 p32x_vdp_write8(a | 1, d);
378 // ------------------------------------------------------------------
381 static u32 p32x_sh2reg_read16(u32 a, int cpuid)
383 u16 *r = Pico32x.regs;
387 case 0x00: // adapter/irq ctl
388 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
389 case 0x04: // H count (often as comm too)
390 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
392 return Pico32x.sh2_regs[4 / 2];
393 case 0x10: // DREQ len
398 if ((a & 0x38) == 0x08)
401 if ((a & 0x30) == 0x20) {
402 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
406 if ((a & 0x30) == 0x30) {
407 sh2_poll[cpuid].cnt = 0;
408 return p32x_pwm_read16(a);
414 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
419 Pico32x.regs[0] &= ~P32XS_FM;
420 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
423 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
424 Pico32x.sh2_regs[0] &= ~0x80;
425 Pico32x.sh2_regs[0] |= d & 0x80;
429 Pico32x.sh2_regs[4 / 2] = d & 0xff;
430 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
434 if ((a & 0x30) == 0x20) {
435 u8 *r8 = (u8 *)Pico32x.regs;
437 if (p32x_poll_undetect(&m68k_poll, 0))
439 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
444 static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
449 if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
450 Pico32x.regs[a / 2] = d;
451 if (p32x_poll_undetect(&m68k_poll, 0))
453 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
457 else if ((a & 0x30) == 0x30) {
458 p32x_pwm_write16(a, d);
464 Pico32x.regs[0] &= ~P32XS_FM;
465 Pico32x.regs[0] |= d & P32XS_FM;
467 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
468 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
469 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
470 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
472 Pico32x.sh2irqs &= ~P32XI_PWM;
477 p32x_sh2reg_write8(a | 1, d, cpuid);
484 // ------------------------------------------------------------------
485 // SH2 internal peripherals
486 // we keep them in little endian format
487 static u32 sh2_peripheral_read8(u32 a, int id)
489 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
495 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
499 static u32 sh2_peripheral_read16(u32 a, int id)
501 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
507 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
511 static u32 sh2_peripheral_read32(u32 a, int id)
515 d = Pico32xMem->sh2_peri_regs[id][a / 4];
517 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
521 static void sh2_peripheral_write8(u32 a, u32 d, int id)
523 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
524 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
530 if ((a == 2 && (d & 0x20)) || // transmiter enabled
531 (a == 4 && !(d & 0x80))) { // valid data in TDR
532 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
533 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
534 int level = PREG8(oregs, 0x60) >> 4;
535 int vector = PREG8(oregs, 0x63) & 0x7f;
536 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
537 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
542 static void sh2_peripheral_write16(u32 a, u32 d, int id)
544 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
545 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
551 if ((d & 0xff00) == 0xa500) { // WTCSR
553 p32x_timers_recalc();
555 if ((d & 0xff00) == 0x5a00) // WTCNT
563 static void sh2_peripheral_write32(u32 a, u32 d, int id)
565 u32 *r = Pico32xMem->sh2_peri_regs[id];
566 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
572 // division unit (TODO: verify):
573 case 0x104: // DVDNT: divident L, starts divide
574 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
576 signed int divisor = r[0x100 / 4];
577 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
578 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
582 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
583 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
585 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
586 signed int divisor = r[0x100 / 4];
587 // XXX: undocumented mirroring to 0x118,0x11c?
588 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
589 r[0x11c / 4] = r[0x114 / 4] = divident / divisor;
594 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
595 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
596 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
597 dmac0->tcr0 &= 0xffffff;
599 // HACK: assume 68k starts writing soon and end the timeslice
602 // DREQ is only sent after first 4 words are written.
603 // we do multiple of 4 words to avoid messing up alignment
604 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
605 elprintf(EL_32X, "68k -> sh2 DMA");
611 // ------------------------------------------------------------------
615 static u32 PicoRead8_32x_on(u32 a)
618 if ((a & 0xffc0) == 0x5100) { // a15100
619 d = p32x_reg_read16(a);
623 if ((a & 0xfc00) != 0x5000)
624 return PicoRead8_io(a);
626 if ((a & 0xfff0) == 0x5180) { // a15180
627 d = p32x_vdp_read16(a);
631 if ((a & 0xfe00) == 0x5200) { // a15200
632 d = Pico32xMem->pal[(a & 0x1ff) / 2];
636 if ((a & 0xfffc) == 0x30ec) { // a130ec
641 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
651 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
655 static u32 PicoRead16_32x_on(u32 a)
658 if ((a & 0xffc0) == 0x5100) { // a15100
659 d = p32x_reg_read16(a);
663 if ((a & 0xfc00) != 0x5000)
664 return PicoRead16_io(a);
666 if ((a & 0xfff0) == 0x5180) { // a15180
667 d = p32x_vdp_read16(a);
671 if ((a & 0xfe00) == 0x5200) { // a15200
672 d = Pico32xMem->pal[(a & 0x1ff) / 2];
676 if ((a & 0xfffc) == 0x30ec) { // a130ec
677 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
681 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
685 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
689 static void PicoWrite8_32x_on(u32 a, u32 d)
691 if ((a & 0xfc00) == 0x5000)
692 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
694 if ((a & 0xffc0) == 0x5100) { // a15100
695 p32x_reg_write8(a, d);
699 if ((a & 0xfc00) != 0x5000) {
704 if ((a & 0xfff0) == 0x5180) { // a15180
705 p32x_vdp_write8(a, d);
710 if ((a & 0xfe00) == 0x5200) { // a15200
711 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
712 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
713 Pico32x.dirty_pal = 1;
717 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
720 static void PicoWrite16_32x_on(u32 a, u32 d)
722 if ((a & 0xfc00) == 0x5000)
723 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
725 if ((a & 0xffc0) == 0x5100) { // a15100
726 p32x_reg_write16(a, d);
730 if ((a & 0xfc00) != 0x5000) {
731 PicoWrite16_io(a, d);
735 if ((a & 0xfff0) == 0x5180) { // a15180
736 p32x_vdp_write16(a, d);
740 if ((a & 0xfe00) == 0x5200) { // a15200
741 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
742 Pico32x.dirty_pal = 1;
746 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
750 u32 PicoRead8_32x(u32 a)
753 if ((a & 0xffc0) == 0x5100) { // a15100
754 // regs are always readable
755 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
759 if ((a & 0xfffc) == 0x30ec) { // a130ec
764 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
768 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
772 u32 PicoRead16_32x(u32 a)
775 if ((a & 0xffc0) == 0x5100) { // a15100
776 d = Pico32x.regs[(a & 0x3f) / 2];
780 if ((a & 0xfffc) == 0x30ec) { // a130ec
781 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
785 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
789 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
793 void PicoWrite8_32x(u32 a, u32 d)
795 if ((a & 0xffc0) == 0x5100) { // a15100
796 u16 *r = Pico32x.regs;
798 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
801 if ((d ^ r[0]) & d & P32XS_ADEN) {
803 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
805 p32x_reg_write8(a, d); // forward for reset processing
810 // allow only COMM for now
811 if ((a & 0x30) == 0x20) {
818 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
821 void PicoWrite16_32x(u32 a, u32 d)
823 if ((a & 0xffc0) == 0x5100) { // a15100
824 u16 *r = Pico32x.regs;
826 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
829 if ((d ^ r[0]) & d & P32XS_ADEN) {
831 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
833 p32x_reg_write16(a, d); // forward for reset processing
838 // allow only COMM for now
839 if ((a & 0x30) == 0x20)
844 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
847 // -----------------------------------------------------------------
849 // hint vector is writeable
850 static void PicoWrite8_hint(u32 a, u32 d)
852 if ((a & 0xfffc) == 0x0070) {
853 Pico32xMem->m68k_rom[a ^ 1] = d;
857 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
860 static void PicoWrite16_hint(u32 a, u32 d)
862 if ((a & 0xfffc) == 0x0070) {
863 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
867 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
870 void Pico32xSwapDRAM(int b)
872 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
873 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
874 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
875 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
878 static void bank_switch(int b)
880 unsigned int rs, bank;
883 if (bank >= Pico.romsize) {
884 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
888 // 32X ROM (unbanked, XXX: consider mirroring?)
889 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
893 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
894 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
896 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
899 // setup FAME fetchmap
900 for (rs = 0x90; rs < 0xa0; rs++)
901 PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom + bank - 0x900000;
905 // -----------------------------------------------------------------
907 // -----------------------------------------------------------------
909 u32 p32x_sh2_read8(u32 a, int id)
913 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
914 return Pico32xMem->sh2_rom_m[a ^ 1];
915 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
916 return Pico32xMem->sh2_rom_s[a ^ 1];
918 if ((a & 0xdffc0000) == 0x06000000)
919 return Pico32xMem->sdram[(a & 0x3ffff) ^ 1];
921 if ((a & 0xdfc00000) == 0x02000000)
922 if ((a & 0x003fffff) < Pico.romsize)
923 return Pico.rom[(a & 0x3fffff) ^ 1];
925 if ((a & ~0xfff) == 0xc0000000)
926 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
928 if ((a & 0xdffc0000) == 0x04000000) {
929 /* XXX: overwrite readable as normal? */
930 u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
931 return dram[(a & 0x1ffff) ^ 1];
934 if ((a & 0xdfffff00) == 0x4000) {
935 d = p32x_sh2reg_read16(a, id);
939 if ((a & 0xdfffff00) == 0x4100) {
940 d = p32x_vdp_read16(a);
941 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
946 if ((a & 0xdfffff00) == 0x4200) {
947 d = Pico32xMem->pal[(a & 0x1ff) / 2];
951 if ((a & 0xfffffe00) == 0xfffffe00)
952 return sh2_peripheral_read8(a, id);
954 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
955 id ? 's' : 'm', a, d, sh2_pc(id));
964 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
965 id ? 's' : 'm', a, d, sh2_pc(id));
969 u32 p32x_sh2_read16(u32 a, int id)
973 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
974 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
975 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
976 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
978 if ((a & 0xdffc0000) == 0x06000000)
979 return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2];
981 if ((a & 0xdfc00000) == 0x02000000)
982 if ((a & 0x003fffff) < Pico.romsize)
983 return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2];
985 if ((a & ~0xfff) == 0xc0000000)
986 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
988 if ((a & 0xdffe0000) == 0x04000000)
989 return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
991 if ((a & 0xdfffff00) == 0x4000) {
992 d = p32x_sh2reg_read16(a, id);
993 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
998 if ((a & 0xdfffff00) == 0x4100) {
999 d = p32x_vdp_read16(a);
1000 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
1005 if ((a & 0xdfffff00) == 0x4200) {
1006 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1010 if ((a & 0xfffffe00) == 0xfffffe00)
1011 return sh2_peripheral_read16(a, id);
1013 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
1014 id ? 's' : 'm', a, d, sh2_pc(id));
1018 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
1019 id ? 's' : 'm', a, d, sh2_pc(id));
1023 u32 p32x_sh2_read32(u32 a, int id)
1025 if ((a & 0xfffffe00) == 0xfffffe00)
1026 return sh2_peripheral_read32(a, id);
1028 // elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc());
1029 return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id);
1032 void p32x_sh2_write8(u32 a, u32 d, int id)
1034 if ((a & 0xdffffc00) == 0x4000)
1035 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
1036 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1038 if ((a & 0xdffc0000) == 0x06000000) {
1039 Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d;
1043 if ((a & 0xdffc0000) == 0x04000000) {
1045 if (!(a & 0x20000) || d) {
1046 dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
1047 dram[(a & 0x1ffff) ^ 1] = d;
1052 if ((a & ~0xfff) == 0xc0000000) {
1053 Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d;
1057 if ((a & 0xdfffff00) == 0x4100) {
1058 p32x_vdp_write8(a, d);
1062 if ((a & 0xdfffff00) == 0x4000) {
1063 p32x_sh2reg_write8(a, d, id);
1067 if ((a & 0xfffffe00) == 0xfffffe00) {
1068 sh2_peripheral_write8(a, d, id);
1072 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
1073 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1076 void p32x_sh2_write16(u32 a, u32 d, int id)
1078 if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1079 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
1080 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1082 // ignore "Associative purge space"
1083 if ((a & 0xf8000000) == 0x40000000)
1086 if ((a & 0xdffc0000) == 0x06000000) {
1087 ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d;
1091 if ((a & ~0xfff) == 0xc0000000) {
1092 ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d;
1096 if ((a & 0xdffc0000) == 0x04000000) {
1097 u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
1098 if (!(a & 0x20000)) {
1103 if (!(d & 0xff00)) d |= *pd & 0xff00;
1104 if (!(d & 0x00ff)) d |= *pd & 0x00ff;
1109 if ((a & 0xdfffff00) == 0x4100) {
1110 sh2_poll[id].cnt = 0; // for poll before VDP accesses
1111 p32x_vdp_write16(a, d);
1115 if ((a & 0xdffffe00) == 0x4200) {
1116 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1117 Pico32x.dirty_pal = 1;
1121 if ((a & 0xdfffff00) == 0x4000) {
1122 p32x_sh2reg_write16(a, d, id);
1126 if ((a & 0xfffffe00) == 0xfffffe00) {
1127 sh2_peripheral_write16(a, d, id);
1131 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1132 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1135 void p32x_sh2_write32(u32 a, u32 d, int id)
1137 if ((a & 0xfffffe00) == 0xfffffe00) {
1138 sh2_peripheral_write32(a, d, id);
1142 p32x_sh2_write16(a, d >> 16, id);
1143 p32x_sh2_write16(a + 2, d, id);
1146 static const u16 msh2_code[] = {
1147 // trap instructions
1148 0xaffe, // bra <self>
1150 // have to wait a bit until m68k initial program finishes clearing stuff
1151 // to avoid races with game SH2 code, like in Tempo
1152 0xd004, // mov.l @(_m_ok,pc), r0
1153 0xd105, // mov.l @(_cnt,pc), r1
1154 0xd205, // mov.l @(_start,pc), r2
1155 0x71ff, // add #-1, r1
1156 0x4115, // cmp/pl r1
1158 0xc208, // mov.l r0, @(h'20,gbr)
1159 0x6822, // mov.l @r2, r8
1162 ('M'<<8)|'_', ('O'<<8)|'K',
1164 0x2200, 0x03e0 // master start pointer in ROM
1167 static const u16 ssh2_code[] = {
1168 0xaffe, // bra <self>
1170 // code to wait for master, in case authentic master BIOS is used
1171 0xd104, // mov.l @(_m_ok,pc), r1
1172 0xd206, // mov.l @(_start,pc), r2
1173 0xc608, // mov.l @(h'20,gbr), r0
1174 0x3100, // cmp/eq r0, r1
1176 0xd003, // mov.l @(_s_ok,pc), r0
1177 0xc209, // mov.l r0, @(h'24,gbr)
1178 0x6822, // mov.l @r2, r8
1181 ('M'<<8)|'_', ('O'<<8)|'K',
1182 ('S'<<8)|'_', ('O'<<8)|'K',
1183 0x2200, 0x03e4 // slave start pointer in ROM
1186 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
1187 static void get_bios(void)
1194 if (p32x_bios_g != NULL) {
1195 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1196 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, 0x100);
1200 ps = (u16 *)Pico32xMem->m68k_rom;
1202 for (i = 1; i < 0xc0/4; i++)
1203 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1206 for (i = 0xc0/2; i < 0x100/2; i++)
1210 ps[0xc0/2] = 0x46fc;
1211 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1212 ps[0xfe/2] = 0x60fe; // jump to self
1214 ps[0xfe/2] = 0x4e75; // rts
1217 // fill remaining m68k_rom page with game ROM
1218 memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
1221 if (p32x_bios_m != NULL) {
1222 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1223 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1226 pl = (u32 *)Pico32xMem->sh2_rom_m;
1228 // fill exception vector table to our trap address
1229 for (i = 0; i < 128; i++)
1230 pl[i] = HWSWAP(0x200);
1233 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1236 pl[1] = pl[3] = HWSWAP(0x6040000);
1238 pl[0] = pl[2] = HWSWAP(0x204);
1242 if (p32x_bios_s != NULL) {
1243 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1244 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1247 pl = (u32 *)Pico32xMem->sh2_rom_s;
1249 // fill exception vector table to our trap address
1250 for (i = 0; i < 128; i++)
1251 pl[i] = HWSWAP(0x200);
1254 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1257 pl[1] = pl[3] = HWSWAP(0x603f800);
1259 pl[0] = pl[2] = HWSWAP(0x204);
1263 void PicoMemSetup32x(void)
1267 Pico32xMem = calloc(1, sizeof(*Pico32xMem));
1268 if (Pico32xMem == NULL) {
1269 elprintf(EL_STATUS, "OOM");
1273 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
1277 // cartridge area becomes unmapped
1278 // XXX: we take the easy way and don't unmap ROM,
1279 // so that we can avoid handling the RV bit.
1280 // m68k_map_unmap(0x000000, 0x3fffff);
1283 rs = sizeof(Pico32xMem->m68k_rom);
1284 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1285 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1286 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1287 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1292 // 32X ROM (unbanked, XXX: consider mirroring?)
1293 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1296 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1297 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1299 // setup FAME fetchmap
1300 PicoCpuFM68k.Fetch[0] = (u32)Pico32xMem->m68k_rom;
1301 for (rs = 0x88; rs < 0x90; rs++)
1302 PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom - 0x880000;
1309 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1310 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1311 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1312 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1314 // setup poll detector
1315 m68k_poll.flag = P32XF_68KPOLL;
1316 m68k_poll.cyc_max = 64;
1317 sh2_poll[0].flag = P32XF_MSH2POLL;
1318 sh2_poll[0].cyc_max = 21;
1319 sh2_poll[1].flag = P32XF_SSH2POLL;
1320 sh2_poll[1].cyc_max = 16;