5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * iii. .cc. ..xx * // Internal, Cs, x
12 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
13 * a15102 ........ ......SM ? 4002 // intS intM
14 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
15 * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
16 * a15108 (32bit DREQ src) 4008
17 * a1510c (32bit DREQ dst) 400c
18 * a15110 llllllll llllll00 4010 // DREQ Len
19 * a15112 (16bit FIFO reg) 4012
20 * a15114 ? (16bit VRES clr) 4014
21 * a15116 ? (16bit Vint clr) 4016
22 * a15118 ? (16bit Hint clr) 4018
23 * a1511a ........ .......C (16bit CMD clr) 401a // Cm
24 * a1511c ? (16bit PWM clr) 401c
26 * a15120 (16 bytes comm) 2020
29 #include "../pico_int.h"
30 #include "../memory.h"
32 #include "../../cpu/sh2/compiler.h"
38 #define ash2_end_run(x)
42 static const char str_mars[] = "MARS";
44 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
45 struct Pico32xMem *Pico32xMem;
47 static void bank_switch(int b);
50 #define POLL_THRESHOLD 6
53 u32 addr, cycles, cyc_max;
56 static struct poll_det m68k_poll, sh2_poll[2];
58 static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
60 int ret = 0, flag = pd->flag;
65 if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
67 if (pd->cnt > POLL_THRESHOLD) {
68 if (!(Pico32x.emu_flags & flag)) {
69 elprintf(EL_32X, "%s poll addr %08x, cyc %u",
70 flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
71 (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
74 Pico32x.emu_flags |= flag;
86 static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
88 int ret = 0, flag = pd->flag;
90 flag <<= 3; // VDP only
92 flag |= flag << 3; // both
93 if (Pico32x.emu_flags & flag) {
94 elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
97 Pico32x.emu_flags &= ~flag;
98 pd->addr = pd->cnt = 0;
102 void p32x_poll_event(int cpu_mask, int is_vdp)
105 p32x_poll_undetect(&sh2_poll[0], is_vdp);
107 p32x_poll_undetect(&sh2_poll[1], is_vdp);
114 static const u16 comm_fakevals[] = {
115 0x4d5f, 0x4f4b, // M_OK
116 0x535f, 0x4f4b, // S_OK
117 0x4D41, 0x5346, // MASF - Brutal Unleashed
118 0x5331, 0x4d31, // Darxide
121 0x0000, 0x0000, // eq for doom
122 0x0002, // Mortal Kombat
126 static u32 sh2_comm_faker(u32 a)
129 if (a == 0x28 && !p32x_csum_faked) {
131 return *(unsigned short *)(Pico.rom + 0x18e);
133 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
135 return comm_fakevals[f++];
141 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
142 unsigned int chcr0; // chan ctl
143 unsigned int sar1, dar1, tcr1; // same for chan 1
149 static void dma_68k2sh2_do(void)
151 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
154 if (dmac0->tcr0 != *dreqlen)
155 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
157 // HACK: assume bus is busy and SH2 is halted
158 // XXX: use different mechanism for this, not poll det
159 Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
161 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
162 elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
163 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], &msh2);
169 Pico32x.dmac_ptr = 0; // HACK
170 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
172 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
173 if (dmac0->tcr0 == 0) {
174 dmac0->chcr0 |= 2; // DMA has ended normally
175 p32x_poll_undetect(&sh2_poll[0], 0);
179 // ------------------------------------------------------------------
182 static u32 p32x_reg_read16(u32 a)
187 if ((a & 0x30) == 0x20)
188 return sh2_comm_faker(a);
190 if ((a & 0x30) == 0x20) {
192 unsigned int cycles = SekCyclesDoneT();
193 int comreg = 1 << (a & 0x0f) / 2;
195 // evil X-Men proto polls in a dbra loop and expects it to expire..
196 if (SekDar(2) != dr2)
200 if (cycles - msh2.m68krcycles_done > 500)
201 p32x_sync_sh2s(cycles);
202 if (Pico32x.comm_dirty_sh2 & comreg)
203 Pico32x.comm_dirty_sh2 &= ~comreg;
204 else if (p32x_poll_detect(&m68k_poll, a, cycles, 0)) {
213 if (a == 2) { // INTM, INTS
214 unsigned int cycles = SekCyclesDoneT();
215 if (cycles - msh2.m68krcycles_done > 64)
216 p32x_sync_sh2s(cycles);
217 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
220 if ((a & 0x30) == 0x30)
221 return p32x_pwm_read16(a);
224 return Pico32x.regs[a / 2];
227 static void p32x_reg_write8(u32 a, u32 d)
229 u16 *r = Pico32x.regs;
232 // for things like bset on comm port
236 case 0: // adapter ctl
237 r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
239 case 1: // adapter ctl, RES bit writeable
240 if ((d ^ r[0]) & d & P32XS_nRES)
242 r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
245 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
246 p32x_sync_sh2s(SekCyclesDoneT());
247 Pico32x.sh2irqi[0] |= P32XI_CMD;
250 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
251 p32x_sync_sh2s(SekCyclesDoneT());
252 Pico32x.sh2irqi[1] |= P32XI_CMD;
264 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
271 if ((a & 0x30) == 0x20) {
273 int cycles = SekCyclesDoneT();
279 comreg = 1 << (a & 0x0f) / 2;
280 if (Pico32x.comm_dirty_68k & comreg)
281 p32x_sync_sh2s(cycles);
284 p32x_poll_undetect(&sh2_poll[0], 0);
285 p32x_poll_undetect(&sh2_poll[1], 0);
286 Pico32x.comm_dirty_68k |= comreg;
288 if (cycles - (int)msh2.m68krcycles_done > 120)
289 p32x_sync_sh2s(cycles);
294 static void p32x_reg_write16(u32 a, u32 d)
296 u16 *r = Pico32x.regs;
299 // for things like bset on comm port
303 case 0x00: // adapter ctl
304 if ((d ^ r[0]) & d & P32XS_nRES)
306 r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
308 case 0x10: // DREQ len
311 case 0x12: // FIFO reg
312 if (!(r[6 / 2] & P32XS_68S)) {
313 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
316 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
317 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
318 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
320 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
321 r[6 / 2] |= P32XS_FULL;
327 if ((a & 0x38) == 0x08) {
332 else if ((a & 0x30) == 0x20) {
333 int cycles = SekCyclesDoneT();
339 comreg = 1 << (a & 0x0f) / 2;
340 if (Pico32x.comm_dirty_68k & comreg)
341 p32x_sync_sh2s(cycles);
344 p32x_poll_undetect(&sh2_poll[0], 0);
345 p32x_poll_undetect(&sh2_poll[1], 0);
346 Pico32x.comm_dirty_68k |= comreg;
348 if (cycles - (int)msh2.m68krcycles_done > 120)
349 p32x_sync_sh2s(cycles);
353 else if ((a & 0x30) == 0x30) {
354 p32x_pwm_write16(a, d);
358 p32x_reg_write8(a + 1, d);
361 // ------------------------------------------------------------------
363 static u32 p32x_vdp_read16(u32 a)
367 return Pico32x.vdp_regs[a / 2];
370 static void p32x_vdp_write8(u32 a, u32 d)
372 u16 *r = Pico32x.vdp_regs;
375 // for FEN checks between writes
378 // TODO: verify what's writeable
381 // priority inversion is handled in palette
382 if ((r[0] ^ d) & P32XV_PRI)
383 Pico32x.dirty_pal = 1;
384 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
386 case 0x03: // shift (for pp mode)
389 case 0x05: // fill len
394 Pico32x.pending_fb = d;
395 // if we are blanking and FS bit is changing
396 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
397 r[0x0a/2] ^= P32XV_FS;
398 Pico32xSwapDRAM(d ^ 1);
399 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
405 static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
408 if (a == 6) { // fill start
409 Pico32x.vdp_regs[6 / 2] = d;
412 if (a == 8) { // fill data
413 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
414 int len = Pico32x.vdp_regs[4 / 2] + 1;
416 a = Pico32x.vdp_regs[6 / 2];
419 a = (a & 0xff00) | ((a + 1) & 0xff);
421 Pico32x.vdp_regs[0x06 / 2] = a;
422 Pico32x.vdp_regs[0x08 / 2] = d;
424 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
425 p32x_event_schedule(P32X_EVENT_FILLEND, cycles, len);
430 p32x_vdp_write8(a | 1, d);
433 // ------------------------------------------------------------------
436 static u32 p32x_sh2reg_read16(u32 a, int cpuid)
438 u16 *r = Pico32x.regs;
442 case 0x00: // adapter/irq ctl
443 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
444 case 0x04: // H count (often as comm too)
445 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
447 return Pico32x.sh2_regs[4 / 2];
448 case 0x10: // DREQ len
453 if ((a & 0x38) == 0x08)
456 if ((a & 0x30) == 0x20) {
457 int comreg = 1 << (a & 0x0f) / 2;
458 if (Pico32x.comm_dirty_68k & comreg)
459 Pico32x.comm_dirty_68k &= ~comreg;
460 else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
464 if ((a & 0x30) == 0x30) {
465 sh2_poll[cpuid].cnt = 0;
466 return p32x_pwm_read16(a);
472 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
477 Pico32x.regs[0] &= ~P32XS_FM;
478 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
481 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
482 Pico32x.sh2_regs[0] &= ~0x80;
483 Pico32x.sh2_regs[0] |= d & 0x80;
485 p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // XXX: timing?
489 Pico32x.sh2_regs[4 / 2] = d & 0xff;
490 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
494 if ((a & 0x30) == 0x20) {
495 u8 *r8 = (u8 *)Pico32x.regs;
501 if (p32x_poll_undetect(&m68k_poll, 0))
503 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
504 comreg = 1 << (a & 0x0f) / 2;
505 Pico32x.comm_dirty_sh2 |= comreg;
510 static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
515 if ((a & 0x30) == 0x20) {
517 if (Pico32x.regs[a / 2] == d)
520 Pico32x.regs[a / 2] = d;
521 if (p32x_poll_undetect(&m68k_poll, 0))
523 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
524 comreg = 1 << (a & 0x0f) / 2;
525 Pico32x.comm_dirty_sh2 |= comreg;
529 else if ((a & 0x30) == 0x30) {
530 p32x_pwm_write16(a, d);
536 Pico32x.regs[0] &= ~P32XS_FM;
537 Pico32x.regs[0] |= d & P32XS_FM;
539 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
540 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
541 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
542 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
544 Pico32x.sh2irqs &= ~P32XI_PWM;
545 if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
546 p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // timing?
550 p32x_sh2reg_write8(a | 1, d, cpuid);
557 // ------------------------------------------------------------------
558 // SH2 internal peripherals
559 // we keep them in little endian format
560 static u32 sh2_peripheral_read8(u32 a, int id)
562 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
568 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
572 static u32 sh2_peripheral_read16(u32 a, int id)
574 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
580 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
584 static u32 sh2_peripheral_read32(u32 a, int id)
588 d = Pico32xMem->sh2_peri_regs[id][a / 4];
590 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
594 static int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
596 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
597 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
603 if ((a == 2 && (d & 0x20)) || // transmiter enabled
604 (a == 4 && !(d & 0x80))) { // valid data in TDR
605 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
606 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
607 int level = PREG8(oregs, 0x60) >> 4;
608 int vector = PREG8(oregs, 0x63) & 0x7f;
609 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
610 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
617 static int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
619 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
620 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
626 if ((d & 0xff00) == 0xa500) { // WTCSR
628 p32x_timers_recalc();
630 if ((d & 0xff00) == 0x5a00) // WTCNT
639 static void sh2_peripheral_write32(u32 a, u32 d, int id)
641 u32 *r = Pico32xMem->sh2_peri_regs[id];
642 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
648 // division unit (TODO: verify):
649 case 0x104: // DVDNT: divident L, starts divide
650 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
652 signed int divisor = r[0x100 / 4];
653 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
654 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
657 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
660 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
661 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
663 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
664 signed int divisor = r[0x100 / 4];
665 // XXX: undocumented mirroring to 0x118,0x11c?
666 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
668 r[0x11c / 4] = r[0x114 / 4] = divident;
670 if ((unsigned long long)divident + 1 > 1) {
671 //elprintf(EL_32X, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
672 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
676 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
680 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
681 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
682 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
683 dmac0->tcr0 &= 0xffffff;
685 // HACK: assume 68k starts writing soon and end the timeslice
688 // DREQ is only sent after first 4 words are written.
689 // we do multiple of 4 words to avoid messing up alignment
690 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
691 elprintf(EL_32X, "68k -> sh2 DMA");
697 // ------------------------------------------------------------------
701 static u32 PicoRead8_32x_on(u32 a)
704 if ((a & 0xffc0) == 0x5100) { // a15100
705 d = p32x_reg_read16(a);
709 if ((a & 0xfc00) != 0x5000)
710 return PicoRead8_io(a);
712 if ((a & 0xfff0) == 0x5180) { // a15180
713 d = p32x_vdp_read16(a);
717 if ((a & 0xfe00) == 0x5200) { // a15200
718 d = Pico32xMem->pal[(a & 0x1ff) / 2];
722 if ((a & 0xfffc) == 0x30ec) { // a130ec
727 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
737 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
741 static u32 PicoRead16_32x_on(u32 a)
744 if ((a & 0xffc0) == 0x5100) { // a15100
745 d = p32x_reg_read16(a);
749 if ((a & 0xfc00) != 0x5000)
750 return PicoRead16_io(a);
752 if ((a & 0xfff0) == 0x5180) { // a15180
753 d = p32x_vdp_read16(a);
757 if ((a & 0xfe00) == 0x5200) { // a15200
758 d = Pico32xMem->pal[(a & 0x1ff) / 2];
762 if ((a & 0xfffc) == 0x30ec) { // a130ec
763 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
767 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
771 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
775 static void PicoWrite8_32x_on(u32 a, u32 d)
777 if ((a & 0xfc00) == 0x5000)
778 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
780 if ((a & 0xffc0) == 0x5100) { // a15100
781 p32x_reg_write8(a, d);
785 if ((a & 0xfc00) != 0x5000) {
790 if ((a & 0xfff0) == 0x5180) { // a15180
791 p32x_vdp_write8(a, d);
796 if ((a & 0xfe00) == 0x5200) { // a15200
797 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
798 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
799 Pico32x.dirty_pal = 1;
803 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
806 static void PicoWrite16_32x_on(u32 a, u32 d)
808 if ((a & 0xfc00) == 0x5000)
809 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
811 if ((a & 0xffc0) == 0x5100) { // a15100
812 p32x_reg_write16(a, d);
816 if ((a & 0xfc00) != 0x5000) {
817 PicoWrite16_io(a, d);
821 if ((a & 0xfff0) == 0x5180) { // a15180
822 p32x_vdp_write16(a, d, 0); // FIXME?
826 if ((a & 0xfe00) == 0x5200) { // a15200
827 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
828 Pico32x.dirty_pal = 1;
832 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
836 u32 PicoRead8_32x(u32 a)
839 if ((a & 0xffc0) == 0x5100) { // a15100
840 // regs are always readable
841 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
845 if ((a & 0xfffc) == 0x30ec) { // a130ec
850 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
854 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
858 u32 PicoRead16_32x(u32 a)
861 if ((a & 0xffc0) == 0x5100) { // a15100
862 d = Pico32x.regs[(a & 0x3f) / 2];
866 if ((a & 0xfffc) == 0x30ec) { // a130ec
867 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
871 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
875 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
879 void PicoWrite8_32x(u32 a, u32 d)
881 if ((a & 0xffc0) == 0x5100) { // a15100
882 u16 *r = Pico32x.regs;
884 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
887 if ((d ^ r[0]) & d & P32XS_ADEN) {
889 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
891 p32x_reg_write8(a, d); // forward for reset processing
896 // allow only COMM for now
897 if ((a & 0x30) == 0x20) {
904 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
907 void PicoWrite16_32x(u32 a, u32 d)
909 if ((a & 0xffc0) == 0x5100) { // a15100
910 u16 *r = Pico32x.regs;
912 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
915 if ((d ^ r[0]) & d & P32XS_ADEN) {
917 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
919 p32x_reg_write16(a, d); // forward for reset processing
924 // allow only COMM for now
925 if ((a & 0x30) == 0x20)
930 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
933 // -----------------------------------------------------------------
935 // hint vector is writeable
936 static void PicoWrite8_hint(u32 a, u32 d)
938 if ((a & 0xfffc) == 0x0070) {
939 Pico32xMem->m68k_rom[a ^ 1] = d;
943 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
946 static void PicoWrite16_hint(u32 a, u32 d)
948 if ((a & 0xfffc) == 0x0070) {
949 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
953 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
956 static void bank_switch(int b)
958 unsigned int rs, bank;
961 if (bank >= Pico.romsize) {
962 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
966 // 32X ROM (unbanked, XXX: consider mirroring?)
967 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
971 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
972 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
974 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
977 // setup FAME fetchmap
978 for (rs = 0x90; rs < 0xa0; rs++)
979 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
983 // -----------------------------------------------------------------
985 // -----------------------------------------------------------------
988 static u32 sh2_read8_unmapped(u32 a, int id)
990 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
991 id ? 's' : 'm', a, 0, sh2_pc(id));
995 static u32 sh2_read8_cs0(u32 a, int id)
999 // 0x3ff00 is veridied
1000 if ((a & 0x3ff00) == 0x4000) {
1001 d = p32x_sh2reg_read16(a, id);
1005 if ((a & 0x3ff00) == 0x4100) {
1006 d = p32x_vdp_read16(a);
1007 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
1013 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
1014 return Pico32xMem->sh2_rom_m[a ^ 1];
1015 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
1016 return Pico32xMem->sh2_rom_s[a ^ 1];
1018 if ((a & 0x3fe00) == 0x4200) {
1019 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1023 return sh2_read8_unmapped(a, id);
1031 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
1032 id ? 's' : 'm', a, d, sh2_pc(id));
1036 static u32 sh2_read8_da(u32 a, int id)
1038 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
1042 static u32 sh2_read16_unmapped(u32 a, int id)
1044 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
1045 id ? 's' : 'm', a, 0, sh2_pc(id));
1049 static u32 sh2_read16_cs0(u32 a, int id)
1053 if ((a & 0x3ff00) == 0x4000) {
1054 d = p32x_sh2reg_read16(a, id);
1055 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1060 if ((a & 0x3ff00) == 0x4100) {
1061 d = p32x_vdp_read16(a);
1062 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
1067 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
1068 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
1069 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
1070 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
1072 if ((a & 0x3fe00) == 0x4200) {
1073 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1077 return sh2_read16_unmapped(a, id);
1080 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
1081 id ? 's' : 'm', a, d, sh2_pc(id));
1085 static u32 sh2_read16_da(u32 a, int id)
1087 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
1090 static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
1096 static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
1098 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
1099 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1103 static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
1105 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
1106 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1108 if ((a & 0x3ff00) == 0x4100) {
1109 p32x_vdp_write8(a, d);
1113 if ((a & 0x3ff00) == 0x4000) {
1114 p32x_sh2reg_write8(a, d, id);
1118 return sh2_write8_unmapped(a, d, id);
1121 /* quirk: in both normal and overwrite areas only nonzero values go through */
1122 #define sh2_write8_dramN(n) \
1123 if ((d & 0xff) != 0) { \
1124 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1125 dram[(a & 0x1ffff) ^ 1] = d; \
1129 static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
1131 sh2_write8_dramN(0);
1134 static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
1136 sh2_write8_dramN(1);
1139 static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
1141 u32 a1 = a & 0x3ffff;
1143 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1145 sh2_drc_wcheck_ram(a, t, id);
1147 Pico32xMem->sdram[a1 ^ 1] = d;
1151 static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
1155 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1157 sh2_drc_wcheck_da(a, t, id);
1159 Pico32xMem->data_array[id][a1 ^ 1] = d;
1164 static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
1166 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1167 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1171 static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
1173 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1174 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
1175 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1177 if ((a & 0x3ff00) == 0x4100) {
1178 sh2_poll[id].cnt = 0; // for poll before VDP accesses
1179 p32x_vdp_write16(a, d, sh2s[id].m68krcycles_done);
1183 if ((a & 0x3fe00) == 0x4200) {
1184 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1185 Pico32x.dirty_pal = 1;
1189 if ((a & 0x3ff00) == 0x4000) {
1190 p32x_sh2reg_write16(a, d, id);
1194 return sh2_write16_unmapped(a, d, id);
1197 #define sh2_write16_dramN(n) \
1198 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1199 if (!(a & 0x20000)) { \
1204 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1205 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1209 static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
1211 sh2_write16_dramN(0);
1214 static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
1216 sh2_write16_dramN(1);
1219 static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
1221 u32 a1 = a & 0x3ffff;
1223 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1225 sh2_drc_wcheck_ram(a, t, id);
1227 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1231 static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
1235 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1237 sh2_drc_wcheck_da(a, t, id);
1239 ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
1245 uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
1249 typedef u32 (sh2_read_handler)(u32 a, int id);
1250 typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
1252 #define SH2MAP_ADDR2OFFS_R(a) \
1253 ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
1255 #define SH2MAP_ADDR2OFFS_W(a) \
1256 ((u32)(a) >> SH2_WRITE_SHIFT)
1258 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1260 const sh2_memmap *sh2_map = sh2->read8_map;
1263 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1265 if (map_flag_set(p))
1266 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1268 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1271 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1273 const sh2_memmap *sh2_map = sh2->read16_map;
1276 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1278 if (map_flag_set(p))
1279 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1281 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1284 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1286 const sh2_memmap *sh2_map = sh2->read16_map;
1287 sh2_read_handler *handler;
1291 offs = SH2MAP_ADDR2OFFS_R(a);
1294 if (!map_flag_set(p)) {
1295 // XXX: maybe 32bit access instead with ror?
1296 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1297 return (pd[0] << 16) | pd[1];
1301 return sh2_peripheral_read32(a, sh2->is_slave);
1303 handler = (sh2_read_handler *)(p << 1);
1304 return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
1307 // return nonzero if write potentially causes an interrupt (used by drc)
1308 int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1310 const void **sh2_wmap = sh2->write8_tab;
1311 sh2_write_handler *wh;
1313 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1314 return wh(a, d, sh2->is_slave);
1317 int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1319 const void **sh2_wmap = sh2->write16_tab;
1320 sh2_write_handler *wh;
1322 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1323 return wh(a, d, sh2->is_slave);
1326 int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1328 const void **sh2_wmap = sh2->write16_tab;
1329 sh2_write_handler *handler;
1332 offs = SH2MAP_ADDR2OFFS_W(a);
1334 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1335 sh2_peripheral_write32(a, d, sh2->is_slave);
1339 handler = sh2_wmap[offs];
1340 handler(a, d >> 16, sh2->is_slave);
1341 handler(a + 2, d, sh2->is_slave);
1345 // -----------------------------------------------------------------
1347 static const u16 msh2_code[] = {
1348 // trap instructions
1349 0xaffe, // bra <self>
1351 // have to wait a bit until m68k initial program finishes clearing stuff
1352 // to avoid races with game SH2 code, like in Tempo
1353 0xd004, // mov.l @(_m_ok,pc), r0
1354 0xd105, // mov.l @(_cnt,pc), r1
1355 0xd205, // mov.l @(_start,pc), r2
1356 0x71ff, // add #-1, r1
1357 0x4115, // cmp/pl r1
1359 0xc208, // mov.l r0, @(h'20,gbr)
1360 0x6822, // mov.l @r2, r8
1363 ('M'<<8)|'_', ('O'<<8)|'K',
1365 0x2200, 0x03e0 // master start pointer in ROM
1368 static const u16 ssh2_code[] = {
1369 0xaffe, // bra <self>
1371 // code to wait for master, in case authentic master BIOS is used
1372 0xd104, // mov.l @(_m_ok,pc), r1
1373 0xd206, // mov.l @(_start,pc), r2
1374 0xc608, // mov.l @(h'20,gbr), r0
1375 0x3100, // cmp/eq r0, r1
1377 0xd003, // mov.l @(_s_ok,pc), r0
1378 0xc209, // mov.l r0, @(h'24,gbr)
1379 0x6822, // mov.l @r2, r8
1382 ('M'<<8)|'_', ('O'<<8)|'K',
1383 ('S'<<8)|'_', ('O'<<8)|'K',
1384 0x2200, 0x03e4 // slave start pointer in ROM
1387 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
1388 static void get_bios(void)
1395 if (p32x_bios_g != NULL) {
1396 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1397 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1401 ps = (u16 *)Pico32xMem->m68k_rom;
1403 for (i = 1; i < 0xc0/4; i++)
1404 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1407 for (i = 0xc0/2; i < 0x100/2; i++)
1411 ps[0xc0/2] = 0x46fc;
1412 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1413 ps[0xfe/2] = 0x60fe; // jump to self
1415 ps[0xfe/2] = 0x4e75; // rts
1418 // fill remaining m68k_rom page with game ROM
1419 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1420 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1421 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1424 if (p32x_bios_m != NULL) {
1425 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1426 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1429 pl = (u32 *)Pico32xMem->sh2_rom_m;
1431 // fill exception vector table to our trap address
1432 for (i = 0; i < 128; i++)
1433 pl[i] = HWSWAP(0x200);
1436 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1439 pl[1] = pl[3] = HWSWAP(0x6040000);
1441 pl[0] = pl[2] = HWSWAP(0x204);
1445 if (p32x_bios_s != NULL) {
1446 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1447 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1450 pl = (u32 *)Pico32xMem->sh2_rom_s;
1452 // fill exception vector table to our trap address
1453 for (i = 0; i < 128; i++)
1454 pl[i] = HWSWAP(0x200);
1457 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1460 pl[1] = pl[3] = HWSWAP(0x603f800);
1462 pl[0] = pl[2] = HWSWAP(0x204);
1466 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1467 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1469 static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
1470 // for writes we are using handlers only
1471 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1473 void Pico32xSwapDRAM(int b)
1475 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1476 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1477 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1478 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1481 sh2_read8_map[2].addr = sh2_read8_map[6].addr =
1482 sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1484 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1485 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1488 void PicoMemSetup32x(void)
1493 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1494 if (Pico32xMem == NULL) {
1495 elprintf(EL_STATUS, "OOM");
1499 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
1503 // cartridge area becomes unmapped
1504 // XXX: we take the easy way and don't unmap ROM,
1505 // so that we can avoid handling the RV bit.
1506 // m68k_map_unmap(0x000000, 0x3fffff);
1509 rs = sizeof(Pico32xMem->m68k_rom_bank);
1510 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1511 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1512 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1513 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1515 // 32X ROM (unbanked, XXX: consider mirroring?)
1516 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1519 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1520 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1522 // setup FAME fetchmap
1523 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1524 for (rs = 0x88; rs < 0x90; rs++)
1525 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1532 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1533 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1534 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1535 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1537 // SH2 maps: A31,A30,A29,CS1,CS0
1538 // all unmapped by default
1539 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1540 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1541 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1544 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1545 sh2_write8_map[i] = sh2_write8_unmapped;
1546 sh2_write16_map[i] = sh2_write16_unmapped;
1550 for (i = 0x40; i <= 0x5f; i++) {
1551 sh2_write8_map[i >> 1] =
1552 sh2_write16_map[i >> 1] = sh2_write_ignore;
1556 sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
1557 sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
1558 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1559 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1561 sh2_read8_map[1].addr = sh2_read8_map[5].addr =
1562 sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
1563 sh2_read8_map[1].mask = sh2_read8_map[5].mask =
1564 sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME
1565 // CS2 - DRAM - done by Pico32xSwapDRAM()
1566 sh2_read8_map[2].mask = sh2_read8_map[6].mask =
1567 sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff;
1569 sh2_read8_map[3].addr = sh2_read8_map[7].addr =
1570 sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
1571 sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
1572 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1573 sh2_read8_map[3].mask = sh2_read8_map[7].mask =
1574 sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
1576 sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
1577 sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
1578 sh2_write8_map[0xc0/2] = sh2_write8_da;
1579 sh2_write16_map[0xc0/2] = sh2_write16_da;
1581 sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
1582 sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
1583 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1584 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1586 // map DRAM area, both 68k and SH2
1589 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1590 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1591 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1592 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1594 // setup poll detector
1595 m68k_poll.flag = P32XF_68KPOLL;
1596 m68k_poll.cyc_max = 64;
1597 sh2_poll[0].flag = P32XF_MSH2POLL;
1598 sh2_poll[0].cyc_max = 21;
1599 sh2_poll[1].flag = P32XF_SSH2POLL;
1600 sh2_poll[1].cyc_max = 16;
1603 sh2_drc_mem_setup(&msh2);
1604 sh2_drc_mem_setup(&ssh2);
1608 void Pico32xStateLoaded(void)
1610 bank_switch(Pico32x.regs[4 / 2]);
1611 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1612 p32x_poll_event(3, 0);
1613 Pico32x.dirty_pal = 1;
1614 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1615 p32x_timers_recalc();
1617 sh2_drc_flush_all();
1621 // vim:shiftwidth=2:ts=2:expandtab