3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
10 * a15102 ........ ......SM ? 4002 // intS intM
11 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
12 * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
13 * a15108 (32bit DREQ src) 4008
14 * a1510c (32bit DREQ dst) 400c
15 * a15110 llllllll llllll00 4010 // DREQ Len
16 * a15112 (16bit FIFO reg) 4012
17 * a15114 ? (16bit VRES clr) 4014
18 * a15116 ? (16bit Vint clr) 4016
19 * a15118 ? (16bit Hint clr) 4018
20 * a1511a ........ .......C (16bit CMD clr) 401a // Cm
21 * a1511c ? (16bit PWM clr) 401c
23 * a15120 (16 bytes comm) 2020
27 * iii. .cc. ..xx * // Internal, Cs, x
29 * sh2 map, wait/bus cycles (from docs):
31 * rom 0000000-0003fff 1 -
32 * sys reg 0004000-00040ff 1 1
33 * vdp reg 0004100-00041ff 5 5
34 * vdp pal 0004200-00043ff 5 5
35 * rom 2000000-23fffff 6-15
36 * dram/fb 4000000-401ffff 5-12 1-3
37 * fb ovr 4020000-403ffff
38 * sdram 6000000-603ffff 12 2 (cycles)
41 #include "../pico_int.h"
42 #include "../memory.h"
43 #include "../../cpu/sh2/compiler.h"
45 static const char str_mars[] = "MARS";
47 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
48 struct Pico32xMem *Pico32xMem;
50 static void bank_switch(int b);
53 #define POLL_THRESHOLD 3
60 static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
64 if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
65 && cycles - m68k_poll.cycles <= 64)
67 if (m68k_poll.cnt++ > POLL_THRESHOLD) {
68 if (!(Pico32x.emu_flags & flags)) {
69 elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
70 a, cycles - m68k_poll.cycles);
73 Pico32x.emu_flags |= flags;
80 m68k_poll.cycles = cycles;
85 void p32x_m68k_poll_event(u32 flags)
87 if (Pico32x.emu_flags & flags) {
88 elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
89 Pico32x.emu_flags & ~flags);
90 Pico32x.emu_flags &= ~flags;
93 m68k_poll.addr = m68k_poll.cnt = 0;
96 static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags)
98 int cycles_left = sh2_cycles_left(sh2);
100 if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
101 if (sh2->poll_cnt++ > 3) {
102 if (!(sh2->state & flags))
103 elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
104 sh2->state, sh2->state | flags);
108 pevt_log_sh2(sh2, EVT_POLL_START);
115 sh2->poll_cycles = cycles_left;
118 void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
120 if (sh2->state & flags) {
121 elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
122 sh2->state, sh2->state & ~flags);
124 if (sh2->m68krcycles_done < m68k_cycles)
125 sh2->m68krcycles_done = m68k_cycles;
127 pevt_log_sh2_o(sh2, EVT_POLL_END);
130 sh2->state &= ~flags;
131 sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
134 static void sh2s_sync_on_read(SH2 *sh2)
137 if (sh2->poll_cnt != 0)
140 cycles = sh2_cycles_done(sh2);
142 p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
148 static int p32x_csum_faked;
149 static const u16 comm_fakevals[] = {
150 0x4d5f, 0x4f4b, // M_OK
151 0x535f, 0x4f4b, // S_OK
152 0x4D41, 0x5346, // MASF - Brutal Unleashed
153 0x5331, 0x4d31, // Darxide
156 0x0000, 0x0000, // eq for doom
157 0x0002, // Mortal Kombat
161 static u32 sh2_comm_faker(u32 a)
164 if (a == 0x28 && !p32x_csum_faked) {
166 return *(unsigned short *)(Pico.rom + 0x18e);
168 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
170 return comm_fakevals[f++];
174 // ------------------------------------------------------------------
177 static u32 p32x_reg_read16(u32 a)
182 if ((a & 0x30) == 0x20)
183 return sh2_comm_faker(a);
185 if ((a & 0x30) == 0x20) {
187 unsigned int cycles = SekCyclesDoneT();
188 int comreg = 1 << (a & 0x0f) / 2;
190 // evil X-Men proto polls in a dbra loop and expects it to expire..
191 if (SekDar(2) != dr2)
195 if (cycles - msh2.m68krcycles_done > 500)
196 p32x_sync_sh2s(cycles);
197 if (Pico32x.comm_dirty_sh2 & comreg)
198 Pico32x.comm_dirty_sh2 &= ~comreg;
199 else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
208 if (a == 2) { // INTM, INTS
209 unsigned int cycles = SekCyclesDoneT();
210 if (cycles - msh2.m68krcycles_done > 64)
211 p32x_sync_sh2s(cycles);
212 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
215 if ((a & 0x30) == 0x30)
216 return p32x_pwm_read16(a, SekCyclesDoneT());
219 return Pico32x.regs[a / 2];
222 static void p32x_reg_write8(u32 a, u32 d)
224 u16 *r = Pico32x.regs;
227 // for things like bset on comm port
231 case 0: // adapter ctl
232 r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
234 case 1: // adapter ctl, RES bit writeable
235 if ((d ^ r[0]) & d & P32XS_nRES)
237 r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
240 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
241 p32x_sync_sh2s(SekCyclesDoneT());
242 Pico32x.sh2irqi[0] |= P32XI_CMD;
243 p32x_update_irls(NULL);
245 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
246 p32x_sync_sh2s(SekCyclesDoneT());
247 Pico32x.sh2irqi[1] |= P32XI_CMD;
248 p32x_update_irls(NULL);
259 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
266 if ((a & 0x30) == 0x20) {
268 int cycles = SekCyclesDoneT();
274 comreg = 1 << (a & 0x0f) / 2;
275 if (Pico32x.comm_dirty_68k & comreg)
276 p32x_sync_sh2s(cycles);
279 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
280 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
281 Pico32x.comm_dirty_68k |= comreg;
283 if (cycles - (int)msh2.m68krcycles_done > 120)
284 p32x_sync_sh2s(cycles);
289 static void p32x_reg_write16(u32 a, u32 d)
291 u16 *r = Pico32x.regs;
294 // for things like bset on comm port
298 case 0x00: // adapter ctl
299 if ((d ^ r[0]) & d & P32XS_nRES)
301 r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
303 case 0x10: // DREQ len
306 case 0x12: // FIFO reg
307 if (!(r[6 / 2] & P32XS_68S)) {
308 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
311 if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
312 Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
313 if ((Pico32x.dmac0_fifo_ptr & 3) == 0)
314 p32x_dreq0_trigger();
315 if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
316 r[6 / 2] |= P32XS_FULL;
322 if ((a & 0x38) == 0x08) {
327 else if ((a & 0x30) == 0x20) {
328 int cycles = SekCyclesDoneT();
334 comreg = 1 << (a & 0x0f) / 2;
335 if (Pico32x.comm_dirty_68k & comreg)
336 p32x_sync_sh2s(cycles);
339 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
340 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
341 Pico32x.comm_dirty_68k |= comreg;
343 if (cycles - (int)msh2.m68krcycles_done > 120)
344 p32x_sync_sh2s(cycles);
348 else if ((a & 0x30) == 0x30) {
349 p32x_pwm_write16(a, d, SekCyclesDoneT());
353 p32x_reg_write8(a + 1, d);
356 // ------------------------------------------------------------------
358 static u32 p32x_vdp_read16(u32 a)
362 return Pico32x.vdp_regs[a / 2];
365 static void p32x_vdp_write8(u32 a, u32 d)
367 u16 *r = Pico32x.vdp_regs;
370 // TODO: verify what's writeable
373 // priority inversion is handled in palette
374 if ((r[0] ^ d) & P32XV_PRI)
375 Pico32x.dirty_pal = 1;
376 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
378 case 0x03: // shift (for pp mode)
381 case 0x05: // fill len
386 Pico32x.pending_fb = d;
387 // if we are blanking and FS bit is changing
388 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
389 r[0x0a/2] ^= P32XV_FS;
390 Pico32xSwapDRAM(d ^ 1);
391 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
397 static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
400 if (a == 6) { // fill start
401 Pico32x.vdp_regs[6 / 2] = d;
404 if (a == 8) { // fill data
405 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
406 int len = Pico32x.vdp_regs[4 / 2] + 1;
408 a = Pico32x.vdp_regs[6 / 2];
411 a = (a & 0xff00) | ((a + 1) & 0xff);
413 Pico32x.vdp_regs[0x06 / 2] = a;
414 Pico32x.vdp_regs[0x08 / 2] = d;
415 if (sh2 != NULL && len > 4) {
416 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
417 // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
418 p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
423 p32x_vdp_write8(a | 1, d);
426 // ------------------------------------------------------------------
429 static u32 p32x_sh2reg_read16(u32 a, int cpuid)
431 u16 *r = Pico32x.regs;
435 case 0x00: // adapter/irq ctl
436 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
437 case 0x04: // H count (often as comm too)
438 sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
439 sh2s_sync_on_read(&sh2s[cpuid]);
440 return Pico32x.sh2_regs[4 / 2];
441 case 0x10: // DREQ len
446 if ((a & 0x38) == 0x08)
449 if ((a & 0x30) == 0x20) {
450 int comreg = 1 << (a & 0x0f) / 2;
451 if (Pico32x.comm_dirty_68k & comreg)
452 Pico32x.comm_dirty_68k &= ~comreg;
454 sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
455 sh2s_sync_on_read(&sh2s[cpuid]);
458 if ((a & 0x30) == 0x30) {
459 return p32x_pwm_read16(a, sh2_cycles_done_m68k(&sh2s[cpuid]));
465 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
469 sh2s[cpuid].poll_addr = 0;
473 Pico32x.regs[0] &= ~P32XS_FM;
474 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
476 case 1: // HEN/irq masks
477 if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
478 elprintf(EL_ANOMALY|EL_32X, "HEN");
479 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
480 Pico32x.sh2_regs[0] &= ~0x80;
481 Pico32x.sh2_regs[0] |= d & 0x80;
483 p32x_pwm_schedule_sh2(&sh2s[cpuid]);
484 p32x_update_irls(&sh2s[cpuid]);
488 if (Pico32x.sh2_regs[4 / 2] != d) {
489 Pico32x.sh2_regs[4 / 2] = d;
490 p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
491 sh2_cycles_done_m68k(&sh2s[cpuid]));
492 sh2_end_run(&sh2s[cpuid], 4);
497 if ((a & 0x30) == 0x20) {
498 u8 *r8 = (u8 *)Pico32x.regs;
504 p32x_m68k_poll_event(P32XF_68KCPOLL);
505 p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
506 sh2_cycles_done_m68k(&sh2s[cpuid]));
507 comreg = 1 << (a & 0x0f) / 2;
508 Pico32x.comm_dirty_sh2 |= comreg;
513 static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
517 sh2s[cpuid].poll_addr = 0;
520 if ((a & 0x30) == 0x20) {
522 if (Pico32x.regs[a / 2] == d)
525 Pico32x.regs[a / 2] = d;
526 p32x_m68k_poll_event(P32XF_68KCPOLL);
527 p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
528 sh2_cycles_done_m68k(&sh2s[cpuid]));
529 comreg = 1 << (a & 0x0f) / 2;
530 Pico32x.comm_dirty_sh2 |= comreg;
534 else if ((a & 0x30) == 0x30) {
535 p32x_pwm_write16(a, d, sh2_cycles_done_m68k(&sh2s[cpuid]));
541 Pico32x.regs[0] &= ~P32XS_FM;
542 Pico32x.regs[0] |= d & P32XS_FM;
544 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
545 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
546 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
547 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
549 Pico32x.sh2irqs &= ~P32XI_PWM;
550 p32x_pwm_schedule_sh2(&sh2s[cpuid]);
554 p32x_sh2reg_write8(a | 1, d, cpuid);
558 p32x_update_irls(&sh2s[cpuid]);
561 // ------------------------------------------------------------------
565 static u32 PicoRead8_32x_on(u32 a)
568 if ((a & 0xffc0) == 0x5100) { // a15100
569 d = p32x_reg_read16(a);
573 if ((a & 0xfc00) != 0x5000)
574 return PicoRead8_io(a);
576 if ((a & 0xfff0) == 0x5180) { // a15180
577 d = p32x_vdp_read16(a);
581 if ((a & 0xfe00) == 0x5200) { // a15200
582 d = Pico32xMem->pal[(a & 0x1ff) / 2];
586 if ((a & 0xfffc) == 0x30ec) { // a130ec
591 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
601 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
605 static u32 PicoRead16_32x_on(u32 a)
608 if ((a & 0xffc0) == 0x5100) { // a15100
609 d = p32x_reg_read16(a);
613 if ((a & 0xfc00) != 0x5000)
614 return PicoRead16_io(a);
616 if ((a & 0xfff0) == 0x5180) { // a15180
617 d = p32x_vdp_read16(a);
621 if ((a & 0xfe00) == 0x5200) { // a15200
622 d = Pico32xMem->pal[(a & 0x1ff) / 2];
626 if ((a & 0xfffc) == 0x30ec) { // a130ec
627 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
631 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
635 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
639 static void PicoWrite8_32x_on(u32 a, u32 d)
641 if ((a & 0xfc00) == 0x5000)
642 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
644 if ((a & 0xffc0) == 0x5100) { // a15100
645 p32x_reg_write8(a, d);
649 if ((a & 0xfc00) != 0x5000) {
654 if (!(Pico32x.regs[0] & P32XS_FM)) {
655 if ((a & 0xfff0) == 0x5180) { // a15180
656 p32x_vdp_write8(a, d);
661 if ((a & 0xfe00) == 0x5200) { // a15200
662 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
663 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
664 Pico32x.dirty_pal = 1;
669 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
672 static void PicoWrite16_32x_on(u32 a, u32 d)
674 if ((a & 0xfc00) == 0x5000)
675 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
677 if ((a & 0xffc0) == 0x5100) { // a15100
678 p32x_reg_write16(a, d);
682 if ((a & 0xfc00) != 0x5000) {
683 PicoWrite16_io(a, d);
687 if (!(Pico32x.regs[0] & P32XS_FM)) {
688 if ((a & 0xfff0) == 0x5180) { // a15180
689 p32x_vdp_write16(a, d, NULL); // FIXME?
693 if ((a & 0xfe00) == 0x5200) { // a15200
694 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
695 Pico32x.dirty_pal = 1;
700 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
704 u32 PicoRead8_32x(u32 a)
707 if ((a & 0xffc0) == 0x5100) { // a15100
708 // regs are always readable
709 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
713 if ((a & 0xfffc) == 0x30ec) { // a130ec
718 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
722 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
726 u32 PicoRead16_32x(u32 a)
729 if ((a & 0xffc0) == 0x5100) { // a15100
730 d = Pico32x.regs[(a & 0x3f) / 2];
734 if ((a & 0xfffc) == 0x30ec) { // a130ec
735 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
739 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
743 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
747 void PicoWrite8_32x(u32 a, u32 d)
749 if ((a & 0xffc0) == 0x5100) { // a15100
750 u16 *r = Pico32x.regs;
752 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
755 if ((d ^ r[0]) & d & P32XS_ADEN) {
757 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
759 p32x_reg_write8(a, d); // forward for reset processing
764 // allow only COMM for now
765 if ((a & 0x30) == 0x20) {
772 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
775 void PicoWrite16_32x(u32 a, u32 d)
777 if ((a & 0xffc0) == 0x5100) { // a15100
778 u16 *r = Pico32x.regs;
780 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
783 if ((d ^ r[0]) & d & P32XS_ADEN) {
785 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
787 p32x_reg_write16(a, d); // forward for reset processing
792 // allow only COMM for now
793 if ((a & 0x30) == 0x20)
798 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
801 /* quirk: in both normal and overwrite areas only nonzero values go through */
802 #define sh2_write8_dramN(n) \
803 if ((d & 0xff) != 0) { \
804 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
805 dram[(a & 0x1ffff) ^ 1] = d; \
808 static void m68k_write8_dram0_ow(u32 a, u32 d)
813 static void m68k_write8_dram1_ow(u32 a, u32 d)
818 #define sh2_write16_dramN(n, ret) \
819 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
820 if (!(a & 0x20000)) { \
825 if (!(d & 0xff00)) d |= *pd & 0xff00; \
826 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
830 static void m68k_write16_dram0_ow(u32 a, u32 d)
832 sh2_write16_dramN(0,);
835 static void m68k_write16_dram1_ow(u32 a, u32 d)
837 sh2_write16_dramN(1,);
840 // -----------------------------------------------------------------
842 // hint vector is writeable
843 static void PicoWrite8_hint(u32 a, u32 d)
845 if ((a & 0xfffc) == 0x0070) {
846 Pico32xMem->m68k_rom[a ^ 1] = d;
850 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
853 static void PicoWrite16_hint(u32 a, u32 d)
855 if ((a & 0xfffc) == 0x0070) {
856 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
860 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
863 static void bank_switch(int b)
865 unsigned int rs, bank;
868 if (bank >= Pico.romsize) {
869 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
873 // 32X ROM (unbanked, XXX: consider mirroring?)
874 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
878 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
879 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
881 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
884 // setup FAME fetchmap
885 for (rs = 0x90; rs < 0xa0; rs++)
886 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
890 // -----------------------------------------------------------------
892 // -----------------------------------------------------------------
895 static u32 sh2_read8_unmapped(u32 a, int id)
897 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
898 id ? 's' : 'm', a, 0, sh2_pc(id));
902 static u32 sh2_read8_cs0(u32 a, int id)
906 // 0x3ff00 is veridied
907 if ((a & 0x3ff00) == 0x4000) {
908 d = p32x_sh2reg_read16(a, id);
912 if ((a & 0x3ff00) == 0x4100) {
913 d = p32x_vdp_read16(a);
914 sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
919 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
920 return Pico32xMem->sh2_rom_m[a ^ 1];
921 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
922 return Pico32xMem->sh2_rom_s[a ^ 1];
924 if ((a & 0x3fe00) == 0x4200) {
925 d = Pico32xMem->pal[(a & 0x1ff) / 2];
929 return sh2_read8_unmapped(a, id);
937 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
938 id ? 's' : 'm', a, d, sh2_pc(id));
942 static u32 sh2_read8_da(u32 a, int id)
944 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
948 static u32 sh2_read16_unmapped(u32 a, int id)
950 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
951 id ? 's' : 'm', a, 0, sh2_pc(id));
955 static u32 sh2_read16_cs0(u32 a, int id)
959 if ((a & 0x3ff00) == 0x4000) {
960 d = p32x_sh2reg_read16(a, id);
961 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
966 if ((a & 0x3ff00) == 0x4100) {
967 d = p32x_vdp_read16(a);
968 sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
972 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
973 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
974 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
975 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
977 if ((a & 0x3fe00) == 0x4200) {
978 d = Pico32xMem->pal[(a & 0x1ff) / 2];
982 return sh2_read16_unmapped(a, id);
985 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
986 id ? 's' : 'm', a, d, sh2_pc(id));
990 static u32 sh2_read16_da(u32 a, int id)
992 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
995 static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
1001 static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
1003 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
1004 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1008 static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
1010 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
1011 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1013 if (Pico32x.regs[0] & P32XS_FM) {
1014 if ((a & 0x3ff00) == 0x4100) {
1015 sh2s[id].poll_addr = 0;
1016 p32x_vdp_write8(a, d);
1021 if ((a & 0x3ff00) == 0x4000) {
1022 p32x_sh2reg_write8(a, d, id);
1026 return sh2_write8_unmapped(a, d, id);
1029 static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
1031 sh2_write8_dramN(0);
1035 static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
1037 sh2_write8_dramN(1);
1041 static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
1043 u32 a1 = a & 0x3ffff;
1045 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1047 sh2_drc_wcheck_ram(a, t, id);
1049 Pico32xMem->sdram[a1 ^ 1] = d;
1053 static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
1057 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1059 sh2_drc_wcheck_da(a, t, id);
1061 Pico32xMem->data_array[id][a1 ^ 1] = d;
1066 static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
1068 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1069 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1073 static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
1075 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1076 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
1077 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1079 if (Pico32x.regs[0] & P32XS_FM) {
1080 if ((a & 0x3ff00) == 0x4100) {
1081 sh2s[id].poll_addr = 0;
1082 p32x_vdp_write16(a, d, &sh2s[id]);
1086 if ((a & 0x3fe00) == 0x4200) {
1087 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1088 Pico32x.dirty_pal = 1;
1093 if ((a & 0x3ff00) == 0x4000) {
1094 p32x_sh2reg_write16(a, d, id);
1098 return sh2_write16_unmapped(a, d, id);
1101 static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
1103 sh2_write16_dramN(0, 0);
1106 static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
1108 sh2_write16_dramN(1, 0);
1111 static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
1113 u32 a1 = a & 0x3ffff;
1115 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1117 sh2_drc_wcheck_ram(a, t, id);
1119 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1123 static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
1127 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1129 sh2_drc_wcheck_da(a, t, id);
1131 ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
1136 typedef u32 (sh2_read_handler)(u32 a, int id);
1137 typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
1139 #define SH2MAP_ADDR2OFFS_R(a) \
1140 ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
1142 #define SH2MAP_ADDR2OFFS_W(a) \
1143 ((u32)(a) >> SH2_WRITE_SHIFT)
1145 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1147 const sh2_memmap *sh2_map = sh2->read8_map;
1150 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1152 if (map_flag_set(p))
1153 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1155 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1158 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1160 const sh2_memmap *sh2_map = sh2->read16_map;
1163 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1165 if (map_flag_set(p))
1166 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1168 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1171 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1173 const sh2_memmap *sh2_map = sh2->read16_map;
1174 sh2_read_handler *handler;
1178 offs = SH2MAP_ADDR2OFFS_R(a);
1181 if (!map_flag_set(p)) {
1182 // XXX: maybe 32bit access instead with ror?
1183 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1184 return (pd[0] << 16) | pd[1];
1188 return sh2_peripheral_read32(a, sh2->is_slave);
1190 handler = (sh2_read_handler *)(p << 1);
1191 return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
1194 // return nonzero if write potentially causes an interrupt (used by drc)
1195 int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1197 const void **sh2_wmap = sh2->write8_tab;
1198 sh2_write_handler *wh;
1200 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1201 return wh(a, d, sh2->is_slave);
1204 int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1206 const void **sh2_wmap = sh2->write16_tab;
1207 sh2_write_handler *wh;
1209 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1210 return wh(a, d, sh2->is_slave);
1213 int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1215 const void **sh2_wmap = sh2->write16_tab;
1216 sh2_write_handler *handler;
1219 offs = SH2MAP_ADDR2OFFS_W(a);
1221 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1222 sh2_peripheral_write32(a, d, sh2->is_slave);
1226 handler = sh2_wmap[offs];
1227 handler(a, d >> 16, sh2->is_slave);
1228 handler(a + 2, d, sh2->is_slave);
1232 // -----------------------------------------------------------------
1234 static const u16 msh2_code[] = {
1235 // trap instructions
1236 0xaffe, // bra <self>
1238 // have to wait a bit until m68k initial program finishes clearing stuff
1239 // to avoid races with game SH2 code, like in Tempo
1240 0xd004, // mov.l @(_m_ok,pc), r0
1241 0xd105, // mov.l @(_cnt,pc), r1
1242 0xd205, // mov.l @(_start,pc), r2
1243 0x71ff, // add #-1, r1
1244 0x4115, // cmp/pl r1
1246 0xc208, // mov.l r0, @(h'20,gbr)
1247 0x6822, // mov.l @r2, r8
1250 ('M'<<8)|'_', ('O'<<8)|'K',
1252 0x2200, 0x03e0 // master start pointer in ROM
1255 static const u16 ssh2_code[] = {
1256 0xaffe, // bra <self>
1258 // code to wait for master, in case authentic master BIOS is used
1259 0xd104, // mov.l @(_m_ok,pc), r1
1260 0xd206, // mov.l @(_start,pc), r2
1261 0xc608, // mov.l @(h'20,gbr), r0
1262 0x3100, // cmp/eq r0, r1
1264 0xd003, // mov.l @(_s_ok,pc), r0
1265 0xc209, // mov.l r0, @(h'24,gbr)
1266 0x6822, // mov.l @r2, r8
1269 ('M'<<8)|'_', ('O'<<8)|'K',
1270 ('S'<<8)|'_', ('O'<<8)|'K',
1271 0x2200, 0x03e4 // slave start pointer in ROM
1274 #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
1275 static void get_bios(void)
1282 if (p32x_bios_g != NULL) {
1283 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1284 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1288 ps = (u16 *)Pico32xMem->m68k_rom;
1290 for (i = 1; i < 0xc0/4; i++)
1291 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1294 for (i = 0xc0/2; i < 0x100/2; i++)
1298 ps[0xc0/2] = 0x46fc;
1299 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1300 ps[0xfe/2] = 0x60fe; // jump to self
1302 ps[0xfe/2] = 0x4e75; // rts
1305 // fill remaining m68k_rom page with game ROM
1306 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1307 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1308 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1311 if (p32x_bios_m != NULL) {
1312 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1313 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1316 pl = (u32 *)Pico32xMem->sh2_rom_m;
1318 // fill exception vector table to our trap address
1319 for (i = 0; i < 128; i++)
1320 pl[i] = HWSWAP(0x200);
1323 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1326 pl[1] = pl[3] = HWSWAP(0x6040000);
1328 pl[0] = pl[2] = HWSWAP(0x204);
1332 if (p32x_bios_s != NULL) {
1333 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1334 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1337 pl = (u32 *)Pico32xMem->sh2_rom_s;
1339 // fill exception vector table to our trap address
1340 for (i = 0; i < 128; i++)
1341 pl[i] = HWSWAP(0x200);
1344 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1347 pl[1] = pl[3] = HWSWAP(0x603f800);
1349 pl[0] = pl[2] = HWSWAP(0x204);
1353 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1354 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1356 static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
1357 // for writes we are using handlers only
1358 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1360 void Pico32xSwapDRAM(int b)
1362 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1363 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1364 cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1365 cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1366 cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff,
1367 b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
1368 cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
1369 b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
1372 sh2_read8_map[2].addr = sh2_read8_map[6].addr =
1373 sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1375 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1376 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1379 void PicoMemSetup32x(void)
1384 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1385 if (Pico32xMem == NULL) {
1386 elprintf(EL_STATUS, "OOM");
1392 // cartridge area becomes unmapped
1393 // XXX: we take the easy way and don't unmap ROM,
1394 // so that we can avoid handling the RV bit.
1395 // m68k_map_unmap(0x000000, 0x3fffff);
1398 rs = sizeof(Pico32xMem->m68k_rom_bank);
1399 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1400 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1401 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1402 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1404 // 32X ROM (unbanked, XXX: consider mirroring?)
1405 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1408 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1409 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1411 // setup FAME fetchmap
1412 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1413 for (rs = 0x88; rs < 0x90; rs++)
1414 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1421 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1422 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1423 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1424 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1426 // SH2 maps: A31,A30,A29,CS1,CS0
1427 // all unmapped by default
1428 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1429 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1430 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1433 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1434 sh2_write8_map[i] = sh2_write8_unmapped;
1435 sh2_write16_map[i] = sh2_write16_unmapped;
1439 for (i = 0x40; i <= 0x5f; i++) {
1440 sh2_write8_map[i >> 1] =
1441 sh2_write16_map[i >> 1] = sh2_write_ignore;
1445 sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
1446 sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
1447 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1448 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1450 sh2_read8_map[1].addr = sh2_read8_map[5].addr =
1451 sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
1452 sh2_read8_map[1].mask = sh2_read8_map[5].mask =
1453 sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME
1454 // CS2 - DRAM - done by Pico32xSwapDRAM()
1455 sh2_read8_map[2].mask = sh2_read8_map[6].mask =
1456 sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff;
1458 sh2_read8_map[3].addr = sh2_read8_map[7].addr =
1459 sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
1460 sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
1461 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1462 sh2_read8_map[3].mask = sh2_read8_map[7].mask =
1463 sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
1465 sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
1466 sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
1467 sh2_write8_map[0xc0/2] = sh2_write8_da;
1468 sh2_write16_map[0xc0/2] = sh2_write16_da;
1470 sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
1471 sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
1472 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1473 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1475 // map DRAM area, both 68k and SH2
1478 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1479 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1480 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1481 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1483 sh2_drc_mem_setup(&msh2);
1484 sh2_drc_mem_setup(&ssh2);
1487 void Pico32xMemStateLoaded(void)
1489 bank_switch(Pico32x.regs[4 / 2]);
1490 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1491 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1492 Pico32x.dirty_pal = 1;
1494 Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
1495 memset(&m68k_poll, 0, sizeof(m68k_poll));
1497 msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
1499 ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
1501 sh2_drc_flush_all();
1504 // vim:shiftwidth=2:ts=2:expandtab