3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
10 * a15102 ........ ......SM ? 4002 // intS intM
11 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
12 * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
13 * a15108 (32bit DREQ src) 4008
14 * a1510c (32bit DREQ dst) 400c
15 * a15110 llllllll llllll00 4010 // DREQ Len
16 * a15112 (16bit FIFO reg) 4012
17 * a15114 ? (16bit VRES clr) 4014
18 * a15116 ? (16bit Vint clr) 4016
19 * a15118 ? (16bit Hint clr) 4018
20 * a1511a ........ .......C (16bit CMD clr) 401a // Cm
21 * a1511c ? (16bit PWM clr) 401c
23 * a15120 (16 bytes comm) 2020
27 * iii. .cc. ..xx * // Internal, Cs, x
29 * sh2 map, wait/bus cycles (from docs):
31 * rom 0000000-0003fff 1 -
32 * sys reg 0004000-00040ff 1 1
33 * vdp reg 0004100-00041ff 5 5
34 * vdp pal 0004200-00043ff 5 5
35 * rom 2000000-23fffff 6-15
36 * dram/fb 4000000-401ffff 5-12 1-3
37 * fb ovr 4020000-403ffff
38 * sdram 6000000-603ffff 12 2 (cycles)
41 #include "../pico_int.h"
42 #include "../memory.h"
44 #include "../../cpu/sh2/compiler.h"
50 #define ash2_end_run(x)
54 static const char str_mars[] = "MARS";
56 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
57 struct Pico32xMem *Pico32xMem;
59 static void bank_switch(int b);
62 #define POLL_THRESHOLD 6
65 u32 addr, cycles, cyc_max;
68 static struct poll_det m68k_poll, sh2_poll[2];
70 static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
72 int ret = 0, flag = pd->flag;
77 if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
79 if (pd->cnt > POLL_THRESHOLD) {
80 if (!(Pico32x.emu_flags & flag)) {
81 elprintf(EL_32X, "%s poll addr %08x, cyc %u",
82 flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
83 (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
86 Pico32x.emu_flags |= flag;
98 static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
100 int ret = 0, flag = pd->flag;
102 flag <<= 3; // VDP only
104 flag |= flag << 3; // both
105 if (Pico32x.emu_flags & flag) {
106 elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
109 Pico32x.emu_flags &= ~flag;
110 pd->addr = pd->cnt = 0;
114 void p32x_poll_event(int cpu_mask, int is_vdp)
117 p32x_poll_undetect(&sh2_poll[0], is_vdp);
119 p32x_poll_undetect(&sh2_poll[1], is_vdp);
126 static const u16 comm_fakevals[] = {
127 0x4d5f, 0x4f4b, // M_OK
128 0x535f, 0x4f4b, // S_OK
129 0x4D41, 0x5346, // MASF - Brutal Unleashed
130 0x5331, 0x4d31, // Darxide
133 0x0000, 0x0000, // eq for doom
134 0x0002, // Mortal Kombat
138 static u32 sh2_comm_faker(u32 a)
141 if (a == 0x28 && !p32x_csum_faked) {
143 return *(unsigned short *)(Pico.rom + 0x18e);
145 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
147 return comm_fakevals[f++];
153 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
154 unsigned int chcr0; // chan ctl
155 unsigned int sar1, dar1, tcr1; // same for chan 1
161 static void dma_68k2sh2_do(void)
163 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
166 if (dmac0->tcr0 != *dreqlen)
167 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
169 // HACK: assume bus is busy and SH2 is halted
170 // XXX: use different mechanism for this, not poll det
171 Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
173 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
174 elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
175 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], &msh2);
181 Pico32x.dmac_ptr = 0; // HACK
182 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
184 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
185 if (dmac0->tcr0 == 0) {
186 dmac0->chcr0 |= 2; // DMA has ended normally
187 p32x_poll_undetect(&sh2_poll[0], 0);
191 // ------------------------------------------------------------------
194 static u32 p32x_reg_read16(u32 a)
199 if ((a & 0x30) == 0x20)
200 return sh2_comm_faker(a);
202 if ((a & 0x30) == 0x20) {
204 unsigned int cycles = SekCyclesDoneT();
205 int comreg = 1 << (a & 0x0f) / 2;
207 // evil X-Men proto polls in a dbra loop and expects it to expire..
208 if (SekDar(2) != dr2)
212 if (cycles - msh2.m68krcycles_done > 500)
213 p32x_sync_sh2s(cycles);
214 if (Pico32x.comm_dirty_sh2 & comreg)
215 Pico32x.comm_dirty_sh2 &= ~comreg;
216 else if (p32x_poll_detect(&m68k_poll, a, cycles, 0)) {
225 if (a == 2) { // INTM, INTS
226 unsigned int cycles = SekCyclesDoneT();
227 if (cycles - msh2.m68krcycles_done > 64)
228 p32x_sync_sh2s(cycles);
229 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
232 if ((a & 0x30) == 0x30)
233 return p32x_pwm_read16(a);
236 return Pico32x.regs[a / 2];
239 static void p32x_reg_write8(u32 a, u32 d)
241 u16 *r = Pico32x.regs;
244 // for things like bset on comm port
248 case 0: // adapter ctl
249 r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
251 case 1: // adapter ctl, RES bit writeable
252 if ((d ^ r[0]) & d & P32XS_nRES)
254 r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
257 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
258 p32x_sync_sh2s(SekCyclesDoneT());
259 Pico32x.sh2irqi[0] |= P32XI_CMD;
262 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
263 p32x_sync_sh2s(SekCyclesDoneT());
264 Pico32x.sh2irqi[1] |= P32XI_CMD;
276 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
283 if ((a & 0x30) == 0x20) {
285 int cycles = SekCyclesDoneT();
291 comreg = 1 << (a & 0x0f) / 2;
292 if (Pico32x.comm_dirty_68k & comreg)
293 p32x_sync_sh2s(cycles);
296 p32x_poll_undetect(&sh2_poll[0], 0);
297 p32x_poll_undetect(&sh2_poll[1], 0);
298 Pico32x.comm_dirty_68k |= comreg;
300 if (cycles - (int)msh2.m68krcycles_done > 120)
301 p32x_sync_sh2s(cycles);
306 static void p32x_reg_write16(u32 a, u32 d)
308 u16 *r = Pico32x.regs;
311 // for things like bset on comm port
315 case 0x00: // adapter ctl
316 if ((d ^ r[0]) & d & P32XS_nRES)
318 r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
320 case 0x10: // DREQ len
323 case 0x12: // FIFO reg
324 if (!(r[6 / 2] & P32XS_68S)) {
325 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
328 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
329 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
330 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
332 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
333 r[6 / 2] |= P32XS_FULL;
339 if ((a & 0x38) == 0x08) {
344 else if ((a & 0x30) == 0x20) {
345 int cycles = SekCyclesDoneT();
351 comreg = 1 << (a & 0x0f) / 2;
352 if (Pico32x.comm_dirty_68k & comreg)
353 p32x_sync_sh2s(cycles);
356 p32x_poll_undetect(&sh2_poll[0], 0);
357 p32x_poll_undetect(&sh2_poll[1], 0);
358 Pico32x.comm_dirty_68k |= comreg;
360 if (cycles - (int)msh2.m68krcycles_done > 120)
361 p32x_sync_sh2s(cycles);
365 else if ((a & 0x30) == 0x30) {
366 p32x_pwm_write16(a, d);
370 p32x_reg_write8(a + 1, d);
373 // ------------------------------------------------------------------
375 static u32 p32x_vdp_read16(u32 a)
379 return Pico32x.vdp_regs[a / 2];
382 static void p32x_vdp_write8(u32 a, u32 d)
384 u16 *r = Pico32x.vdp_regs;
387 // for FEN checks between writes
390 // TODO: verify what's writeable
393 // priority inversion is handled in palette
394 if ((r[0] ^ d) & P32XV_PRI)
395 Pico32x.dirty_pal = 1;
396 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
398 case 0x03: // shift (for pp mode)
401 case 0x05: // fill len
406 Pico32x.pending_fb = d;
407 // if we are blanking and FS bit is changing
408 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
409 r[0x0a/2] ^= P32XV_FS;
410 Pico32xSwapDRAM(d ^ 1);
411 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
417 static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
420 if (a == 6) { // fill start
421 Pico32x.vdp_regs[6 / 2] = d;
424 if (a == 8) { // fill data
425 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
426 int len = Pico32x.vdp_regs[4 / 2] + 1;
428 a = Pico32x.vdp_regs[6 / 2];
431 a = (a & 0xff00) | ((a + 1) & 0xff);
433 Pico32x.vdp_regs[0x06 / 2] = a;
434 Pico32x.vdp_regs[0x08 / 2] = d;
436 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
437 p32x_event_schedule(P32X_EVENT_FILLEND, cycles, len);
442 p32x_vdp_write8(a | 1, d);
445 // ------------------------------------------------------------------
448 static u32 p32x_sh2reg_read16(u32 a, int cpuid)
450 u16 *r = Pico32x.regs;
454 case 0x00: // adapter/irq ctl
455 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
456 case 0x04: // H count (often as comm too)
457 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
458 ash2_end_run(&sh2s[cpuid], 8);
459 return Pico32x.sh2_regs[4 / 2];
460 case 0x10: // DREQ len
465 if ((a & 0x38) == 0x08)
468 if ((a & 0x30) == 0x20) {
469 int comreg = 1 << (a & 0x0f) / 2;
470 if (Pico32x.comm_dirty_68k & comreg)
471 Pico32x.comm_dirty_68k &= ~comreg;
472 else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
473 ash2_end_run(&sh2s[cpuid], 8);
476 if ((a & 0x30) == 0x30) {
477 sh2_poll[cpuid].cnt = 0;
478 return p32x_pwm_read16(a);
484 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
489 Pico32x.regs[0] &= ~P32XS_FM;
490 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
493 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
494 Pico32x.sh2_regs[0] &= ~0x80;
495 Pico32x.sh2_regs[0] |= d & 0x80;
497 p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // XXX: timing?
501 Pico32x.sh2_regs[4 / 2] = d & 0xff;
502 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
506 if ((a & 0x30) == 0x20) {
507 u8 *r8 = (u8 *)Pico32x.regs;
513 if (p32x_poll_undetect(&m68k_poll, 0))
515 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
516 comreg = 1 << (a & 0x0f) / 2;
517 Pico32x.comm_dirty_sh2 |= comreg;
522 static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
527 if ((a & 0x30) == 0x20) {
529 if (Pico32x.regs[a / 2] == d)
532 Pico32x.regs[a / 2] = d;
533 if (p32x_poll_undetect(&m68k_poll, 0))
535 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
536 comreg = 1 << (a & 0x0f) / 2;
537 Pico32x.comm_dirty_sh2 |= comreg;
541 else if ((a & 0x30) == 0x30) {
542 p32x_pwm_write16(a, d);
548 Pico32x.regs[0] &= ~P32XS_FM;
549 Pico32x.regs[0] |= d & P32XS_FM;
551 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
552 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
553 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
554 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
556 Pico32x.sh2irqs &= ~P32XI_PWM;
557 if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
558 p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // timing?
562 p32x_sh2reg_write8(a | 1, d, cpuid);
569 // ------------------------------------------------------------------
570 // SH2 internal peripherals
571 // we keep them in little endian format
572 static u32 sh2_peripheral_read8(u32 a, int id)
574 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
580 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
584 static u32 sh2_peripheral_read16(u32 a, int id)
586 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
592 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
596 static u32 sh2_peripheral_read32(u32 a, int id)
600 d = Pico32xMem->sh2_peri_regs[id][a / 4];
602 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
606 static int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
608 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
609 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
615 if ((a == 2 && (d & 0x20)) || // transmiter enabled
616 (a == 4 && !(d & 0x80))) { // valid data in TDR
617 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
618 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
619 int level = PREG8(oregs, 0x60) >> 4;
620 int vector = PREG8(oregs, 0x63) & 0x7f;
621 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
622 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
629 static int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
631 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
632 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
638 if ((d & 0xff00) == 0xa500) { // WTCSR
640 p32x_timers_recalc();
642 if ((d & 0xff00) == 0x5a00) // WTCNT
651 static void sh2_peripheral_write32(u32 a, u32 d, int id)
653 u32 *r = Pico32xMem->sh2_peri_regs[id];
654 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
660 // division unit (TODO: verify):
661 case 0x104: // DVDNT: divident L, starts divide
662 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
664 signed int divisor = r[0x100 / 4];
665 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
666 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
669 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
672 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
673 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
675 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
676 signed int divisor = r[0x100 / 4];
677 // XXX: undocumented mirroring to 0x118,0x11c?
678 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
680 r[0x11c / 4] = r[0x114 / 4] = divident;
682 if ((unsigned long long)divident + 1 > 1) {
683 //elprintf(EL_32X, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
684 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
688 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
692 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
693 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
694 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
695 dmac0->tcr0 &= 0xffffff;
697 // HACK: assume 68k starts writing soon and end the timeslice
698 ash2_end_run(&sh2s[id], 16);
700 // DREQ is only sent after first 4 words are written.
701 // we do multiple of 4 words to avoid messing up alignment
702 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
703 elprintf(EL_32X, "68k -> sh2 DMA");
709 // ------------------------------------------------------------------
713 static u32 PicoRead8_32x_on(u32 a)
716 if ((a & 0xffc0) == 0x5100) { // a15100
717 d = p32x_reg_read16(a);
721 if ((a & 0xfc00) != 0x5000)
722 return PicoRead8_io(a);
724 if ((a & 0xfff0) == 0x5180) { // a15180
725 d = p32x_vdp_read16(a);
729 if ((a & 0xfe00) == 0x5200) { // a15200
730 d = Pico32xMem->pal[(a & 0x1ff) / 2];
734 if ((a & 0xfffc) == 0x30ec) { // a130ec
739 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
749 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
753 static u32 PicoRead16_32x_on(u32 a)
756 if ((a & 0xffc0) == 0x5100) { // a15100
757 d = p32x_reg_read16(a);
761 if ((a & 0xfc00) != 0x5000)
762 return PicoRead16_io(a);
764 if ((a & 0xfff0) == 0x5180) { // a15180
765 d = p32x_vdp_read16(a);
769 if ((a & 0xfe00) == 0x5200) { // a15200
770 d = Pico32xMem->pal[(a & 0x1ff) / 2];
774 if ((a & 0xfffc) == 0x30ec) { // a130ec
775 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
779 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
783 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
787 static void PicoWrite8_32x_on(u32 a, u32 d)
789 if ((a & 0xfc00) == 0x5000)
790 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
792 if ((a & 0xffc0) == 0x5100) { // a15100
793 p32x_reg_write8(a, d);
797 if ((a & 0xfc00) != 0x5000) {
802 if ((a & 0xfff0) == 0x5180) { // a15180
803 p32x_vdp_write8(a, d);
808 if ((a & 0xfe00) == 0x5200) { // a15200
809 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
810 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
811 Pico32x.dirty_pal = 1;
815 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
818 static void PicoWrite16_32x_on(u32 a, u32 d)
820 if ((a & 0xfc00) == 0x5000)
821 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
823 if ((a & 0xffc0) == 0x5100) { // a15100
824 p32x_reg_write16(a, d);
828 if ((a & 0xfc00) != 0x5000) {
829 PicoWrite16_io(a, d);
833 if ((a & 0xfff0) == 0x5180) { // a15180
834 p32x_vdp_write16(a, d, 0); // FIXME?
838 if ((a & 0xfe00) == 0x5200) { // a15200
839 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
840 Pico32x.dirty_pal = 1;
844 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
848 u32 PicoRead8_32x(u32 a)
851 if ((a & 0xffc0) == 0x5100) { // a15100
852 // regs are always readable
853 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
857 if ((a & 0xfffc) == 0x30ec) { // a130ec
862 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
866 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
870 u32 PicoRead16_32x(u32 a)
873 if ((a & 0xffc0) == 0x5100) { // a15100
874 d = Pico32x.regs[(a & 0x3f) / 2];
878 if ((a & 0xfffc) == 0x30ec) { // a130ec
879 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
883 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
887 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
891 void PicoWrite8_32x(u32 a, u32 d)
893 if ((a & 0xffc0) == 0x5100) { // a15100
894 u16 *r = Pico32x.regs;
896 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
899 if ((d ^ r[0]) & d & P32XS_ADEN) {
901 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
903 p32x_reg_write8(a, d); // forward for reset processing
908 // allow only COMM for now
909 if ((a & 0x30) == 0x20) {
916 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
919 void PicoWrite16_32x(u32 a, u32 d)
921 if ((a & 0xffc0) == 0x5100) { // a15100
922 u16 *r = Pico32x.regs;
924 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
927 if ((d ^ r[0]) & d & P32XS_ADEN) {
929 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
931 p32x_reg_write16(a, d); // forward for reset processing
936 // allow only COMM for now
937 if ((a & 0x30) == 0x20)
942 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
945 // -----------------------------------------------------------------
947 // hint vector is writeable
948 static void PicoWrite8_hint(u32 a, u32 d)
950 if ((a & 0xfffc) == 0x0070) {
951 Pico32xMem->m68k_rom[a ^ 1] = d;
955 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
958 static void PicoWrite16_hint(u32 a, u32 d)
960 if ((a & 0xfffc) == 0x0070) {
961 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
965 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
968 static void bank_switch(int b)
970 unsigned int rs, bank;
973 if (bank >= Pico.romsize) {
974 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
978 // 32X ROM (unbanked, XXX: consider mirroring?)
979 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
983 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
984 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
986 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
989 // setup FAME fetchmap
990 for (rs = 0x90; rs < 0xa0; rs++)
991 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
995 // -----------------------------------------------------------------
997 // -----------------------------------------------------------------
1000 static u32 sh2_read8_unmapped(u32 a, int id)
1002 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
1003 id ? 's' : 'm', a, 0, sh2_pc(id));
1007 static u32 sh2_read8_cs0(u32 a, int id)
1011 // 0x3ff00 is veridied
1012 if ((a & 0x3ff00) == 0x4000) {
1013 d = p32x_sh2reg_read16(a, id);
1017 if ((a & 0x3ff00) == 0x4100) {
1018 d = p32x_vdp_read16(a);
1019 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
1020 ash2_end_run(&sh2s[id], 8);
1025 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
1026 return Pico32xMem->sh2_rom_m[a ^ 1];
1027 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
1028 return Pico32xMem->sh2_rom_s[a ^ 1];
1030 if ((a & 0x3fe00) == 0x4200) {
1031 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1035 return sh2_read8_unmapped(a, id);
1043 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
1044 id ? 's' : 'm', a, d, sh2_pc(id));
1048 static u32 sh2_read8_da(u32 a, int id)
1050 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
1054 static u32 sh2_read16_unmapped(u32 a, int id)
1056 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
1057 id ? 's' : 'm', a, 0, sh2_pc(id));
1061 static u32 sh2_read16_cs0(u32 a, int id)
1065 if ((a & 0x3ff00) == 0x4000) {
1066 d = p32x_sh2reg_read16(a, id);
1067 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1072 if ((a & 0x3ff00) == 0x4100) {
1073 d = p32x_vdp_read16(a);
1074 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
1075 ash2_end_run(&sh2s[id], 8);
1079 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
1080 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
1081 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
1082 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
1084 if ((a & 0x3fe00) == 0x4200) {
1085 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1089 return sh2_read16_unmapped(a, id);
1092 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
1093 id ? 's' : 'm', a, d, sh2_pc(id));
1097 static u32 sh2_read16_da(u32 a, int id)
1099 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
1102 static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
1108 static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
1110 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
1111 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1115 static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
1117 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
1118 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1120 if ((a & 0x3ff00) == 0x4100) {
1121 p32x_vdp_write8(a, d);
1125 if ((a & 0x3ff00) == 0x4000) {
1126 p32x_sh2reg_write8(a, d, id);
1130 return sh2_write8_unmapped(a, d, id);
1133 /* quirk: in both normal and overwrite areas only nonzero values go through */
1134 #define sh2_write8_dramN(n) \
1135 if ((d & 0xff) != 0) { \
1136 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1137 dram[(a & 0x1ffff) ^ 1] = d; \
1141 static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
1143 sh2_write8_dramN(0);
1146 static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
1148 sh2_write8_dramN(1);
1151 static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
1153 u32 a1 = a & 0x3ffff;
1155 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1157 sh2_drc_wcheck_ram(a, t, id);
1159 Pico32xMem->sdram[a1 ^ 1] = d;
1163 static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
1167 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1169 sh2_drc_wcheck_da(a, t, id);
1171 Pico32xMem->data_array[id][a1 ^ 1] = d;
1176 static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
1178 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1179 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1183 static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
1185 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1186 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
1187 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1189 if ((a & 0x3ff00) == 0x4100) {
1190 sh2_poll[id].cnt = 0; // for poll before VDP accesses
1191 p32x_vdp_write16(a, d, sh2s[id].m68krcycles_done);
1195 if ((a & 0x3fe00) == 0x4200) {
1196 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1197 Pico32x.dirty_pal = 1;
1201 if ((a & 0x3ff00) == 0x4000) {
1202 p32x_sh2reg_write16(a, d, id);
1206 return sh2_write16_unmapped(a, d, id);
1209 #define sh2_write16_dramN(n) \
1210 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1211 if (!(a & 0x20000)) { \
1216 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1217 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1221 static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
1223 sh2_write16_dramN(0);
1226 static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
1228 sh2_write16_dramN(1);
1231 static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
1233 u32 a1 = a & 0x3ffff;
1235 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1237 sh2_drc_wcheck_ram(a, t, id);
1239 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1243 static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
1247 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1249 sh2_drc_wcheck_da(a, t, id);
1251 ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
1257 uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
1261 typedef u32 (sh2_read_handler)(u32 a, int id);
1262 typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
1264 #define SH2MAP_ADDR2OFFS_R(a) \
1265 ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
1267 #define SH2MAP_ADDR2OFFS_W(a) \
1268 ((u32)(a) >> SH2_WRITE_SHIFT)
1270 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1272 const sh2_memmap *sh2_map = sh2->read8_map;
1275 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1277 if (map_flag_set(p))
1278 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1280 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1283 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1285 const sh2_memmap *sh2_map = sh2->read16_map;
1288 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1290 if (map_flag_set(p))
1291 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1293 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1296 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1298 const sh2_memmap *sh2_map = sh2->read16_map;
1299 sh2_read_handler *handler;
1303 offs = SH2MAP_ADDR2OFFS_R(a);
1306 if (!map_flag_set(p)) {
1307 // XXX: maybe 32bit access instead with ror?
1308 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1309 return (pd[0] << 16) | pd[1];
1313 return sh2_peripheral_read32(a, sh2->is_slave);
1315 handler = (sh2_read_handler *)(p << 1);
1316 return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
1319 // return nonzero if write potentially causes an interrupt (used by drc)
1320 int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1322 const void **sh2_wmap = sh2->write8_tab;
1323 sh2_write_handler *wh;
1325 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1326 return wh(a, d, sh2->is_slave);
1329 int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1331 const void **sh2_wmap = sh2->write16_tab;
1332 sh2_write_handler *wh;
1334 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1335 return wh(a, d, sh2->is_slave);
1338 int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1340 const void **sh2_wmap = sh2->write16_tab;
1341 sh2_write_handler *handler;
1344 offs = SH2MAP_ADDR2OFFS_W(a);
1346 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1347 sh2_peripheral_write32(a, d, sh2->is_slave);
1351 handler = sh2_wmap[offs];
1352 handler(a, d >> 16, sh2->is_slave);
1353 handler(a + 2, d, sh2->is_slave);
1357 // -----------------------------------------------------------------
1359 static const u16 msh2_code[] = {
1360 // trap instructions
1361 0xaffe, // bra <self>
1363 // have to wait a bit until m68k initial program finishes clearing stuff
1364 // to avoid races with game SH2 code, like in Tempo
1365 0xd004, // mov.l @(_m_ok,pc), r0
1366 0xd105, // mov.l @(_cnt,pc), r1
1367 0xd205, // mov.l @(_start,pc), r2
1368 0x71ff, // add #-1, r1
1369 0x4115, // cmp/pl r1
1371 0xc208, // mov.l r0, @(h'20,gbr)
1372 0x6822, // mov.l @r2, r8
1375 ('M'<<8)|'_', ('O'<<8)|'K',
1377 0x2200, 0x03e0 // master start pointer in ROM
1380 static const u16 ssh2_code[] = {
1381 0xaffe, // bra <self>
1383 // code to wait for master, in case authentic master BIOS is used
1384 0xd104, // mov.l @(_m_ok,pc), r1
1385 0xd206, // mov.l @(_start,pc), r2
1386 0xc608, // mov.l @(h'20,gbr), r0
1387 0x3100, // cmp/eq r0, r1
1389 0xd003, // mov.l @(_s_ok,pc), r0
1390 0xc209, // mov.l r0, @(h'24,gbr)
1391 0x6822, // mov.l @r2, r8
1394 ('M'<<8)|'_', ('O'<<8)|'K',
1395 ('S'<<8)|'_', ('O'<<8)|'K',
1396 0x2200, 0x03e4 // slave start pointer in ROM
1399 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
1400 static void get_bios(void)
1407 if (p32x_bios_g != NULL) {
1408 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1409 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1413 ps = (u16 *)Pico32xMem->m68k_rom;
1415 for (i = 1; i < 0xc0/4; i++)
1416 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1419 for (i = 0xc0/2; i < 0x100/2; i++)
1423 ps[0xc0/2] = 0x46fc;
1424 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1425 ps[0xfe/2] = 0x60fe; // jump to self
1427 ps[0xfe/2] = 0x4e75; // rts
1430 // fill remaining m68k_rom page with game ROM
1431 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1432 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1433 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1436 if (p32x_bios_m != NULL) {
1437 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1438 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1441 pl = (u32 *)Pico32xMem->sh2_rom_m;
1443 // fill exception vector table to our trap address
1444 for (i = 0; i < 128; i++)
1445 pl[i] = HWSWAP(0x200);
1448 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1451 pl[1] = pl[3] = HWSWAP(0x6040000);
1453 pl[0] = pl[2] = HWSWAP(0x204);
1457 if (p32x_bios_s != NULL) {
1458 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1459 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1462 pl = (u32 *)Pico32xMem->sh2_rom_s;
1464 // fill exception vector table to our trap address
1465 for (i = 0; i < 128; i++)
1466 pl[i] = HWSWAP(0x200);
1469 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1472 pl[1] = pl[3] = HWSWAP(0x603f800);
1474 pl[0] = pl[2] = HWSWAP(0x204);
1478 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1479 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1481 static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
1482 // for writes we are using handlers only
1483 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1485 void Pico32xSwapDRAM(int b)
1487 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1488 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1489 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1490 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1493 sh2_read8_map[2].addr = sh2_read8_map[6].addr =
1494 sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1496 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1497 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1500 void PicoMemSetup32x(void)
1505 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1506 if (Pico32xMem == NULL) {
1507 elprintf(EL_STATUS, "OOM");
1511 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
1515 // cartridge area becomes unmapped
1516 // XXX: we take the easy way and don't unmap ROM,
1517 // so that we can avoid handling the RV bit.
1518 // m68k_map_unmap(0x000000, 0x3fffff);
1521 rs = sizeof(Pico32xMem->m68k_rom_bank);
1522 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1523 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1524 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1525 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1527 // 32X ROM (unbanked, XXX: consider mirroring?)
1528 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1531 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1532 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1534 // setup FAME fetchmap
1535 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1536 for (rs = 0x88; rs < 0x90; rs++)
1537 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1544 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1545 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1546 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1547 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1549 // SH2 maps: A31,A30,A29,CS1,CS0
1550 // all unmapped by default
1551 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1552 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1553 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1556 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1557 sh2_write8_map[i] = sh2_write8_unmapped;
1558 sh2_write16_map[i] = sh2_write16_unmapped;
1562 for (i = 0x40; i <= 0x5f; i++) {
1563 sh2_write8_map[i >> 1] =
1564 sh2_write16_map[i >> 1] = sh2_write_ignore;
1568 sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
1569 sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
1570 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1571 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1573 sh2_read8_map[1].addr = sh2_read8_map[5].addr =
1574 sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
1575 sh2_read8_map[1].mask = sh2_read8_map[5].mask =
1576 sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME
1577 // CS2 - DRAM - done by Pico32xSwapDRAM()
1578 sh2_read8_map[2].mask = sh2_read8_map[6].mask =
1579 sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff;
1581 sh2_read8_map[3].addr = sh2_read8_map[7].addr =
1582 sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
1583 sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
1584 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1585 sh2_read8_map[3].mask = sh2_read8_map[7].mask =
1586 sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
1588 sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
1589 sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
1590 sh2_write8_map[0xc0/2] = sh2_write8_da;
1591 sh2_write16_map[0xc0/2] = sh2_write16_da;
1593 sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
1594 sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
1595 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1596 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1598 // map DRAM area, both 68k and SH2
1601 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1602 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1603 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1604 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1606 // setup poll detector
1607 m68k_poll.flag = P32XF_68KPOLL;
1608 m68k_poll.cyc_max = 64;
1609 sh2_poll[0].flag = P32XF_MSH2POLL;
1610 sh2_poll[0].cyc_max = 21;
1611 sh2_poll[1].flag = P32XF_SSH2POLL;
1612 sh2_poll[1].cyc_max = 16;
1615 sh2_drc_mem_setup(&msh2);
1616 sh2_drc_mem_setup(&ssh2);
1620 void Pico32xStateLoaded(void)
1622 sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
1623 p32x_poll_event(3, 0);
1625 bank_switch(Pico32x.regs[4 / 2]);
1626 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1627 Pico32x.dirty_pal = 1;
1628 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1629 p32x_timers_recalc();
1631 sh2_drc_flush_all();
1635 // vim:shiftwidth=2:ts=2:expandtab