2 * SH2 peripherals/"system on chip"
4 * (C) irixxxx, 2019-2024
6 * This work is licensed under the terms of MAME license.
7 * See COPYING file in the top-level directory.
9 * rough fffffe00-ffffffff map:
10 * e00-e05 SCI serial communication interface
11 * e10-e1a FRT free-running timer
12 * e60-e68 VCRx irq vectors
13 * e71-e72 DRCR dma selection
14 * e80-e83 WDT watchdog timer
15 * e91 SBYCR standby control
16 * e92 CCR cache control
18 * ee2 IPRA irq priorities
19 * ee4 VCRWDT WDT irq vectors
21 * f40-f7b UBC user break controller
23 * fe0-ffb BSC bus state controller
26 #include "../pico_int.h"
27 #include "../memory.h"
29 #include <cpu/sh2/compiler.h>
34 u32 sar, dar; // src, dst addr
35 u32 tcr; // transfer count
37 // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de
38 // ts - transfer size: 1, 2, 4, 16 bytes
39 // ar - auto request if 1, else dreq signal
43 #define DMA_AR (1 << 9)
44 #define DMA_IE (1 << 2)
45 #define DMA_TE (1 << 1)
46 #define DMA_DE (1 << 0)
50 struct dma_chan chan[2];
57 // pr - priority: chan0 > chan1 or round-robin
59 // nmif - nmi occurred
60 // dme - DMA master enable
61 #define DMA_DME (1 << 0)
64 static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
66 char *regs = (void *)sh2->peri_regs;
67 struct dmac *dmac = (void *)(regs + 0x180);
68 int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
69 int vector = (chan == &dmac->chan[0]) ?
70 dmac->vcrdma0 : dmac->vcrdma1;
72 elprintf(EL_32XP, "dmac irq %d %d", level, vector);
73 sh2_internal_irq(sh2, level, vector & 0x7f);
76 static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
78 chan->chcr |= DMA_TE; // DMA has ended normally
80 p32x_sh2_poll_event(sh2->poll_addr, sh2, SH2_STATE_SLEEP, SekCyclesDone());
81 if (chan->chcr & DMA_IE)
82 dmac_te_irq(sh2, chan);
85 static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
89 size = (chan->chcr >> 10) & 3;
92 d = p32x_sh2_read8(chan->sar, sh2);
93 p32x_sh2_write8(chan->dar, d, sh2);
96 d = p32x_sh2_read16(chan->sar, sh2);
97 p32x_sh2_write16(chan->dar, d, sh2);
100 d = p32x_sh2_read32(chan->sar, sh2);
101 p32x_sh2_write32(chan->dar, d, sh2);
104 d = p32x_sh2_read32(chan->sar + 0x00, sh2);
105 p32x_sh2_write32(chan->dar + 0x00, d, sh2);
106 d = p32x_sh2_read32(chan->sar + 0x04, sh2);
107 p32x_sh2_write32(chan->dar + 0x04, d, sh2);
108 d = p32x_sh2_read32(chan->sar + 0x08, sh2);
109 p32x_sh2_write32(chan->dar + 0x08, d, sh2);
110 d = p32x_sh2_read32(chan->sar + 0x0c, sh2);
111 p32x_sh2_write32(chan->dar + 0x0c, d, sh2);
112 chan->sar += 16; // always?
113 if (chan->chcr & (1 << 15))
115 if (chan->chcr & (1 << 14))
123 if (chan->chcr & (1 << 15))
125 if (chan->chcr & (1 << 14))
127 if (chan->chcr & (1 << 13))
129 if (chan->chcr & (1 << 12))
133 // optimization for copying around memory with SH2 DMA
134 static void dmac_memcpy(struct dma_chan *chan, SH2 *sh2)
136 u32 size = (chan->chcr >> 10) & 3, up = chan->chcr & (1 << 14);
139 if (!up || chan->tcr < 4)
142 if (size == 3) size = 2; // 4-word xfer mode still counts in words
143 // XXX check TCR being a multiple of 4 in 4-word xfer mode?
144 // XXX check alignment of sar/dar, generating a bus error if unaligned?
145 count = p32x_sh2_memcpy(chan->dar, chan->sar, chan->tcr, 1 << size, sh2);
147 chan->sar += count << size;
148 chan->dar += count << size;
152 // DMA trigger by SH2 register write
153 static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
155 elprintf_sh2(sh2, EL_32XP, "DMA %08x->%08x, cnt %d, chcr %04x @%06x",
156 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
157 chan->tcr &= 0xffffff;
159 if (chan->chcr & DMA_AR) {
160 // auto-request transfer
161 sh2->state |= SH2_STATE_SLEEP;
162 if ((((chan->chcr >> 12) ^ (chan->chcr >> 14)) & 3) == 0 &&
163 (((chan->chcr >> 14) ^ (chan->chcr >> 15)) & 1) == 1) {
164 // SM == DM and either DM0 or DM1 are set. check for mem to mem copy
165 dmac_memcpy(chan, sh2);
167 while ((int)chan->tcr > 0)
168 dmac_transfer_one(sh2, chan);
169 dmac_transfer_complete(sh2, chan);
173 // DREQ0 is only sent after first 4 words are written.
174 // we do multiple of 4 words to avoid messing up alignment
175 if ((chan->sar & ~0x20000000) == 0x00004012) {
176 if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
177 elprintf(EL_32XP, "68k -> sh2 DMA");
178 p32x_dreq0_trigger();
184 if ((chan->dar & 0xc7fffff0) == 0x00004030)
187 elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
188 "%08x->%08x, cnt %d, chcr %04x @%06x",
189 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
192 // FIXME, timer state, in unused peri_regs space to have it in state save/load
193 #define timer_cycles(sh2) *((u32 *)&(sh2)->peri_regs[0x1c])
194 static u32 timer_tick_shift[2];
197 void p32x_timers_recalc(void)
202 for (i = 0; i < 2; i++) {
203 sh2s[i].state &= ~SH2_TIMER_RUN;
204 if (PREG8(sh2s[i].peri_regs, 0x80) & 0x20) // TME
205 sh2s[i].state |= SH2_TIMER_RUN;
206 tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7;
207 // Sclk cycles per timer tick
211 timer_tick_shift[i] = tmp;
212 elprintf(EL_32XP, "WDT cycles[%d] = %d", i, 1 << tmp);
216 NOINLINE void p32x_timer_do(SH2 *sh2, unsigned int m68k_slice)
218 unsigned int cycles = m68k_slice * 3;
219 void *pregs = sh2->peri_regs;
220 int cnt; int i = sh2->is_slave;
223 timer_cycles(sh2) += cycles;
224 cnt = (timer_cycles(sh2) >> timer_tick_shift[i]);
226 timer_cycles(sh2) -= cnt << timer_tick_shift[i];
228 cnt += PREG8(pregs, 0x81);
230 int level = PREG8(pregs, 0xe3) >> 4;
231 int vector = PREG8(pregs, 0xe4) & 0x7f;
232 PREG8(pregs, 0x80) |= 0x80; // WOVF
233 elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)",
234 i ? 's' : 'm', level, vector);
235 sh2_internal_irq(sh2, level, vector);
238 PREG8(pregs, 0x81) = cnt;
242 void sh2_peripheral_reset(SH2 *sh2)
244 memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
245 PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR
246 PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR
247 PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR
248 PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER
249 PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR
252 // ------------------------------------------------------------------
253 // SH2 internal peripheral memhandlers
254 // we keep them in little endian format
256 u32 REGPARM(2) sh2_peripheral_read8(u32 a, SH2 *sh2)
258 u8 *r = (void *)sh2->peri_regs;
265 elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x",
266 a | ~0x1ff, d, sh2_pc(sh2));
267 if ((a & 0x1c0) == 0x140) {
268 // abused as comm area
269 p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
275 u32 REGPARM(2) sh2_peripheral_read16(u32 a, SH2 *sh2)
277 u16 *r = (void *)sh2->peri_regs;
282 d = r[MEM_BE2(a / 2)];
284 elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
285 a | ~0x1ff, d, sh2_pc(sh2));
286 if ((a & 0x1c0) == 0x140) {
287 // abused as comm area
288 p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
294 u32 REGPARM(2) sh2_peripheral_read32(u32 a, SH2 *sh2)
300 d = sh2->peri_regs[a / 4];
302 elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
303 a | ~0x1ff, d, sh2_pc(sh2));
305 // kludge for polling COMM while polling for end of DMA
307 else if ((a & 0x1c0) == 0x140) {
308 // abused as comm area
309 p32x_sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 3);
315 static void sci_trigger(SH2 *sh2, u8 *r)
319 if (!(PREG8(r, 2) & 0x20))
320 return; // transmitter not enabled
321 if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty
324 oregs = (u8 *)sh2->other_sh2->peri_regs;
325 if (!(PREG8(oregs, 2) & 0x10))
326 return; // receiver not enabled
328 PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR
329 PREG8(r, 4) |= 0x80; // TDRE - TDR empty
330 PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full
332 // might need to delay these a bit..
333 if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled
334 int level = PREG8(oregs, 0x60) >> 4;
335 int vector = PREG8(oregs, 0x64) & 0x7f;
336 elprintf_sh2(sh2, EL_32XP, "SCI tx irq (%d, %d)",
338 sh2_internal_irq(sh2, level, vector);
341 if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled
342 int level = PREG8(oregs, 0x60) >> 4;
343 int vector = PREG8(oregs, 0x63) & 0x7f;
344 elprintf_sh2(sh2->other_sh2, EL_32XP, "SCI rx irq (%d, %d)",
346 sh2_internal_irq(sh2->other_sh2, level, vector);
350 void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
352 u8 *r = (void *)sh2->peri_regs;
356 elprintf_sh2(sh2, EL_32XP, "peri w8 [%08x] %02x @%06x",
364 case 0x002: // SCR - serial control
365 if (!(old & 0x20) && (d & 0x20)) // TE being set
368 case 0x003: // TDR - transmit data
370 case 0x004: // SSR - serial status
371 d = (old & (d | 0x06)) | (d & 1);
375 case 0x005: // RDR - receive data
379 elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
388 if ((a & 0x1c0) == 0x140)
389 p32x_sh2_poll_event(a, sh2, SH2_STATE_CPOLL, SekCyclesDone());
394 void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
396 u16 *r = (void *)sh2->peri_regs;
399 elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
406 if ((d & 0xff00) == 0xa500) { // WTCSR
408 p32x_timers_recalc();
409 timer_cycles(sh2) = 0;
411 if ((d & 0xff00) == 0x5a00) // WTCNT
414 r[MEM_BE2(a / 2)] = d;
415 if ((a & 0x1c0) == 0x140)
416 p32x_sh2_poll_event(a, sh2, SH2_STATE_CPOLL, SekCyclesDone());
421 void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
423 u32 *r = sh2->peri_regs;
428 elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
435 // TODO: DRC doesn't correctly extend 'd' parameter register to 64bit :-/
437 // division unit (TODO: verify):
438 case 0x104: // DVDNT: divident L, starts divide
439 elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x",
440 r[0x104 / 4], r[0x100 / 4]);
442 signed int divisor = r[0x100 / 4];
443 r[0x118 / 4] = r[0x110 / 4] = (signed int)r[0x104 / 4] % divisor;
444 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)r[0x104 / 4] / divisor;
447 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
450 elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x",
451 r[0x110 / 4], r[0x114 / 4], r[0x100 / 4], sh2_pc(sh2));
453 signed long long divident = (signed long long)r[0x110 / 4] << 32 | r[0x114 / 4];
454 signed int divisor = r[0x100 / 4];
455 // XXX: undocumented mirroring to 0x118,0x11c?
456 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
458 r[0x11c / 4] = r[0x114 / 4] = divident;
460 if ((unsigned long long)divident + 1 > 1) {
461 //elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2));
462 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
466 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
468 // perhaps starting a DMA?
472 dmac = (void *)&sh2->peri_regs[0x180 / 4];
473 if (a == 0x1b0 && !((old ^ d) & d & DMA_DME))
475 if (!(dmac->dmaor & DMA_DME))
478 if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
479 dmac_trigger(sh2, &dmac->chan[0]);
480 if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
481 dmac_trigger(sh2, &dmac->chan[1]);
484 if ((a & 0x1c0) == 0x140)
485 p32x_sh2_poll_event(a, sh2, SH2_STATE_CPOLL, SekCyclesDone());
492 static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
494 unsigned short dreqlen = Pico32x.regs[0x10 / 2];
497 // debug/sanity checks
498 if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
499 elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
501 // note: DACK is not connected, single addr mode should not be used
502 if ((chan->chcr & 0x3f08) != 0x0400)
503 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
504 if ((chan->sar & ~0x20000000) != 0x00004012)
505 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar);
507 // HACK: assume bus is busy and SH2 is halted
508 sh2->state |= SH2_STATE_SLEEP;
510 for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
511 elprintf_sh2(sh2, EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
512 chan->dar, Pico32x.dmac_fifo[i], dreqlen);
513 p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
518 if (Pico32x.dmac0_fifo_ptr != i)
519 memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
520 (Pico32x.dmac0_fifo_ptr - i) * 2);
521 Pico32x.dmac0_fifo_ptr -= i;
523 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
525 dmac_transfer_complete(sh2, chan);
527 sh2_end_run(sh2, 16);
530 static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
532 // debug/sanity checks
533 if ((chan->chcr & 0xc308) != 0x0000)
534 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
535 if ((chan->dar & ~0xf) != 0x20004030)
536 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
538 sh2->state |= SH2_STATE_SLEEP;
539 dmac_transfer_one(sh2, chan);
540 sh2->state &= ~SH2_STATE_SLEEP;
542 dmac_transfer_complete(sh2, chan);
545 void p32x_dreq0_trigger(void)
547 struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
548 struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
550 elprintf(EL_32XP, "dreq0_trigger");
551 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
552 dreq0_do(&msh2, &mdmac->chan[0]);
554 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
555 dreq0_do(&ssh2, &sdmac->chan[0]);
559 void p32x_dreq1_trigger(void)
561 struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
562 struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
565 elprintf(EL_32XP, "dreq1_trigger");
566 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
567 dreq1_do(&msh2, &mdmac->chan[1]);
570 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
571 dreq1_do(&ssh2, &sdmac->chan[1]);
576 #if (EL_LOGMASK & (EL_32XP|EL_ANOMALY))
578 static int miss_count;
580 if (++miss_count == 4)
581 elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
590 // vim:shiftwidth=2:ts=2:expandtab