pico/carthw/svp/compiler.c

   1 // SSP1601 to ARM recompiler
   2
   3 // (c) Copyright 2008, Grazvydas "notaz" Ignotas
   4 // Free for non-commercial use.
   5
   6 #include "../../pico_int.h"
   7 #include "../../../cpu/drc/cmn.h"
   8 #include "compiler.h"
   9
  10 // FIXME: asm has these hardcoded
  11 #define SSP_BLOCKTAB_ENTS       (0x5090/2)
  12 #define SSP_BLOCKTAB_IRAM_ONE   (0x800/2) // table entries
  13 #define SSP_BLOCKTAB_IRAM_ENTS  (15*SSP_BLOCKTAB_IRAM_ONE)
  14
  15 static u32 **ssp_block_table; // [0x5090/2];
  16 static u32 **ssp_block_table_iram; // [15][0x800/2];
  17
  18 static u32 *tcache_ptr = NULL;
  19
  20 static int nblocks = 0;
  21 static int n_in_ops = 0;
  22
  23 extern ssp1601_t *ssp;
  24
  25 #define rPC    ssp->gr[SSP_PC].h
  26 #define rPMC   ssp->gr[SSP_PMC]
  27
  28 #define SSP_FLAG_Z (1<<0xd)
  29 #define SSP_FLAG_N (1<<0xf)
  30
  31 #ifndef ARM
  32 //#define DUMP_BLOCK 0x0c9a
  33 void ssp_drc_next(void){}
  34 void ssp_drc_next_patch(void){}
  35 void ssp_drc_end(void){}
  36 #endif
  37
  38 #define COUNT_OP
  39 #include "../../../cpu/drc/emit_arm.c"
  40
  41 // -----------------------------------------------------
  42
  43 static int get_inc(int mode)
  44 {
  45         int inc = (mode >> 11) & 7;
  46         if (inc != 0) {
  47                 if (inc != 7) inc--;
  48                 inc = 1 << inc; // 0 1 2 4 8 16 32 128
  49                 if (mode & 0x8000) inc = -inc; // decrement mode
  50         }
  51         return inc;
  52 }
  53
  54 u32 ssp_pm_read(int reg)
  55 {
  56         u32 d = 0, mode;
  57
  58         if (ssp->emu_status & SSP_PMC_SET)
  59         {
  60                 ssp->pmac_read[reg] = rPMC.v;
  61                 ssp->emu_status &= ~SSP_PMC_SET;
  62                 return 0;
  63         }
  64
  65         // just in case
  66         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  67
  68         mode = ssp->pmac_read[reg]>>16;
  69         if      ((mode & 0xfff0) == 0x0800) // ROM
  70         {
  71                 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
  72                 ssp->pmac_read[reg] += 1;
  73         }
  74         else if ((mode & 0x47ff) == 0x0018) // DRAM
  75         {
  76                 unsigned short *dram = (unsigned short *)svp->dram;
  77                 int inc = get_inc(mode);
  78                 d = dram[ssp->pmac_read[reg]&0xffff];
  79                 ssp->pmac_read[reg] += inc;
  80         }
  81
  82         // PMC value corresponds to last PMR accessed
  83         rPMC.v = ssp->pmac_read[reg];
  84
  85         return d;
  86 }
  87
  88 #define overwrite_write(dst, d) \
  89 { \
  90         if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
  91         if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
  92         if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
  93         if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
  94 }
  95
  96 void ssp_pm_write(u32 d, int reg)
  97 {
  98         unsigned short *dram;
  99         int mode, addr;
 100
 101         if (ssp->emu_status & SSP_PMC_SET)
 102         {
 103                 ssp->pmac_write[reg] = rPMC.v;
 104                 ssp->emu_status &= ~SSP_PMC_SET;
 105                 return;
 106         }
 107
 108         // just in case
 109         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
 110
 111         dram = (unsigned short *)svp->dram;
 112         mode = ssp->pmac_write[reg]>>16;
 113         addr = ssp->pmac_write[reg]&0xffff;
 114         if      ((mode & 0x43ff) == 0x0018) // DRAM
 115         {
 116                 int inc = get_inc(mode);
 117                 if (mode & 0x0400) {
 118                        overwrite_write(dram[addr], d);
 119                 } else dram[addr] = d;
 120                 ssp->pmac_write[reg] += inc;
 121         }
 122         else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
 123         {
 124                 if (mode & 0x0400) {
 125                        overwrite_write(dram[addr], d);
 126                 } else dram[addr] = d;
 127                 ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
 128         }
 129         else if ((mode & 0x47ff) == 0x001c) // IRAM
 130         {
 131                 int inc = get_inc(mode);
 132                 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
 133                 ssp->pmac_write[reg] += inc;
 134                 ssp->drc.iram_dirty = 1;
 135         }
 136
 137         rPMC.v = ssp->pmac_write[reg];
 138 }
 139
 140
 141 // -----------------------------------------------------
 142
 143 // 14 IRAM blocks
 144 static unsigned char iram_context_map[] =
 145 {
 146          0, 0, 0, 0, 1, 0, 0, 0, // 04
 147          0, 0, 0, 0, 0, 0, 2, 0, // 0e
 148          0, 0, 0, 0, 0, 3, 0, 4, // 15 17
 149          5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
 150          8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
 151          0, 0, 0, 0, 0, 0, 0, 0,
 152          0, 0,11, 0, 0,12, 0, 0, // 32 35
 153         13,14, 0, 0, 0, 0, 0, 0  // 38 39
 154 };
 155
 156 int ssp_get_iram_context(void)
 157 {
 158         unsigned char *ir = (unsigned char *)svp->iram_rom;
 159         int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
 160         val1 = iram_context_map[(val>>1)&0x3f];
 161
 162         if (val1 == 0) {
 163                 elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
 164                 //debug_dump2file(name, svp->iram_rom, 0x800);
 165                 //exit(1);
 166         }
 167         return val1;
 168 }
 169
 170 // -----------------------------------------------------
 171
 172 /* regs with known values */
 173 static struct
 174 {
 175         ssp_reg_t gr[8];
 176         unsigned char r[8];
 177         unsigned int pmac_read[5];
 178         unsigned int pmac_write[5];
 179         ssp_reg_t pmc;
 180         unsigned int emu_status;
 181 } known_regs;
 182
 183 #define KRREG_X     (1 << SSP_X)
 184 #define KRREG_Y     (1 << SSP_Y)
 185 #define KRREG_A     (1 << SSP_A)        /* AH only */
 186 #define KRREG_ST    (1 << SSP_ST)
 187 #define KRREG_STACK (1 << SSP_STACK)
 188 #define KRREG_PC    (1 << SSP_PC)
 189 #define KRREG_P     (1 << SSP_P)
 190 #define KRREG_PR0   (1 << 8)
 191 #define KRREG_PR4   (1 << 12)
 192 #define KRREG_AL    (1 << 16)
 193 #define KRREG_PMCM  (1 << 18)           /* only mode word of PMC */
 194 #define KRREG_PMC   (1 << 19)
 195 #define KRREG_PM0R  (1 << 20)
 196 #define KRREG_PM1R  (1 << 21)
 197 #define KRREG_PM2R  (1 << 22)
 198 #define KRREG_PM3R  (1 << 23)
 199 #define KRREG_PM4R  (1 << 24)
 200 #define KRREG_PM0W  (1 << 25)
 201 #define KRREG_PM1W  (1 << 26)
 202 #define KRREG_PM2W  (1 << 27)
 203 #define KRREG_PM3W  (1 << 28)
 204 #define KRREG_PM4W  (1 << 29)
 205
 206 /* bitfield of known register values */
 207 static u32 known_regb = 0;
 208
 209 /* known vals, which need to be flushed
 210  * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
 211  * ST means flags are being held in ARM PSR
 212  * P means that it needs to be recalculated
 213  */
 214 static u32 dirty_regb = 0;
 215
 216 /* known values of host regs.
 217  * -1            - unknown
 218  * 000000-00ffff - 16bit value
 219  * 100000-10ffff - base reg (r7) + 16bit val
 220  * 0r0000        - means reg (low) eq gr[r].h, r != AL
 221  */
 222 static int hostreg_r[4];
 223
 224 static void hostreg_clear(void)
 225 {
 226         int i;
 227         for (i = 0; i < 4; i++)
 228                 hostreg_r[i] = -1;
 229 }
 230
 231 static void hostreg_sspreg_changed(int sspreg)
 232 {
 233         int i;
 234         for (i = 0; i < 4; i++)
 235                 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
 236 }
 237
 238
 239 #define PROGRAM(x)   ((unsigned short *)svp->iram_rom)[x]
 240 #define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
 241
 242 void tr_unhandled(void)
 243 {
 244         //FILE *f = fopen("tcache.bin", "wb");
 245         //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
 246         //fclose(f);
 247         elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
 248         //exit(1);
 249 }
 250
 251 /* update P, if needed. Trashes r0 */
 252 static void tr_flush_dirty_P(void)
 253 {
 254         // TODO: const regs
 255         if (!(dirty_regb & KRREG_P)) return;
 256         EOP_MOV_REG_ASR(10, 4, 16);             // mov  r10, r4, asr #16
 257         EOP_MOV_REG_LSL( 0, 4, 16);             // mov  r0,  r4, lsl #16
 258         EOP_MOV_REG_ASR( 0, 0, 15);             // mov  r0,  r0, asr #15
 259         EOP_MUL(10, 0, 10);                     // mul  r10, r0, r10
 260         dirty_regb &= ~KRREG_P;
 261         hostreg_r[0] = -1;
 262 }
 263
 264 /* write dirty pr to host reg. Nothing is trashed */
 265 static void tr_flush_dirty_pr(int r)
 266 {
 267         int ror = 0, reg;
 268
 269         if (!(dirty_regb & (1 << (r+8)))) return;
 270
 271         switch (r&3) {
 272                 case 0: ror =    0; break;
 273                 case 1: ror = 24/2; break;
 274                 case 2: ror = 16/2; break;
 275         }
 276         reg = (r < 4) ? 8 : 9;
 277         EOP_BIC_IMM(reg,reg,ror,0xff);
 278         if (known_regs.r[r] != 0)
 279                 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
 280         dirty_regb &= ~(1 << (r+8));
 281 }
 282
 283 /* write all dirty pr0-pr7 to host regs. Nothing is trashed */
 284 static void tr_flush_dirty_prs(void)
 285 {
 286         int i, ror = 0, reg;
 287         int dirty = dirty_regb >> 8;
 288         if ((dirty&7) == 7) {
 289                 emith_move_r_imm(8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
 290                 dirty &= ~7;
 291         }
 292         if ((dirty&0x70) == 0x70) {
 293                 emith_move_r_imm(9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
 294                 dirty &= ~0x70;
 295         }
 296         /* r0-r7 */
 297         for (i = 0; dirty && i < 8; i++, dirty >>= 1)
 298         {
 299                 if (!(dirty&1)) continue;
 300                 switch (i&3) {
 301                         case 0: ror =    0; break;
 302                         case 1: ror = 24/2; break;
 303                         case 2: ror = 16/2; break;
 304                 }
 305                 reg = (i < 4) ? 8 : 9;
 306                 EOP_BIC_IMM(reg,reg,ror,0xff);
 307                 if (known_regs.r[i] != 0)
 308                         EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
 309         }
 310         dirty_regb &= ~0xff00;
 311 }
 312
 313 /* write dirty pr and "forget" it. Nothing is trashed. */
 314 static void tr_release_pr(int r)
 315 {
 316         tr_flush_dirty_pr(r);
 317         known_regb &= ~(1 << (r+8));
 318 }
 319
 320 /* fush ARM PSR to r6. Trashes r1 */
 321 static void tr_flush_dirty_ST(void)
 322 {
 323         if (!(dirty_regb & KRREG_ST)) return;
 324         EOP_BIC_IMM(6,6,0,0x0f);
 325         EOP_MRS(1);
 326         EOP_ORR_REG_LSR(6,6,1,28);
 327         dirty_regb &= ~KRREG_ST;
 328         hostreg_r[1] = -1;
 329 }
 330
 331 /* inverse of above. Trashes r1 */
 332 static void tr_make_dirty_ST(void)
 333 {
 334         if (dirty_regb & KRREG_ST) return;
 335         if (known_regb & KRREG_ST) {
 336                 int flags = 0;
 337                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
 338                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
 339                 EOP_MSR_IMM(4/2, flags);
 340         } else {
 341                 EOP_MOV_REG_LSL(1, 6, 28);
 342                 EOP_MSR_REG(1);
 343                 hostreg_r[1] = -1;
 344         }
 345         dirty_regb |= KRREG_ST;
 346 }
 347
 348 /* load 16bit val into host reg r0-r3. Nothing is trashed */
 349 static void tr_mov16(int r, int val)
 350 {
 351         if (hostreg_r[r] != val) {
 352                 emith_move_r_imm(r, val);
 353                 hostreg_r[r] = val;
 354         }
 355 }
 356
 357 static void tr_mov16_cond(int cond, int r, int val)
 358 {
 359         emith_op_imm(cond, 0, A_OP_MOV, r, val);
 360         hostreg_r[r] = -1;
 361 }
 362
 363 /* trashes r1 */
 364 static void tr_flush_dirty_pmcrs(void)
 365 {
 366         u32 i, val = (u32)-1;
 367         if (!(dirty_regb & 0x3ff80000)) return;
 368
 369         if (dirty_regb & KRREG_PMC) {
 370                 val = known_regs.pmc.v;
 371                 emith_move_r_imm(1, val);
 372                 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
 373
 374                 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
 375                         elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
 376                         tr_unhandled();
 377                 }
 378         }
 379         for (i = 0; i < 5; i++)
 380         {
 381                 if (dirty_regb & (1 << (20+i))) {
 382                         if (val != known_regs.pmac_read[i]) {
 383                                 val = known_regs.pmac_read[i];
 384                                 emith_move_r_imm(1, val);
 385                         }
 386                         EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
 387                 }
 388                 if (dirty_regb & (1 << (25+i))) {
 389                         if (val != known_regs.pmac_write[i]) {
 390                                 val = known_regs.pmac_write[i];
 391                                 emith_move_r_imm(1, val);
 392                         }
 393                         EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
 394                 }
 395         }
 396         dirty_regb &= ~0x3ff80000;
 397         hostreg_r[1] = -1;
 398 }
 399
 400 /* read bank word to r0 (upper bits zero). Thrashes r1. */
 401 static void tr_bank_read(int addr) /* word addr 0-0x1ff */
 402 {
 403         int breg = 7;
 404         if (addr > 0x7f) {
 405                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 406                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 407                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 408                 }
 409                 breg = 1;
 410         }
 411         EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1);    // ldrh r0, [r1, (op&0x7f)<<1]
 412         hostreg_r[0] = -1;
 413 }
 414
 415 /* write r0 to bank. Trashes r1. */
 416 static void tr_bank_write(int addr)
 417 {
 418         int breg = 7;
 419         if (addr > 0x7f) {
 420                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 421                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 422                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 423                 }
 424                 breg = 1;
 425         }
 426         EOP_STRH_IMM(0,breg,(addr&0x7f)<<1);            // strh r0, [r1, (op&0x7f)<<1]
 427 }
 428
 429 /* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
 430 static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
 431 {
 432         int modulo_shift = -1;  /* unknown */
 433
 434         if (mod == 0) return;
 435
 436         if (!need_modulo || mod == 1) // +!
 437                 modulo_shift = 8;
 438         else if (need_modulo && (known_regb & KRREG_ST)) {
 439                 modulo_shift = known_regs.gr[SSP_ST].h & 7;
 440                 if (modulo_shift == 0) modulo_shift = 8;
 441         }
 442
 443         if (modulo_shift == -1)
 444         {
 445                 int reg = (r < 4) ? 8 : 9;
 446                 tr_release_pr(r);
 447                 if (dirty_regb & KRREG_ST) {
 448                         // avoid flushing ARM flags
 449                         EOP_AND_IMM(1, 6, 0, 0x70);
 450                         EOP_SUB_IMM(1, 1, 0, 0x10);
 451                         EOP_AND_IMM(1, 1, 0, 0x70);
 452                         EOP_ADD_IMM(1, 1, 0, 0x10);
 453                 } else {
 454                         EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands  r1, r6, #0x70
 455                         EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
 456                 }
 457                 EOP_MOV_REG_LSR(1, 1, 4);               // mov r1, r1, lsr #4
 458                 EOP_RSB_IMM(2, 1, 0, 8);                // rsb r1, r1, #8
 459                 EOP_MOV_IMM(3, 8/2, count);             // mov r3, #0x01000000
 460                 if (r&3)
 461                         EOP_ADD_IMM(1, 1, 0, (r&3)*8);  // add r1, r1, #(r&3)*8
 462                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 463                 if (mod == 2)
 464                      EOP_SUB_REG2_LSL(reg,reg,3,2);     // sub reg, reg, #0x01000000 << r2
 465                 else EOP_ADD_REG2_LSL(reg,reg,3,2);
 466                 EOP_RSB_IMM(1, 1, 0, 32);               // rsb r1, r1, #32
 467                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 468                 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
 469         }
 470         else if (known_regb & (1 << (r + 8)))
 471         {
 472                 int modulo = (1 << modulo_shift) - 1;
 473                 if (mod == 2)
 474                      known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
 475                 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
 476         }
 477         else
 478         {
 479                 int reg = (r < 4) ? 8 : 9;
 480                 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
 481                 EOP_MOV_REG_ROR(reg,reg,ror);
 482                 // {add|sub} reg, reg, #1<<shift
 483                 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
 484                 EOP_MOV_REG_ROR(reg,reg,32-ror);
 485         }
 486 }
 487
 488 /* handle writes r0 to (rX). Trashes r1.
 489  * fortunately we can ignore modulo increment modes for writes. */
 490 static void tr_rX_write(int op)
 491 {
 492         if ((op&3) == 3)
 493         {
 494                 int mod = (op>>2) & 3; // direct addressing
 495                 tr_bank_write((op & 0x100) + mod);
 496         }
 497         else
 498         {
 499                 int r = (op&3) | ((op>>6)&4);
 500                 if (known_regb & (1 << (r + 8))) {
 501                         tr_bank_write((op&0x100) | known_regs.r[r]);
 502                 } else {
 503                         int reg = (r < 4) ? 8 : 9;
 504                         int ror = ((4 - (r&3))*8) & 0x1f;
 505                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 506                         if (r >= 4)
 507                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 508                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 509                         else     EOP_ADD_REG_LSL(1,7,1,1);
 510                         EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 511                         hostreg_r[1] = -1;
 512                 }
 513                 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
 514         }
 515 }
 516
 517 /* read (rX) to r0. Trashes r1-r3. */
 518 static void tr_rX_read(int r, int mod)
 519 {
 520         if ((r&3) == 3)
 521         {
 522                 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
 523         }
 524         else
 525         {
 526                 if (known_regb & (1 << (r + 8))) {
 527                         tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
 528                 } else {
 529                         int reg = (r < 4) ? 8 : 9;
 530                         int ror = ((4 - (r&3))*8) & 0x1f;
 531                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 532                         if (r >= 4)
 533                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 534                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 535                         else     EOP_ADD_REG_LSL(1,7,1,1);
 536                         EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 537                         hostreg_r[0] = hostreg_r[1] = -1;
 538                 }
 539                 tr_ptrr_mod(r, mod, 1, 1);
 540         }
 541 }
 542
 543 /* read ((rX)) to r0. Trashes r1,r2. */
 544 static void tr_rX_read2(int op)
 545 {
 546         int r = (op&3) | ((op>>6)&4); // src
 547
 548         if ((r&3) == 3) {
 549                 tr_bank_read((op&0x100) | ((op>>2)&3));
 550         } else if (known_regb & (1 << (r+8))) {
 551                 tr_bank_read((op&0x100) | known_regs.r[r]);
 552         } else {
 553                 int reg = (r < 4) ? 8 : 9;
 554                 int ror = ((4 - (r&3))*8) & 0x1f;
 555                 EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 556                 if (r >= 4)
 557                         EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 558                 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 559                 else     EOP_ADD_REG_LSL(1,7,1,1);
 560                 EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 561         }
 562         EOP_LDR_IMM(2,7,0x48c);                                 // ptr_iram_rom
 563         EOP_ADD_REG_LSL(2,2,0,1);                               // add  r2, r2, r0, lsl #1
 564         EOP_ADD_IMM(0,0,0,1);                                   // add  r0, r0, #1
 565         if ((r&3) == 3) {
 566                 tr_bank_write((op&0x100) | ((op>>2)&3));
 567         } else if (known_regb & (1 << (r+8))) {
 568                 tr_bank_write((op&0x100) | known_regs.r[r]);
 569         } else {
 570                 EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 571                 hostreg_r[1] = -1;
 572         }
 573         EOP_LDRH_SIMPLE(0,2);                                   // ldrh r0, [r2]
 574         hostreg_r[0] = hostreg_r[2] = -1;
 575 }
 576
 577 // check if AL is going to be used later in block
 578 static int tr_predict_al_need(void)
 579 {
 580         int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
 581
 582         while (1)
 583         {
 584                 op = PROGRAM(pc);
 585                 switch (op >> 9)
 586                 {
 587                         // ld d, s
 588                         case 0x00:
 589                                 tmpv2 = (op >> 4) & 0xf; // dst
 590                                 tmpv  = op & 0xf; // src
 591                                 if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
 592                                         return 0;
 593                                 break;
 594
 595                         // ld (ri), s
 596                         case 0x02:
 597                         // ld ri, s
 598                         case 0x0a:
 599                         // OP a, s
 600                         case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
 601                                 tmpv  = op & 0xf; // src
 602                                 if (tmpv == SSP_AL) // OP *, AL
 603                                         return 1;
 604                                 break;
 605
 606                         case 0x04:
 607                         case 0x06:
 608                         case 0x14:
 609                         case 0x34:
 610                         case 0x44:
 611                         case 0x64:
 612                         case 0x74: pc++; break;
 613
 614                         // call cond, addr
 615                         case 0x24:
 616                         // bra cond, addr
 617                         case 0x26:
 618                         // mod cond, op
 619                         case 0x48:
 620                         // mpys?
 621                         case 0x1b:
 622                         // mpya (rj), (ri), b
 623                         case 0x4b: return 1;
 624
 625                         // mld (rj), (ri), b
 626                         case 0x5b: return 0; // cleared anyway
 627
 628                         // and A, *
 629                         case 0x50:
 630                                 tmpv  = op & 0xf; // src
 631                                 if (tmpv == SSP_AL) return 1;
 632                         case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
 633                                 return 0;
 634                 }
 635                 pc++;
 636         }
 637 }
 638
 639
 640 /* get ARM cond which would mean that SSP cond is satisfied. No trash. */
 641 static int tr_cond_check(int op)
 642 {
 643         int f = (op & 0x100) >> 8;
 644         switch (op&0xf0) {
 645                 case 0x00: return A_COND_AL;    /* always true */
 646                 case 0x50:                      /* Z matches f(?) bit */
 647                         if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
 648                         EOP_TST_IMM(6, 0, 4);
 649                         return f ? A_COND_NE : A_COND_EQ;
 650                 case 0x70:                      /* N matches f(?) bit */
 651                         if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
 652                         EOP_TST_IMM(6, 0, 8);
 653                         return f ? A_COND_NE : A_COND_EQ;
 654                 default:
 655                         elprintf(EL_ANOMALY, "unimplemented cond?\n");
 656                         tr_unhandled();
 657                         return 0;
 658         }
 659 }
 660
 661 static int tr_neg_cond(int cond)
 662 {
 663         switch (cond) {
 664                 case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
 665                 case A_COND_EQ: return A_COND_NE;
 666                 case A_COND_NE: return A_COND_EQ;
 667                 case A_COND_MI: return A_COND_PL;
 668                 case A_COND_PL: return A_COND_MI;
 669                 default:        elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
 670         }
 671         return 0;
 672 }
 673
 674 static int tr_aop_ssp2arm(int op)
 675 {
 676         switch (op) {
 677                 case 1: return A_OP_SUB;
 678                 case 3: return A_OP_CMP;
 679                 case 4: return A_OP_ADD;
 680                 case 5: return A_OP_AND;
 681                 case 6: return A_OP_ORR;
 682                 case 7: return A_OP_EOR;
 683         }
 684
 685         tr_unhandled();
 686         return 0;
 687 }
 688
 689 // -----------------------------------------------------
 690
 691 //@ r4:  XXYY
 692 //@ r5:  A
 693 //@ r6:  STACK and emu flags
 694 //@ r7:  SSP context
 695 //@ r10: P
 696
 697 // read general reg to r0. Trashes r1
 698 static void tr_GR0_to_r0(int op)
 699 {
 700         tr_mov16(0, 0xffff);
 701 }
 702
 703 static void tr_X_to_r0(int op)
 704 {
 705         if (hostreg_r[0] != (SSP_X<<16)) {
 706                 EOP_MOV_REG_LSR(0, 4, 16);      // mov  r0, r4, lsr #16
 707                 hostreg_r[0] = SSP_X<<16;
 708         }
 709 }
 710
 711 static void tr_Y_to_r0(int op)
 712 {
 713         if (hostreg_r[0] != (SSP_Y<<16)) {
 714                 EOP_MOV_REG_SIMPLE(0, 4);       // mov  r0, r4
 715                 hostreg_r[0] = SSP_Y<<16;
 716         }
 717 }
 718
 719 static void tr_A_to_r0(int op)
 720 {
 721         if (hostreg_r[0] != (SSP_A<<16)) {
 722                 EOP_MOV_REG_LSR(0, 5, 16);      // mov  r0, r5, lsr #16  @ AH
 723                 hostreg_r[0] = SSP_A<<16;
 724         }
 725 }
 726
 727 static void tr_ST_to_r0(int op)
 728 {
 729         // VR doesn't need much accuracy here..
 730         EOP_MOV_REG_LSR(0, 6, 4);               // mov  r0, r6, lsr #4
 731         EOP_AND_IMM(0, 0, 0, 0x67);             // and  r0, r0, #0x67
 732         hostreg_r[0] = -1;
 733 }
 734
 735 static void tr_STACK_to_r0(int op)
 736 {
 737         // 448
 738         EOP_SUB_IMM(6, 6,  8/2, 0x20);          // sub  r6, r6, #1<<29
 739         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 740         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 741         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 742         EOP_LDRH_SIMPLE(0, 1);                  // ldrh r0, [r1]
 743         hostreg_r[0] = hostreg_r[1] = -1;
 744 }
 745
 746 static void tr_PC_to_r0(int op)
 747 {
 748         tr_mov16(0, known_regs.gr[SSP_PC].h);
 749 }
 750
 751 static void tr_P_to_r0(int op)
 752 {
 753         tr_flush_dirty_P();
 754         EOP_MOV_REG_LSR(0, 10, 16);             // mov  r0, r10, lsr #16
 755         hostreg_r[0] = -1;
 756 }
 757
 758 static void tr_AL_to_r0(int op)
 759 {
 760         if (op == 0x000f) {
 761                 if (known_regb & KRREG_PMC) {
 762                         known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 763                 } else {
 764                         EOP_LDR_IMM(0,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 765                         EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 766                         EOP_STR_IMM(0,7,0x484);
 767                 }
 768         }
 769
 770         if (hostreg_r[0] != (SSP_AL<<16)) {
 771                 EOP_MOV_REG_SIMPLE(0, 5);       // mov  r0, r5
 772                 hostreg_r[0] = SSP_AL<<16;
 773         }
 774 }
 775
 776 static void tr_PMX_to_r0(int reg)
 777 {
 778         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
 779         {
 780                 known_regs.pmac_read[reg] = known_regs.pmc.v;
 781                 known_regs.emu_status &= ~SSP_PMC_SET;
 782                 known_regb |= 1 << (20+reg);
 783                 dirty_regb |= 1 << (20+reg);
 784                 return;
 785         }
 786
 787         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
 788         {
 789                 u32 pmcv = known_regs.pmac_read[reg];
 790                 int mode = pmcv>>16;
 791                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 792
 793                 if      ((mode & 0xfff0) == 0x0800)
 794                 {
 795                         EOP_LDR_IMM(1,7,0x488);         // rom_ptr
 796                         emith_move_r_imm(0, (pmcv&0xfffff)<<1);
 797                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 798                         known_regs.pmac_read[reg] += 1;
 799                 }
 800                 else if ((mode & 0x47ff) == 0x0018) // DRAM
 801                 {
 802                         int inc = get_inc(mode);
 803                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
 804                         emith_move_r_imm(0, (pmcv&0xffff)<<1);
 805                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 806                         if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
 807                         {
 808                                 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
 809                                 tr_flush_dirty_ST();
 810                                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 811                                 EOP_TST_REG_SIMPLE(0,0);
 812                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1);       // subeq r11, r11, #1024
 813                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
 814                                 EOP_STR_IMM(1,7,0x484);                 // str r1, [r7, #0x484] // emu_status
 815                         }
 816                         known_regs.pmac_read[reg] += inc;
 817                 }
 818                 else
 819                 {
 820                         tr_unhandled();
 821                 }
 822                 known_regs.pmc.v = known_regs.pmac_read[reg];
 823                 //known_regb |= KRREG_PMC;
 824                 dirty_regb |= KRREG_PMC;
 825                 dirty_regb |= 1 << (20+reg);
 826                 hostreg_r[0] = hostreg_r[1] = -1;
 827                 return;
 828         }
 829
 830         known_regb &= ~KRREG_PMC;
 831         dirty_regb &= ~KRREG_PMC;
 832         known_regb &= ~(1 << (20+reg));
 833         dirty_regb &= ~(1 << (20+reg));
 834
 835         // call the C code to handle this
 836         tr_flush_dirty_ST();
 837         //tr_flush_dirty_pmcrs();
 838         tr_mov16(0, reg);
 839         emith_call(ssp_pm_read);
 840         hostreg_clear();
 841 }
 842
 843 static void tr_PM0_to_r0(int op)
 844 {
 845         tr_PMX_to_r0(0);
 846 }
 847
 848 static void tr_PM1_to_r0(int op)
 849 {
 850         tr_PMX_to_r0(1);
 851 }
 852
 853 static void tr_PM2_to_r0(int op)
 854 {
 855         tr_PMX_to_r0(2);
 856 }
 857
 858 static void tr_XST_to_r0(int op)
 859 {
 860         EOP_ADD_IMM(0, 7, 24/2, 4);     // add r0, r7, #0x400
 861         EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
 862 }
 863
 864 static void tr_PM4_to_r0(int op)
 865 {
 866         tr_PMX_to_r0(4);
 867 }
 868
 869 static void tr_PMC_to_r0(int op)
 870 {
 871         if (known_regb & KRREG_PMC)
 872         {
 873                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
 874                         known_regs.emu_status |= SSP_PMC_SET;
 875                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 876                         // do nothing - this is handled elsewhere
 877                 } else {
 878                         tr_mov16(0, known_regs.pmc.l);
 879                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
 880                 }
 881         }
 882         else
 883         {
 884                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 885                 tr_flush_dirty_ST();
 886                 if (op != 0x000e)
 887                         EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
 888                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
 889                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
 890                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
 891                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
 892                 EOP_STR_IMM(1,7,0x484);
 893                 hostreg_r[0] = hostreg_r[1] = -1;
 894         }
 895 }
 896
 897
 898 typedef void (tr_read_func)(int op);
 899
 900 static tr_read_func *tr_read_funcs[16] =
 901 {
 902         tr_GR0_to_r0,
 903         tr_X_to_r0,
 904         tr_Y_to_r0,
 905         tr_A_to_r0,
 906         tr_ST_to_r0,
 907         tr_STACK_to_r0,
 908         tr_PC_to_r0,
 909         tr_P_to_r0,
 910         tr_PM0_to_r0,
 911         tr_PM1_to_r0,
 912         tr_PM2_to_r0,
 913         tr_XST_to_r0,
 914         tr_PM4_to_r0,
 915         (tr_read_func *)tr_unhandled,
 916         tr_PMC_to_r0,
 917         tr_AL_to_r0
 918 };
 919
 920
 921 // write r0 to general reg handlers. Trashes r1
 922 #define TR_WRITE_R0_TO_REG(reg) \
 923 { \
 924         hostreg_sspreg_changed(reg); \
 925         hostreg_r[0] = (reg)<<16; \
 926         if (const_val != -1) { \
 927                 known_regs.gr[reg].h = const_val; \
 928                 known_regb |= 1 << (reg); \
 929         } else { \
 930                 known_regb &= ~(1 << (reg)); \
 931         } \
 932 }
 933
 934 static void tr_r0_to_GR0(int const_val)
 935 {
 936         // do nothing
 937 }
 938
 939 static void tr_r0_to_X(int const_val)
 940 {
 941         EOP_MOV_REG_LSL(4, 4, 16);              // mov  r4, r4, lsl #16
 942         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 943         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 944         dirty_regb |= KRREG_P;                  // touching X or Y makes P dirty.
 945         TR_WRITE_R0_TO_REG(SSP_X);
 946 }
 947
 948 static void tr_r0_to_Y(int const_val)
 949 {
 950         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 951         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 952         EOP_MOV_REG_ROR(4, 4, 16);              // mov  r4, r4, ror #16
 953         dirty_regb |= KRREG_P;
 954         TR_WRITE_R0_TO_REG(SSP_Y);
 955 }
 956
 957 static void tr_r0_to_A(int const_val)
 958 {
 959         if (tr_predict_al_need()) {
 960                 EOP_MOV_REG_LSL(5, 5, 16);      // mov  r5, r5, lsl #16
 961                 EOP_MOV_REG_LSR(5, 5, 16);      // mov  r5, r5, lsr #16  @ AL
 962                 EOP_ORR_REG_LSL(5, 5, 0, 16);   // orr  r5, r5, r0, lsl #16
 963         }
 964         else
 965                 EOP_MOV_REG_LSL(5, 0, 16);
 966         TR_WRITE_R0_TO_REG(SSP_A);
 967 }
 968
 969 static void tr_r0_to_ST(int const_val)
 970 {
 971         // VR doesn't need much accuracy here..
 972         EOP_AND_IMM(1, 0,   0, 0x67);           // and   r1, r0, #0x67
 973         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
 974         EOP_ORR_REG_LSL(6, 6, 1, 4);            // orr   r6, r6, r1, lsl #4
 975         TR_WRITE_R0_TO_REG(SSP_ST);
 976         hostreg_r[1] = -1;
 977         dirty_regb &= ~KRREG_ST;
 978 }
 979
 980 static void tr_r0_to_STACK(int const_val)
 981 {
 982         // 448
 983         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 984         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 985         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 986         EOP_STRH_SIMPLE(0, 1);                  // strh r0, [r1]
 987         EOP_ADD_IMM(6, 6,  8/2, 0x20);          // add  r6, r6, #1<<29
 988         hostreg_r[1] = -1;
 989 }
 990
 991 static void tr_r0_to_PC(int const_val)
 992 {
 993 /*
 994  * do nothing - dispatcher will take care of this
 995         EOP_MOV_REG_LSL(1, 0, 16);              // mov  r1, r0, lsl #16
 996         EOP_STR_IMM(1,7,0x400+6*4);             // str  r1, [r7, #(0x400+6*8)]
 997         hostreg_r[1] = -1;
 998 */
 999 }
1000
1001 static void tr_r0_to_AL(int const_val)
1002 {
1003         EOP_MOV_REG_LSR(5, 5, 16);              // mov  r5, r5, lsr #16
1004         EOP_ORR_REG_LSL(5, 5, 0, 16);           // orr  r5, r5, r0, lsl #16
1005         EOP_MOV_REG_ROR(5, 5, 16);              // mov  r5, r5, ror #16
1006         hostreg_sspreg_changed(SSP_AL);
1007         if (const_val != -1) {
1008                 known_regs.gr[SSP_A].l = const_val;
1009                 known_regb |= 1 << SSP_AL;
1010         } else
1011                 known_regb &= ~(1 << SSP_AL);
1012 }
1013
1014 static void tr_r0_to_PMX(int reg)
1015 {
1016         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
1017         {
1018                 known_regs.pmac_write[reg] = known_regs.pmc.v;
1019                 known_regs.emu_status &= ~SSP_PMC_SET;
1020                 known_regb |= 1 << (25+reg);
1021                 dirty_regb |= 1 << (25+reg);
1022                 return;
1023         }
1024
1025         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
1026         {
1027                 int mode, addr;
1028
1029                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1030
1031                 mode = known_regs.pmac_write[reg]>>16;
1032                 addr = known_regs.pmac_write[reg]&0xffff;
1033                 if      ((mode & 0x43ff) == 0x0018) // DRAM
1034                 {
1035                         int inc = get_inc(mode);
1036                         if (mode & 0x0400) tr_unhandled();
1037                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
1038                         emith_move_r_imm(2, addr << 1);
1039                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1040                         known_regs.pmac_write[reg] += inc;
1041                 }
1042                 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
1043                 {
1044                         if (mode & 0x0400) tr_unhandled();
1045                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
1046                         emith_move_r_imm(2, addr << 1);
1047                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1048                         known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
1049                 }
1050                 else if ((mode & 0x47ff) == 0x001c) // IRAM
1051                 {
1052                         int inc = get_inc(mode);
1053                         EOP_LDR_IMM(1,7,0x48c);         // iram_ptr
1054                         emith_move_r_imm(2, (addr&0x3ff) << 1);
1055                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1056                         EOP_MOV_IMM(1,0,1);
1057                         EOP_STR_IMM(1,7,0x494);         // iram_dirty
1058                         known_regs.pmac_write[reg] += inc;
1059                 }
1060                 else
1061                         tr_unhandled();
1062
1063                 known_regs.pmc.v = known_regs.pmac_write[reg];
1064                 //known_regb |= KRREG_PMC;
1065                 dirty_regb |= KRREG_PMC;
1066                 dirty_regb |= 1 << (25+reg);
1067                 hostreg_r[1] = hostreg_r[2] = -1;
1068                 return;
1069         }
1070
1071         known_regb &= ~KRREG_PMC;
1072         dirty_regb &= ~KRREG_PMC;
1073         known_regb &= ~(1 << (25+reg));
1074         dirty_regb &= ~(1 << (25+reg));
1075
1076         // call the C code to handle this
1077         tr_flush_dirty_ST();
1078         //tr_flush_dirty_pmcrs();
1079         tr_mov16(1, reg);
1080         emith_call(ssp_pm_write);
1081         hostreg_clear();
1082 }
1083
1084 static void tr_r0_to_PM0(int const_val)
1085 {
1086         tr_r0_to_PMX(0);
1087 }
1088
1089 static void tr_r0_to_PM1(int const_val)
1090 {
1091         tr_r0_to_PMX(1);
1092 }
1093
1094 static void tr_r0_to_PM2(int const_val)
1095 {
1096         tr_r0_to_PMX(2);
1097 }
1098
1099 static void tr_r0_to_PM4(int const_val)
1100 {
1101         tr_r0_to_PMX(4);
1102 }
1103
1104 static void tr_r0_to_PMC(int const_val)
1105 {
1106         if ((known_regb & KRREG_PMC) && const_val != -1)
1107         {
1108                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1109                         known_regs.emu_status |= SSP_PMC_SET;
1110                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1111                         known_regs.pmc.h = const_val;
1112                 } else {
1113                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1114                         known_regs.pmc.l = const_val;
1115                 }
1116         }
1117         else
1118         {
1119                 tr_flush_dirty_ST();
1120                 if (known_regb & KRREG_PMC) {
1121                         emith_move_r_imm(1, known_regs.pmc.v);
1122                         EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
1123                         known_regb &= ~KRREG_PMC;
1124                         dirty_regb &= ~KRREG_PMC;
1125                 }
1126                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
1127                 EOP_ADD_IMM(2,7,24/2,4);                // add r2, r7, #0x400
1128                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1129                 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4);         // strxx r0, [r2, #SSP_PMC]
1130                 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1131                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1132                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1133                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
1134                 EOP_STR_IMM(1,7,0x484);
1135                 hostreg_r[1] = hostreg_r[2] = -1;
1136         }
1137 }
1138
1139 typedef void (tr_write_func)(int const_val);
1140
1141 static tr_write_func *tr_write_funcs[16] =
1142 {
1143         tr_r0_to_GR0,
1144         tr_r0_to_X,
1145         tr_r0_to_Y,
1146         tr_r0_to_A,
1147         tr_r0_to_ST,
1148         tr_r0_to_STACK,
1149         tr_r0_to_PC,
1150         (tr_write_func *)tr_unhandled,
1151         tr_r0_to_PM0,
1152         tr_r0_to_PM1,
1153         tr_r0_to_PM2,
1154         (tr_write_func *)tr_unhandled,
1155         tr_r0_to_PM4,
1156         (tr_write_func *)tr_unhandled,
1157         tr_r0_to_PMC,
1158         tr_r0_to_AL
1159 };
1160
1161 static void tr_mac_load_XY(int op)
1162 {
1163         tr_rX_read(op&3, (op>>2)&3); // X
1164         EOP_MOV_REG_LSL(4, 0, 16);
1165         tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1166         EOP_ORR_REG_SIMPLE(4, 0);
1167         dirty_regb |= KRREG_P;
1168         hostreg_sspreg_changed(SSP_X);
1169         hostreg_sspreg_changed(SSP_Y);
1170         known_regb &= ~KRREG_X;
1171         known_regb &= ~KRREG_Y;
1172 }
1173
1174 // -----------------------------------------------------
1175
1176 static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
1177 {
1178         u32 pmcv, tmpv;
1179         if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1180
1181         // programming PMC:
1182         // ldi PMC, imm1
1183         // ldi PMC, imm2
1184         (*pc)++;
1185         pmcv = imm | (PROGRAM((*pc)++) << 16);
1186         known_regs.pmc.v = pmcv;
1187         known_regb |= KRREG_PMC;
1188         dirty_regb |= KRREG_PMC;
1189         known_regs.emu_status |= SSP_PMC_SET;
1190         n_in_ops++;
1191
1192         // check for possible reg programming
1193         tmpv = PROGRAM(*pc);
1194         if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1195         {
1196                 int is_write = (tmpv & 0xff8f) == 0x80;
1197                 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1198                 if (reg > 4) tr_unhandled();
1199                 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
1200                 if (is_write)
1201                         known_regs.pmac_write[reg] = pmcv;
1202                 else
1203                         known_regs.pmac_read[reg] = pmcv;
1204                 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1205                 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1206                 known_regs.emu_status &= ~SSP_PMC_SET;
1207                 (*pc)++;
1208                 n_in_ops++;
1209                 return 5;
1210         }
1211
1212         tr_unhandled();
1213         return 4;
1214 }
1215
1216 static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1217
1218 static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1219 {
1220         // ldi ST, 0
1221         // ldi PM0, 0
1222         // ldi PM0, 0
1223         // ldi ST, 60h
1224         unsigned short *pp;
1225         if (op != 0x0840 || imm != 0) return 0;
1226         pp = PROGRAM_P(*pc);
1227         if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1228
1229         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
1230         EOP_ORR_IMM(6, 6, 24/2, 6);             // orr   r6, r6, 0x600
1231         hostreg_sspreg_changed(SSP_ST);
1232         known_regs.gr[SSP_ST].h = 0x60;
1233         known_regb |= 1 << SSP_ST;
1234         dirty_regb &= ~KRREG_ST;
1235         (*pc) += 3*2;
1236         n_in_ops += 3;
1237         return 4*2;
1238 }
1239
1240 static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1241 {
1242         // @ 3DA2 and 426A
1243         // ld PMC, (r3|00)
1244         // ld (r3|00), PMC
1245         // ld -, AL
1246         if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1247
1248         tr_bank_read(0);
1249         EOP_MOV_REG_LSL(0, 0, 4);
1250         EOP_ORR_REG_LSR(0, 0, 0, 16);
1251         tr_bank_write(0);
1252         (*pc) += 2;
1253         n_in_ops += 2;
1254         return 3;
1255 }
1256
1257 // -----------------------------------------------------
1258
1259 static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
1260 {
1261         u32 tmpv, tmpv2, tmpv3;
1262         int ret = 0;
1263         known_regs.gr[SSP_PC].h = *pc;
1264
1265         switch (op >> 9)
1266         {
1267                 // ld d, s
1268                 case 0x00:
1269                         if (op == 0) { ret++; break; } // nop
1270                         tmpv  = op & 0xf; // src
1271                         tmpv2 = (op >> 4) & 0xf; // dst
1272                         if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1273                                 tr_flush_dirty_P();
1274                                 EOP_MOV_REG_SIMPLE(5, 10);
1275                                 hostreg_sspreg_changed(SSP_A);
1276                                 known_regb &= ~(KRREG_A|KRREG_AL);
1277                                 ret++; break;
1278                         }
1279                         tr_read_funcs[tmpv](op);
1280                         tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
1281                         if (tmpv2 == SSP_PC) {
1282                                 ret |= 0x10000;
1283                                 *end_cond = -A_COND_AL;
1284                         }
1285                         ret++; break;
1286
1287                 // ld d, (ri)
1288                 case 0x01: {
1289                         int r = (op&3) | ((op>>6)&4);
1290                         int mod = (op>>2)&3;
1291                         tmpv = (op >> 4) & 0xf; // dst
1292                         ret = tr_detect_rotate(op, pc, imm);
1293                         if (ret > 0) break;
1294                         if (tmpv != 0)
1295                                 tr_rX_read(r, mod);
1296                         else {
1297                                 int cnt = 1;
1298                                 while (PROGRAM(*pc) == op) {
1299                                         (*pc)++; cnt++; ret++;
1300                                         n_in_ops++;
1301                                 }
1302                                 tr_ptrr_mod(r, mod, 1, cnt); // skip
1303                         }
1304                         tr_write_funcs[tmpv](-1);
1305                         if (tmpv == SSP_PC) {
1306                                 ret |= 0x10000;
1307                                 *end_cond = -A_COND_AL;
1308                         }
1309                         ret++; break;
1310                 }
1311
1312                 // ld (ri), s
1313                 case 0x02:
1314                         tmpv = (op >> 4) & 0xf; // src
1315                         tr_read_funcs[tmpv](op);
1316                         tr_rX_write(op);
1317                         ret++; break;
1318
1319                 // ld a, adr
1320                 case 0x03:
1321                         tr_bank_read(op&0x1ff);
1322                         tr_r0_to_A(-1);
1323                         ret++; break;
1324
1325                 // ldi d, imm
1326                 case 0x04:
1327                         tmpv = (op & 0xf0) >> 4; // dst
1328                         ret = tr_detect_pm0_block(op, pc, imm);
1329                         if (ret > 0) break;
1330                         ret = tr_detect_set_pm(op, pc, imm);
1331                         if (ret > 0) break;
1332                         tr_mov16(0, imm);
1333                         tr_write_funcs[tmpv](imm);
1334                         if (tmpv == SSP_PC) {
1335                                 ret |= 0x10000;
1336                                 *jump_pc = imm;
1337                         }
1338                         ret += 2; break;
1339
1340                 // ld d, ((ri))
1341                 case 0x05:
1342                         tmpv2 = (op >> 4) & 0xf;  // dst
1343                         tr_rX_read2(op);
1344                         tr_write_funcs[tmpv2](-1);
1345                         if (tmpv2 == SSP_PC) {
1346                                 ret |= 0x10000;
1347                                 *end_cond = -A_COND_AL;
1348                         }
1349                         ret += 3; break;
1350
1351                 // ldi (ri), imm
1352                 case 0x06:
1353                         tr_mov16(0, imm);
1354                         tr_rX_write(op);
1355                         ret += 2; break;
1356
1357                 // ld adr, a
1358                 case 0x07:
1359                         tr_A_to_r0(op);
1360                         tr_bank_write(op&0x1ff);
1361                         ret++; break;
1362
1363                 // ld d, ri
1364                 case 0x09: {
1365                         int r;
1366                         r = (op&3) | ((op>>6)&4); // src
1367                         tmpv2 = (op >> 4) & 0xf;  // dst
1368                         if ((r&3) == 3) tr_unhandled();
1369
1370                         if (known_regb & (1 << (r+8))) {
1371                                 tr_mov16(0, known_regs.r[r]);
1372                                 tr_write_funcs[tmpv2](known_regs.r[r]);
1373                         } else {
1374                                 int reg = (r < 4) ? 8 : 9;
1375                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1376                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1377                                 hostreg_r[0] = -1;
1378                                 tr_write_funcs[tmpv2](-1);
1379                         }
1380                         ret++; break;
1381                 }
1382
1383                 // ld ri, s
1384                 case 0x0a: {
1385                         int r;
1386                         r = (op&3) | ((op>>6)&4); // dst
1387                         tmpv = (op >> 4) & 0xf;   // src
1388                         if ((r&3) == 3) tr_unhandled();
1389
1390                         if (known_regb & (1 << tmpv)) {
1391                                 known_regs.r[r] = known_regs.gr[tmpv].h;
1392                                 known_regb |= 1 << (r + 8);
1393                                 dirty_regb |= 1 << (r + 8);
1394                         } else {
1395                                 int reg = (r < 4) ? 8 : 9;
1396                                 int ror = ((4 - (r&3))*8) & 0x1f;
1397                                 tr_read_funcs[tmpv](op);
1398                                 EOP_BIC_IMM(reg, reg, ror/2, 0xff);             // bic r{7,8}, r{7,8}, <mask>
1399                                 EOP_AND_IMM(0, 0, 0, 0xff);                     // and r0, r0, 0xff
1400                                 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8);          // orr r{7,8}, r{7,8}, r0, lsl #lsl
1401                                 hostreg_r[0] = -1;
1402                                 known_regb &= ~(1 << (r+8));
1403                                 dirty_regb &= ~(1 << (r+8));
1404                         }
1405                         ret++; break;
1406                 }
1407
1408                 // ldi ri, simm
1409                 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1410                         tmpv = (op>>8)&7;
1411                         known_regs.r[tmpv] = op;
1412                         known_regb |= 1 << (tmpv + 8);
1413                         dirty_regb |= 1 << (tmpv + 8);
1414                         ret++; break;
1415
1416                 // call cond, addr
1417                 case 0x24: {
1418                         u32 *jump_op = NULL;
1419                         tmpv = tr_cond_check(op);
1420                         if (tmpv != A_COND_AL) {
1421                                 jump_op = tcache_ptr;
1422                                 EOP_MOV_IMM(0, 0, 0); // placeholder for branch
1423                         }
1424                         tr_mov16(0, *pc);
1425                         tr_r0_to_STACK(*pc);
1426                         if (tmpv != A_COND_AL) {
1427                                 u32 *real_ptr = tcache_ptr;
1428                                 tcache_ptr = jump_op;
1429                                 EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
1430                                 tcache_ptr = real_ptr;
1431                         }
1432                         tr_mov16_cond(tmpv, 0, imm);
1433                         if (tmpv != A_COND_AL)
1434                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1435                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1436                         ret |= 0x10000;
1437                         *end_cond = tmpv;
1438                         *jump_pc = imm;
1439                         ret += 2; break;
1440                 }
1441
1442                 // ld d, (a)
1443                 case 0x25:
1444                         tmpv2 = (op >> 4) & 0xf;  // dst
1445                         tr_A_to_r0(op);
1446                         EOP_LDR_IMM(1,7,0x48c);                                 // ptr_iram_rom
1447                         EOP_ADD_REG_LSL(0,1,0,1);                               // add  r0, r1, r0, lsl #1
1448                         EOP_LDRH_SIMPLE(0,0);                                   // ldrh r0, [r0]
1449                         hostreg_r[0] = hostreg_r[1] = -1;
1450                         tr_write_funcs[tmpv2](-1);
1451                         if (tmpv2 == SSP_PC) {
1452                                 ret |= 0x10000;
1453                                 *end_cond = -A_COND_AL;
1454                         }
1455                         ret += 3; break;
1456
1457                 // bra cond, addr
1458                 case 0x26:
1459                         tmpv = tr_cond_check(op);
1460                         tr_mov16_cond(tmpv, 0, imm);
1461                         if (tmpv != A_COND_AL)
1462                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1463                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1464                         ret |= 0x10000;
1465                         *end_cond = tmpv;
1466                         *jump_pc = imm;
1467                         ret += 2; break;
1468
1469                 // mod cond, op
1470                 case 0x48: {
1471                         // check for repeats of this op
1472                         tmpv = 1; // count
1473                         while (PROGRAM(*pc) == op && (op & 7) != 6) {
1474                                 (*pc)++; tmpv++;
1475                                 n_in_ops++;
1476                         }
1477                         if ((op&0xf0) != 0) // !always
1478                                 tr_make_dirty_ST();
1479
1480                         tmpv2 = tr_cond_check(op);
1481                         switch (op & 7) {
1482                                 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1483                                 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1484                                 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
1485                                 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor  r1, r5, r5, asr #31
1486                                         EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
1487                                         hostreg_r[1] = -1; break; // abs
1488                                 default: tr_unhandled();
1489                         }
1490
1491                         hostreg_sspreg_changed(SSP_A);
1492                         dirty_regb |=  KRREG_ST;
1493                         known_regb &= ~KRREG_ST;
1494                         known_regb &= ~(KRREG_A|KRREG_AL);
1495                         ret += tmpv; break;
1496                 }
1497
1498                 // mpys?
1499                 case 0x1b:
1500                         tr_flush_dirty_P();
1501                         tr_mac_load_XY(op);
1502                         tr_make_dirty_ST();
1503                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1504                         hostreg_sspreg_changed(SSP_A);
1505                         known_regb &= ~(KRREG_A|KRREG_AL);
1506                         dirty_regb |= KRREG_ST;
1507                         ret++; break;
1508
1509                 // mpya (rj), (ri), b
1510                 case 0x4b:
1511                         tr_flush_dirty_P();
1512                         tr_mac_load_XY(op);
1513                         tr_make_dirty_ST();
1514                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1515                         hostreg_sspreg_changed(SSP_A);
1516                         known_regb &= ~(KRREG_A|KRREG_AL);
1517                         dirty_regb |= KRREG_ST;
1518                         ret++; break;
1519
1520                 // mld (rj), (ri), b
1521                 case 0x5b:
1522                         EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1523                         hostreg_sspreg_changed(SSP_A);
1524                         known_regs.gr[SSP_A].v = 0;
1525                         known_regb |= (KRREG_A|KRREG_AL);
1526                         dirty_regb |= KRREG_ST;
1527                         tr_mac_load_XY(op);
1528                         ret++; break;
1529
1530                 // OP a, s
1531                 case 0x10:
1532                 case 0x30:
1533                 case 0x40:
1534                 case 0x50:
1535                 case 0x60:
1536                 case 0x70:
1537                         tmpv = op & 0xf; // src
1538                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1539                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1540                         if (tmpv == SSP_P) {
1541                                 tr_flush_dirty_P();
1542                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1543                         } else if (tmpv == SSP_A) {
1544                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1545                         } else {
1546                                 tr_read_funcs[tmpv](op);
1547                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1548                         }
1549                         hostreg_sspreg_changed(SSP_A);
1550                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1551                         dirty_regb |= KRREG_ST;
1552                         ret++; break;
1553
1554                 // OP a, (ri)
1555                 case 0x11:
1556                 case 0x31:
1557                 case 0x41:
1558                 case 0x51:
1559                 case 0x61:
1560                 case 0x71:
1561                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1562                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1563                         tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1564                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1565                         hostreg_sspreg_changed(SSP_A);
1566                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1567                         dirty_regb |= KRREG_ST;
1568                         ret++; break;
1569
1570                 // OP a, adr
1571                 case 0x13:
1572                 case 0x33:
1573                 case 0x43:
1574                 case 0x53:
1575                 case 0x63:
1576                 case 0x73:
1577                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1578                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1579                         tr_bank_read(op&0x1ff);
1580                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1581                         hostreg_sspreg_changed(SSP_A);
1582                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1583                         dirty_regb |= KRREG_ST;
1584                         ret++; break;
1585
1586                 // OP a, imm
1587                 case 0x14:
1588                 case 0x34:
1589                 case 0x44:
1590                 case 0x54:
1591                 case 0x64:
1592                 case 0x74:
1593                         tmpv = (op & 0xf0) >> 4;
1594                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1595                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1596                         tr_mov16(0, imm);
1597                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1598                         hostreg_sspreg_changed(SSP_A);
1599                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1600                         dirty_regb |= KRREG_ST;
1601                         ret += 2; break;
1602
1603                 // OP a, ((ri))
1604                 case 0x15:
1605                 case 0x35:
1606                 case 0x45:
1607                 case 0x55:
1608                 case 0x65:
1609                 case 0x75:
1610                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1611                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1612                         tr_rX_read2(op);
1613                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1614                         hostreg_sspreg_changed(SSP_A);
1615                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1616                         dirty_regb |= KRREG_ST;
1617                         ret += 3; break;
1618
1619                 // OP a, ri
1620                 case 0x19:
1621                 case 0x39:
1622                 case 0x49:
1623                 case 0x59:
1624                 case 0x69:
1625                 case 0x79: {
1626                         int r;
1627                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1628                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1629                         r = (op&3) | ((op>>6)&4); // src
1630                         if ((r&3) == 3) tr_unhandled();
1631
1632                         if (known_regb & (1 << (r+8))) {
1633                                 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]);  // OPs r5, r5, #val<<16
1634                         } else {
1635                                 int reg = (r < 4) ? 8 : 9;
1636                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1637                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1638                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1639                                 hostreg_r[0] = -1;
1640                         }
1641                         hostreg_sspreg_changed(SSP_A);
1642                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1643                         dirty_regb |= KRREG_ST;
1644                         ret++; break;
1645                 }
1646
1647                 // OP simm
1648                 case 0x1c:
1649                 case 0x3c:
1650                 case 0x4c:
1651                 case 0x5c:
1652                 case 0x6c:
1653                 case 0x7c:
1654                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1655                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1656                         EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff);        // OPs r5, r5, #val<<16
1657                         hostreg_sspreg_changed(SSP_A);
1658                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1659                         dirty_regb |= KRREG_ST;
1660                         ret++; break;
1661         }
1662
1663         n_in_ops++;
1664
1665         return ret;
1666 }
1667
1668 static void emit_block_prologue(void)
1669 {
1670         // check if there are enough cycles..
1671         // note: r0 must contain PC of current block
1672         EOP_CMP_IMM(11,0,0);                    // cmp r11, #0
1673         emith_jump_cond(A_COND_LE, ssp_drc_end);
1674 }
1675
1676 /* cond:
1677  * >0: direct (un)conditional jump
1678  * <0: indirect jump
1679  */
1680 static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
1681 {
1682         if (cycles > 0xff) { elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles); cycles = 0xff; }
1683         EOP_SUB_IMM(11,11,0,cycles);            // sub r11, r11, #cycles
1684
1685         if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1686                 // indirect jump, or rom -> iram jump, must use dispatcher
1687                 emith_jump(ssp_drc_next);
1688         }
1689         else if (cond == A_COND_AL) {
1690                 u32 *target = (pc < 0x400) ?
1691                         ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
1692                         ssp_block_table[pc];
1693                 if (target != NULL)
1694                         emith_jump(target);
1695                 else {
1696                         int ops = emith_jump(ssp_drc_next);
1697                         // cause the next block to be emitted over jump instruction
1698                         tcache_ptr -= ops;
1699                 }
1700         }
1701         else {
1702                 u32 *target1 = (pc     < 0x400) ?
1703                         ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
1704                         ssp_block_table[pc];
1705                 u32 *target2 = (end_pc < 0x400) ?
1706                         ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + end_pc] :
1707                         ssp_block_table[end_pc];
1708                 if (target1 != NULL)
1709                      emith_jump_cond(cond, target1);
1710                 if (target2 != NULL)
1711                      emith_jump_cond(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
1712 #ifndef __EPOC32__
1713                 // emit patchable branches
1714                 if (target1 == NULL)
1715                         emith_call_cond(cond, ssp_drc_next_patch);
1716                 if (target2 == NULL)
1717                         emith_call_cond(tr_neg_cond(cond), ssp_drc_next_patch);
1718 #else
1719                 // won't patch indirect jumps
1720                 if (target1 == NULL || target2 == NULL)
1721                         emith_jump(ssp_drc_next);
1722 #endif
1723         }
1724 }
1725
1726 void *ssp_translate_block(int pc)
1727 {
1728         unsigned int op, op1, imm, ccount = 0;
1729         unsigned int *block_start;
1730         int ret, end_cond = A_COND_AL, jump_pc = -1;
1731
1732         //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
1733
1734         block_start = tcache_ptr;
1735         known_regb = 0;
1736         dirty_regb = KRREG_P;
1737         known_regs.emu_status = 0;
1738         hostreg_clear();
1739
1740         emit_block_prologue();
1741
1742         for (; ccount < 100;)
1743         {
1744                 op = PROGRAM(pc++);
1745                 op1 = op >> 9;
1746                 imm = (u32)-1;
1747
1748                 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1749                         imm = PROGRAM(pc++); // immediate
1750
1751                 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
1752                 if (ret <= 0)
1753                 {
1754                         elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
1755                         //exit(1);
1756                 }
1757
1758                 ccount += ret & 0xffff;
1759                 if (ret & 0x10000) break;
1760         }
1761
1762         if (ccount >= 100) {
1763                 end_cond = A_COND_AL;
1764                 jump_pc = pc;
1765                 emith_move_r_imm(0, pc);
1766         }
1767
1768         tr_flush_dirty_prs();
1769         tr_flush_dirty_ST();
1770         tr_flush_dirty_pmcrs();
1771         emit_block_epilogue(ccount, end_cond, jump_pc, pc);
1772
1773         if (tcache_ptr - (u32 *)tcache > DRC_TCACHE_SIZE/4) {
1774                 elprintf(EL_ANOMALY|EL_STATUS|EL_SVP, "tcache overflow!\n");
1775                 fflush(stdout);
1776                 exit(1);
1777         }
1778
1779         // stats
1780         nblocks++;
1781         //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
1782         //      (double)(tcache_ptr - tcache) / (double)n_in_ops);
1783
1784 #ifdef DUMP_BLOCK
1785         {
1786                 FILE *f = fopen("tcache.bin", "wb");
1787                 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1788                 fclose(f);
1789         }
1790         printf("dumped tcache.bin\n");
1791         exit(0);
1792 #endif
1793
1794 #ifdef ARM
1795         cache_flush_d_inval_i(tcache, tcache_ptr);
1796 #endif
1797
1798         return block_start;
1799 }
1800
1801
1802
1803 // -----------------------------------------------------
1804
1805 static void ssp1601_state_load(void)
1806 {
1807         ssp->drc.iram_dirty = 1;
1808         ssp->drc.iram_context = 0;
1809 }
1810
1811 void ssp1601_dyn_exit(void)
1812 {
1813         free(ssp_block_table);
1814         free(ssp_block_table_iram);
1815         ssp_block_table = ssp_block_table_iram = NULL;
1816
1817         drc_cmn_cleanup();
1818 }
1819
1820 int ssp1601_dyn_startup(void)
1821 {
1822         drc_cmn_init();
1823
1824         ssp_block_table = calloc(sizeof(ssp_block_table[0]), SSP_BLOCKTAB_ENTS);
1825         if (ssp_block_table == NULL)
1826                 return -1;
1827         ssp_block_table_iram = calloc(sizeof(ssp_block_table_iram[0]), SSP_BLOCKTAB_IRAM_ENTS);
1828         if (ssp_block_table_iram == NULL) {
1829                 free(ssp_block_table);
1830                 return -1;
1831         }
1832
1833         memset(tcache, 0, DRC_TCACHE_SIZE);
1834         tcache_ptr = (void *)tcache;
1835
1836         PicoLoadStateHook = ssp1601_state_load;
1837
1838         n_in_ops = 0;
1839 #ifdef ARM
1840         // hle'd blocks
1841         ssp_block_table[0x800/2] = (void *) ssp_hle_800;
1842         ssp_block_table[0x902/2] = (void *) ssp_hle_902;
1843         ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x030/2] = (void *) ssp_hle_07_030;
1844         ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x036/2] = (void *) ssp_hle_07_036;
1845         ssp_block_table_iram[ 7 * SSP_BLOCKTAB_IRAM_ONE + 0x6d6/2] = (void *) ssp_hle_07_6d6;
1846         ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x12c/2] = (void *) ssp_hle_11_12c;
1847         ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x384/2] = (void *) ssp_hle_11_384;
1848         ssp_block_table_iram[11 * SSP_BLOCKTAB_IRAM_ONE + 0x38a/2] = (void *) ssp_hle_11_38a;
1849 #endif
1850
1851         return 0;
1852 }
1853
1854
1855 void ssp1601_dyn_reset(ssp1601_t *ssp)
1856 {
1857         ssp1601_reset(ssp);
1858         ssp->drc.iram_dirty = 1;
1859         ssp->drc.iram_context = 0;
1860         // must do this here because ssp is not available @ startup()
1861         ssp->drc.ptr_rom = (u32) Pico.rom;
1862         ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1863         ssp->drc.ptr_dram = (u32) svp->dram;
1864         ssp->drc.ptr_btable = (u32) ssp_block_table;
1865         ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
1866
1867         // prevent new versions of IRAM from appearing
1868         memset(svp->iram_rom, 0, 0x800);
1869 }
1870
1871
1872 void ssp1601_dyn_run(int cycles)
1873 {
1874         if (ssp->emu_status & SSP_WAIT_MASK) return;
1875
1876 #ifdef DUMP_BLOCK
1877         ssp_translate_block(DUMP_BLOCK >> 1);
1878 #endif
1879 #ifdef ARM
1880         ssp_drc_entry(cycles);
1881 #endif
1882 }
1883