2 @* Compiler helper functions and some SVP HLE code
3 @* (C) notaz, 2008,2009
5 @* This work is licensed under the terms of MAME license.
6 @* See COPYING file in the top-level directory.
9 #include "../../arm_features.h"
16 #define cache_flush_d_inval_i ESYM(cache_flush_d_inval_i)
17 #define ssp_get_iram_context ESYM(ssp_get_iram_context)
18 #define ssp_pm_read ESYM(ssp_pm_read)
19 #define ssp_pm_write ESYM(ssp_pm_write)
20 #define ssp_translate_block ESYM(ssp_translate_block)
21 #define tr_unhandled ESYM(tr_unhandled)
23 @ SSP_GR0, SSP_X, SSP_Y, SSP_A,
24 @ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
25 @ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
26 @ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
31 @ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
40 #define SSP_OFFS_GR 0x400
45 #define SSP_OFFS_PM_WRITE 0x46c // pmac_write[]
46 #define SSP_OFFS_EMUSTAT 0x484 // emu_status
47 #define SSP_OFFS_IRAM_ROM 0x48c // ptr_iram_rom
48 #define SSP_OFFS_DRAM 0x490 // ptr_dram
49 #define SSP_OFFS_IRAM_DIRTY 0x494
50 #define SSP_OFFS_IRAM_CTX 0x498 // iram_context
51 #define SSP_OFFS_BLTAB 0x49c // block_table
52 #define SSP_OFFS_BLTAB_IRAM 0x4a0
53 #define SSP_OFFS_TMP0 0x4a4 // for entry PC
54 #define SSP_OFFS_TMP1 0x4a8
55 #define SSP_OFFS_TMP2 0x4ac
56 #define SSP_WAIT_PM0 0x2000
59 .macro ssp_drc_do_next patch_jump=0
61 str lr, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
65 str r0, [r7, #SSP_OFFS_TMP0]
69 ldr r2, [r7, #SSP_OFFS_BLTAB]
70 ldr r2, [r2, r0, lsl #2]
77 bl ssp_translate_block
79 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
80 ldr r1, [r7, #SSP_OFFS_BLTAB]
81 str r2, [r1, r0, lsl #2]
89 ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
91 ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
92 beq 1f @ ssp_de_iram_ctx
94 bl ssp_get_iram_context
96 str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
98 str r1, [r7, #SSP_OFFS_IRAM_CTX]
99 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
101 1: @ ssp_de_iram_ctx:
102 ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
103 add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
104 add r1, r2, r0, lsl #2
112 str r1, [r7, #SSP_OFFS_TMP1]
113 bl ssp_translate_block
115 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
116 ldr r1, [r7, #SSP_OFFS_TMP1] @ &block_table_iram[iram_context][rPC]
123 .endm @ ssp_drc_do_next
126 FUNCTION(ssp_drc_entry):
127 stmfd sp!, {r4-r11, lr}
133 ldmia r2, {r3,r4,r5,r6,r8}
136 orr r4, r3, r4, lsr #16 @ XXYY
138 and r8, r8, #0x0f0000
139 mov r8, r8, lsl #13 @ sss0 *
140 and r9, r6, #0x670000
144 orrne r8, r8, #0x4 @ sss0 * NZ..
145 orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
147 ldr r8, [r7, #0x440] @ r0-r2
148 ldr r9, [r7, #0x444] @ r4-r6
149 ldr r10,[r7, #(0x400+SSP_P*4)] @ P
151 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
155 FUNCTION(ssp_drc_next):
159 FUNCTION(ssp_drc_next_patch):
163 ldr r1, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
165 moveq r3, #0xe1000000
166 orreq r3, r3, #0x00a00000 @ nop
173 streq r3, [r1, #-4] @ move the other cond up
174 moveq r3, #0xe1000000
175 orreq r3, r3, #0x00a00000
176 streq r3, [r1] @ fill it's place with nop
182 bic r3, r3, #1 @ L bit
183 orr r3, r3, r12,lsl #6
184 mov r3, r3, ror #8 @ patched branch instruction
185 str r3, [r1, #-4] @ patch the bl/b to jump directly to another handler
188 str r2, [r7, #SSP_OFFS_TMP1]
191 bl cache_flush_d_inval_i
192 ldr r2, [r7, #SSP_OFFS_TMP1]
193 ldr r0, [r7, #SSP_OFFS_TMP0]
197 FUNCTION(ssp_drc_end):
199 str r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
202 str r10,[r7, #(0x400+SSP_P*4)] @ P
203 str r8, [r7, #0x440] @ r0-r2
204 str r9, [r7, #0x444] @ r4-r6
207 and r9, r9, #(7<<16) @ STACK
209 msr cpsr_f, r3 @ to to ARM PSR
212 orrmi r6, r6, #0x80000000 @ N
213 orreq r6, r6, #0x20000000 @ Z
215 mov r3, r4, lsl #16 @ Y
217 mov r2, r2, lsl #16 @ X
220 stmia r8, {r2,r3,r5,r6,r9}
223 ldmfd sp!, {r4-r11, lr}
231 FUNCTION(ssp_hle_800):
232 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
233 ldr r1, [r7, #SSP_OFFS_EMUSTAT]
235 orreq r1, r1, #SSP_WAIT_PM0
237 streq r1, [r7, #SSP_OFFS_EMUSTAT]
244 .macro hle_flushflags
247 orr r6, r6, r1, lsr #28
251 sub r6, r6, #0x20000000
253 add r1, r1, #0x048 @ stack
254 add r1, r1, r6, lsr #28
258 FUNCTION(ssp_hle_902):
264 ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
265 add r2, r3, r0, lsl #1 @ (r7|00)
270 add r3, r3, r0, lsl #1 @ IRAM dest
271 ldrh r12,[r2], #2 @ length
272 bic r3, r3, #3 @ always seen aligned
273 @ orr r5, r5, #0x08000000
274 @ orr r5, r5, #0x00880000
275 @ sub r5, r5, r12, lsl #16
279 str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
280 sub r11,r11,r12,lsl #1
281 sub r11,r11,r12 @ -= length*3
287 orr r0, r0, r1, lsl #16
295 ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
299 strh r2, [r1] @ (r7|00)
303 orr r0, r0, #0x08000000
304 orr r0, r0, #0x001c8000
305 str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
306 str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
309 subs r11,r11,#16 @ timeslice is likely to end
314 @ this one is car rendering related
315 .macro hle_11_12c_mla offs_in
316 ldrsh r5, [r7, #(\offs_in+0)]
317 ldrsh r0, [r7, #(\offs_in+2)]
318 ldrsh r1, [r7, #(\offs_in+4)]
320 ldrsh r12,[r7, #(\offs_in+6)]
323 add r5, r5, r12,lsl #11
326 add r1, r7, r8, lsr #23
331 FUNCTION(ssp_hle_11_12c):
347 mov r2, r2, asr #15 @ (r7|00) << 1
349 mov r3, r3, asr #15 @ (r7|01) << 1
351 mov r4, r4, asr #15 @ (r7|10) << 1
368 FUNCTION(ssp_hle_11_384):
372 FUNCTION(ssp_hle_11_38a):
379 mov r2, #0 @ EFh, EEh
381 add r0, r7, #0x1c0 @ r0 (based)
387 eor r5, r5, r5, asr #31
388 add r5, r5, r5, lsr #31 @ abs(r5)
390 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
395 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
405 bpl ssp_hle_11_38x_loop
410 orr r8, r8, r0, lsr #1
416 sub r11,r11,#(9+30*4)
420 FUNCTION(ssp_hle_07_6d6):
425 and r0, r8, #0xff @ assuming alignment
426 add r0, r7, r0, lsl #1
428 mov r1, r1, lsl #16 @ 106h << 16
429 mov r2, r2, lsl #16 @ 107h << 16
434 bmi ssp_hle_07_6d6_end
440 bmi ssp_hle_07_6d6_loop
442 b ssp_hle_07_6d6_loop
449 orr r1, r2, r1, lsr #16
456 FUNCTION(ssp_hle_07_030):
459 orr r0, r0, r0, lsr #16
463 FUNCTION(ssp_hle_07_036):
464 ldr r1, [r7, #0x1e0] @ F1h F0h
465 rsb r5, r1, r1, lsr #16
466 mov r5, r5, lsl #16 @ AL not needed
469 bmi hle_07_036_ending2
470 ldr r1, [r7, #0x1dc] @ EEh
477 strh r0, [r1, #0xea] @ F5h
478 ldr r0, [r7, #0x1e0] @ F0h
480 strh r0, [r1, #0xf0] @ F8h
481 add r2, r0, #0xc0 @ r2
482 add r2, r7, r2, lsl #1
488 @ will handle PMC later
489 ldr r0, [r7, #0x1e8] @ F5h << 16
490 ldr r1, [r7, #0x1f0] @ F8h
491 ldr r2, [r7, #0x1d4] @ EAh
493 add r0, r0, r1, lsl #16
494 sub r0, r2, r0, asr #18
496 rsbs r0, r0, #0x78 @ length
497 ble hle_07_036_ending1
502 ldr r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
503 ldr r2, [r7, #SSP_OFFS_DRAM]
505 add r1, r2, r1, lsr #15 @ addr (based)
506 ldrh r2, [r7, #0] @ pattern
507 ldrh r3, [r7, #6] @ mode
512 subsne r12,r12,#0x0400
515 orr r2, r2, r2, lsl #16
521 strhne r2, [r1], #0x3e @ align
534 strne r2, [r1], #0x40
537 b hle_07_036_end_copy
541 orreq r12,r12,#0x000f
543 orreq r12,r12,#0x00f0
545 orreq r12,r12,#0x0f00
547 orreq r12,r12,#0xf000
548 orrs r12,r12,r12,lsl #16
549 beq hle_07_036_no_ovrwr
556 strh r3, [r1], #0x3e @ align
579 ldr r2, [r7, #SSP_OFFS_DRAM]
581 sub r0, r1, r2 @ new addr
583 strh r0, [r3, #(0x6c+4*4)] @ SSP_OFFS_PM_WRITE+4*4 (low)
586 ldr r0, [r7, #0x1e0] @ F1h << 16
589 add r0, r0, #(0xc4<<16)
590 bic r8, r8, #0xff0000
592 add r0, r7, r0, lsr #15
598 ldr r1, [r7, #4] @ new mode
600 strh r1, [r2, #(0x6c+4*4+2)] @ SSP_OFFS_PM_WRITE+4*4 (high)
614 b ssp_drc_next @ let the dispatcher finish this
616 @ vim:filetype=armasm