1 /***************************************************************************************
3 * CD data controller (LC89510 compatible)
5 * Copyright (C) 2012 Eke-Eke (Genesis Plus GX)
7 * Redistribution and use of this code or any derivative works are permitted
8 * provided that the following conditions are met:
10 * - Redistributions may not be sold, nor may they be used in a commercial
11 * product or activity.
13 * - Redistributions that are modified from the original source must include the
14 * complete source code, including the source code for all components used by a
15 * binary built from the modified sources. However, as a special exception, the
16 * source code distributed need not include anything that is normally distributed
17 * (in either source or binary form) with the major components (compiler, kernel,
18 * and so on) of the operating system on which the executable runs, unless that
19 * component itself accompanies the executable.
21 * - Redistributions must reproduce the above copyright notice, this list of
22 * conditions and the following disclaimer in the documentation and/or other
23 * materials provided with the distribution.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
37 ****************************************************************************************/
39 #include "../pico_int.h"
40 #include "genplus_macros.h"
42 /* IFSTAT register bitmasks */
45 #define BIT_DTBSY 0x08
48 /* IFCTRL register bitmasks */
49 #define BIT_DTEIEN 0x40
50 #define BIT_DECIEN 0x20
51 #define BIT_DOUTEN 0x02
53 /* CTRL0 register bitmasks */
54 #define BIT_DECEN 0x80
55 #define BIT_E01RQ 0x20
56 #define BIT_AUTORQ 0x10
59 /* CTRL1 register bitmasks */
60 #define BIT_MODRQ 0x08
61 #define BIT_FORMRQ 0x04
62 #define BIT_SHDREN 0x01
64 /* CTRL2 register bitmask */
65 #define BIT_VALST 0x80
67 /* PicoDrive: doing DMA at once, not using callbacks */
68 //#define DMA_BYTES_PER_LINE 512
69 #define DMA_CYCLES_PER_BYTE 4 // or 6?
74 word_ram_2M_dma_w = 3,
92 //void (*dma_w)(unsigned int words);
94 uint8 ram[0x4000 + 2352]; /* 16K external RAM (with one block overhead to handle buffer overrun) */
101 memset(&cdc, 0, sizeof(cdc_t));
106 /* reset CDC register index */
107 Pico_mcd->s68k_regs[0x04+1] = 0x00;
109 /* reset CDC registers */
118 cdc.head[0][0] = 0x00;
119 cdc.head[0][1] = 0x00;
120 cdc.head[0][2] = 0x00;
121 cdc.head[0][3] = 0x01;
122 cdc.head[1][0] = 0x00;
123 cdc.head[1][1] = 0x00;
124 cdc.head[1][2] = 0x00;
125 cdc.head[1][3] = 0x00;
127 /* reset CDC cycle counter */
128 cdc.cycles = SekCyclesDoneS68k();
130 /* DMA transfer disabled */
134 int cdc_context_save(uint8 *state)
139 if (cdc.dma_w == pcm_ram_dma_w)
143 else if (cdc.dma_w == prg_ram_dma_w)
147 else if (cdc.dma_w == word_ram_0_dma_w)
151 else if (cdc.dma_w == word_ram_1_dma_w)
155 else if (cdc.dma_w == word_ram_2M_dma_w)
164 save_param(&cdc, sizeof(cdc));
165 save_param(&tmp8, 1);
170 int cdc_context_load(uint8 *state)
175 load_param(&cdc, sizeof(cdc));
176 load_param(&tmp8, 1);
181 cdc.dma_w = pcm_ram_dma_w;
184 cdc.dma_w = prg_ram_dma_w;
187 cdc.dma_w = word_ram_0_dma_w;
190 cdc.dma_w = word_ram_1_dma_w;
193 cdc.dma_w = word_ram_2M_dma_w;
203 int cdc_context_load_old(uint8 *state)
205 #define old_load(v, ofs) \
206 memcpy(&cdc.v, state + ofs, sizeof(cdc.v))
208 memcpy(cdc.ram, state, 0x4000);
209 old_load(ifstat, 67892);
210 old_load(ifctrl, 67924);
211 old_load(dbc, 67896);
212 old_load(dac, 67900);
215 old_load(ctrl, 67928);
216 old_load(head[0], 67904);
217 old_load(stat, 67916);
220 switch (Pico_mcd->s68k_regs[0x04+0] & 0x07)
222 case 4: /* PCM RAM DMA */
223 cdc.dma_w = pcm_ram_dma_w;
225 case 5: /* PRG-RAM DMA */
226 cdc.dma_w = prg_ram_dma_w;
228 case 7: /* WORD-RAM DMA */
229 if (Pico_mcd->s68k_regs[0x02+1] & 0x04)
231 if (Pico_mcd->s68k_regs[0x02+1] & 0x01)
232 cdc.dma_w = word_ram_0_dma_w;
234 cdc.dma_w = word_ram_1_dma_w;
238 if (Pico_mcd->s68k_regs[0x02+1] & 0x02)
239 cdc.dma_w = word_ram_2M_dma_w;
244 return 0x10960; // sizeof(old_cdc)
248 static int check_decoder_irq_pending(void)
250 /* As per mcd-verificator, DECI is active for a phase of 49:72 per sector */
251 /* 12500000/75 * 49/(49+72) = ~67500, but it sometimes fails with that */
252 if (CYCLES_GE(SekCyclesDoneS68k(), cdc.cycles + 67250))
253 cdc.ifstat |= BIT_DECI;
255 return !(cdc.ifstat & BIT_DECI) && (cdc.ifctrl & BIT_DECIEN);
258 static void do_dma(enum dma_type type, int bytes_in)
260 int dma_addr = (Pico_mcd->s68k_regs[0x0a] << 8) | Pico_mcd->s68k_regs[0x0b];
261 int src_addr = cdc.dac & 0x3ffe;
262 int dst_addr = dma_addr;
263 int bytes = bytes_in;
264 int words = bytes_in >> 1;
269 elprintf(EL_CD, "dma %d %04x->%04x %x",
270 type, cdc.dac, dst_addr, bytes_in);
275 dst_addr = (dst_addr << 2) & 0xffc;
276 if (dst_addr + bytes > 0x1000) {
277 elprintf(EL_ANOMALY, "pcm dma oflow: %x %x", dst_addr, words);
278 bytes = 0x1000 - dst_addr;
280 dst = Pico_mcd->pcm_ram_b[Pico_mcd->pcm.bank];
281 dst = dst + dst_addr;
284 if (src_addr + bytes > 0x4000) {
285 len = 0x4000 - src_addr;
286 memcpy(dst, cdc.ram + src_addr, len);
292 memcpy(dst, cdc.ram + src_addr, bytes);
299 dst = Pico_mcd->prg_ram + dst_addr;
303 case word_ram_0_dma_w:
304 dst_addr = (dst_addr << 3) & 0x1fffe;
305 dst = Pico_mcd->word_ram1M[0] + dst_addr;
309 case word_ram_1_dma_w:
310 dst_addr = (dst_addr << 3) & 0x1fffe;
311 dst = Pico_mcd->word_ram1M[1] + dst_addr;
315 case word_ram_2M_dma_w:
316 dst_addr = (dst_addr << 3) & 0x3fffe;
317 dst = Pico_mcd->word_ram2M + dst_addr;
322 elprintf(EL_ANOMALY, "invalid dma: %d", type);
326 if (dst_addr + words * 2 > dst_limit) {
327 elprintf(EL_ANOMALY, "cd dma %d oflow: %x %x", type, dst_addr, words);
328 words = (dst_limit - dst_addr) / 2;
332 if (src_addr + words * 2 > 0x4000) {
333 len = 0x4000 - src_addr;
334 memcpy16bswap((void *)dst, cdc.ram + src_addr, len / 2);
340 memcpy16bswap((void *)dst, cdc.ram + src_addr, words);
344 bytes_in &= ~1; // Todo leftover byte?
347 /* update DMA addresses */
349 if (type == pcm_ram_dma_w)
350 dma_addr += bytes_in >> 2;
352 dma_addr += bytes_in >> 3;
354 Pico_mcd->s68k_regs[0x0a] = dma_addr >> 8;
355 Pico_mcd->s68k_regs[0x0b] = dma_addr;
358 void cdc_dma_update(void)
360 /* end of DMA transfer ? */
361 //if (cdc.dbc < DMA_BYTES_PER_LINE)
363 /* transfer remaining words using 16-bit DMA */
364 //cdc.dma_w((cdc.dbc + 1) >> 1);
365 do_dma(cdc.dma_w, cdc.dbc + 1);
367 /* reset data byte counter (DBCH bits 4-7 should be set to 1) */
370 /* clear !DTEN and !DTBSY */
371 cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
373 /* clear DSR bit & set EDT bit (SCD register $04) */
374 Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80;
376 if (cdc.ifstat & BIT_DTEI) {
377 /* pending Data Transfer End interrupt */
378 cdc.ifstat &= ~BIT_DTEI;
380 /* Data Transfer End interrupt enabled ? */
381 if (!check_decoder_irq_pending() && (cdc.ifctrl & BIT_DTEIEN))
383 /* level 5 interrupt enabled ? */
384 if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
386 /* update IRQ level */
387 elprintf(EL_INTS, "cdc DTE irq 5");
393 /* disable DMA transfer */
399 /* transfer all words using 16-bit DMA */
400 cdc.dma_w(DMA_BYTES_PER_LINE >> 1);
402 /* decrement data byte counter */
408 int cdc_decoder_update(uint8 header[4])
410 /* data decoding enabled ? */
411 if (cdc.ctrl[0] & BIT_DECEN)
413 /* update HEAD registers */
414 memcpy(cdc.head[0], header, sizeof(cdc.head[0]));
420 cdc.stat[0] = BIT_DECEN;
422 /* pending decoder interrupt */
423 cdc.ifstat &= ~BIT_DECI;
424 cdc.cycles = SekCyclesDoneS68k();
426 /* decoder interrupt enabled ? */
427 if (((cdc.ifstat & BIT_DTEI) || !(cdc.ifctrl & BIT_DTEIEN)) && (cdc.ifctrl & BIT_DECIEN))
429 /* level 5 interrupt enabled ? */
430 if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
432 /* update IRQ level */
433 elprintf(EL_INTS, "cdc DEC irq 5");
438 /* buffer RAM write enabled ? */
439 if (cdc.ctrl[0] & BIT_WRRQ)
443 /* increment block pointer */
446 /* increment write address */
449 /* CDC buffer address */
450 offset = cdc.pt & 0x3fff;
452 /* write CDD block header (4 bytes) */
453 memcpy(cdc.ram + offset, header, 4);
455 /* write CDD block data (2048 bytes) */
456 cdd_read_data(cdc.ram + 4 + offset);
458 /* take care of buffer overrun */
459 if (offset > (0x4000 - 2048 - 4))
461 /* data should be written at the start of buffer */
462 memcpy(cdc.ram, cdc.ram + 0x4000, offset + 2048 + 4 - 0x4000);
465 /* read next data block */
470 /* keep decoding same data block if Buffer Write is disabled */
474 void cdc_reg_w(unsigned char data)
477 elprintf(EL_STATUS, "CDC register %X write 0x%04x", Pico_mcd->s68k_regs[0x04+1] & 0x0F, data);
479 switch (Pico_mcd->s68k_regs[0x04+1] & 0x1F)
484 case 0x01: /* IFCTRL */
486 /* pending interrupts ? */
487 check_decoder_irq_pending();
488 if (((data & BIT_DTEIEN) && !(cdc.ifstat & BIT_DTEI)) ||
489 ((data & BIT_DECIEN) && !(cdc.ifstat & BIT_DECI)))
491 /* level 5 interrupt enabled ? */
492 if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
494 /* update IRQ level */
495 elprintf(EL_INTS, "cdc pending irq 5");
499 else // if (scd.pending & (1 << 5))
501 /* clear pending level 5 interrupts */
505 /* abort any data transfer if data output is disabled */
506 if (!(data & BIT_DOUTEN))
508 /* clear !DTBSY and !DTEN */
509 cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
513 Pico_mcd->s68k_regs[0x04+1] = 0x02;
517 case 0x02: /* DBCL */
520 Pico_mcd->s68k_regs[0x04+1] = 0x03;
523 case 0x03: /* DBCH */
525 cdc.dbc |= (data & 0x0f) << 8;
526 Pico_mcd->s68k_regs[0x04+1] = 0x04;
529 case 0x04: /* DACL */
532 Pico_mcd->s68k_regs[0x04+1] = 0x05;
535 case 0x05: /* DACH */
537 cdc.dac |= data << 8;
538 Pico_mcd->s68k_regs[0x04+1] = 0x06;
541 case 0x06: /* DTRG */
543 /* start data transfer if data output is enabled */
544 if (cdc.ifctrl & BIT_DOUTEN)
547 cdc.ifstat &= ~BIT_DTBSY;
549 /* clear DBCH bits 4-7 */
552 /* clear EDT & DSR bits (SCD register $04) */
553 Pico_mcd->s68k_regs[0x04+0] &= 0x07;
557 /* setup data transfer destination */
558 switch (Pico_mcd->s68k_regs[0x04+0] & 0x07)
560 case 2: /* MAIN-CPU host read */
561 case 3: /* SUB-CPU host read */
564 cdc.ifstat &= ~BIT_DTEN;
566 /* set DSR bit (register $04) */
567 Pico_mcd->s68k_regs[0x04+0] |= 0x40;
571 case 4: /* PCM RAM DMA */
573 cdc.dma_w = pcm_ram_dma_w;
577 case 5: /* PRG-RAM DMA */
579 cdc.dma_w = prg_ram_dma_w;
583 case 7: /* WORD-RAM DMA */
585 /* check memory mode */
586 if (Pico_mcd->s68k_regs[0x02+1] & 0x04)
589 if (Pico_mcd->s68k_regs[0x02+1] & 0x01)
591 /* Word-RAM bank 0 is assigned to SUB-CPU */
592 cdc.dma_w = word_ram_0_dma_w;
596 /* Word-RAM bank 1 is assigned to SUB-CPU */
597 cdc.dma_w = word_ram_1_dma_w;
603 if (Pico_mcd->s68k_regs[0x02+1] & 0x02)
605 /* only process DMA if Word-RAM is assigned to SUB-CPU */
606 cdc.dma_w = word_ram_2M_dma_w;
612 default: /* invalid */
614 elprintf(EL_ANOMALY, "invalid CDC tranfer destination (%d)",
615 Pico_mcd->s68k_regs[0x04+0] & 0x07);
621 pcd_event_schedule_s68k(PCD_EVENT_DMA, cdc.dbc * DMA_CYCLES_PER_BYTE);
624 Pico_mcd->s68k_regs[0x04+1] = 0x07;
628 case 0x07: /* DTACK */
630 /* clear pending data transfer end interrupt */
631 cdc.ifstat |= BIT_DTEI;
633 /* clear DBCH bits 4-7 */
636 /* no pending decoder interrupt ? */
637 if (!check_decoder_irq_pending())
639 /* clear pending level 5 interrupt */
643 Pico_mcd->s68k_regs[0x04+1] = 0x08;
650 Pico_mcd->s68k_regs[0x04+1] = 0x09;
656 Pico_mcd->s68k_regs[0x04+1] = 0x0a;
659 case 0x0a: /* CTRL0 */
661 /* reset DECI if decoder turned off */
662 if (!(data & BIT_DECEN)) {
663 cdc.ifstat |= BIT_DECI;
665 if ((cdc.ifstat & BIT_DTEI) || !(cdc.ifctrl & BIT_DTEIEN))
667 /* clear pending level 5 interrupt */
672 /* update decoding mode */
673 if (data & BIT_AUTORQ)
675 /* set MODE bit according to CTRL1 register & clear FORM bit */
676 cdc.stat[2] = cdc.ctrl[1] & BIT_MODRQ;
680 /* set MODE & FORM bits according to CTRL1 register */
681 cdc.stat[2] = cdc.ctrl[1] & (BIT_MODRQ | BIT_FORMRQ);
685 Pico_mcd->s68k_regs[0x04+1] = 0x0b;
689 case 0x0b: /* CTRL1 */
691 /* update decoding mode */
692 if (cdc.ctrl[0] & BIT_AUTORQ)
694 /* set MODE bit according to CTRL1 register & clear FORM bit */
695 cdc.stat[2] = data & BIT_MODRQ;
699 /* set MODE & FORM bits according to CTRL1 register */
700 cdc.stat[2] = data & (BIT_MODRQ | BIT_FORMRQ);
704 Pico_mcd->s68k_regs[0x04+1] = 0x0c;
711 Pico_mcd->s68k_regs[0x04+1] = 0x0d;
717 Pico_mcd->s68k_regs[0x04+1] = 0x0e;
720 case 0x0e: /* CTRL2 (unused) */
721 Pico_mcd->s68k_regs[0x04+1] = 0x0f;
724 case 0x0f: /* RESET */
728 default: /* by default, SBOUT is not used */
729 Pico_mcd->s68k_regs[0x04+1] = (Pico_mcd->s68k_regs[0x04+1] + 1) & 0x1f;
734 unsigned char cdc_reg_r(void)
736 switch (Pico_mcd->s68k_regs[0x04+1] & 0x1F)
741 case 0x01: /* IFSTAT */
742 Pico_mcd->s68k_regs[0x04+1] = 0x02;
743 check_decoder_irq_pending();
746 case 0x02: /* DBCL */
747 Pico_mcd->s68k_regs[0x04+1] = 0x03;
748 return cdc.dbc & 0xff;
750 case 0x03: /* DBCH */
751 Pico_mcd->s68k_regs[0x04+1] = 0x04;
752 return (cdc.dbc >> 8) & 0xff;
754 case 0x04: /* HEAD0 */
755 Pico_mcd->s68k_regs[0x04+1] = 0x05;
756 return cdc.head[cdc.ctrl[1] & BIT_SHDREN][0];
758 case 0x05: /* HEAD1 */
759 Pico_mcd->s68k_regs[0x04+1] = 0x06;
760 return cdc.head[cdc.ctrl[1] & BIT_SHDREN][1];
762 case 0x06: /* HEAD2 */
763 Pico_mcd->s68k_regs[0x04+1] = 0x07;
764 return cdc.head[cdc.ctrl[1] & BIT_SHDREN][2];
766 case 0x07: /* HEAD3 */
767 Pico_mcd->s68k_regs[0x04+1] = 0x08;
768 return cdc.head[cdc.ctrl[1] & BIT_SHDREN][3];
771 Pico_mcd->s68k_regs[0x04+1] = 0x09;
772 return cdc.pt & 0xff;
775 Pico_mcd->s68k_regs[0x04+1] = 0x0a;
776 return (cdc.pt >> 8) & 0xff;
779 Pico_mcd->s68k_regs[0x04+1] = 0x0b;
780 return cdc.wa & 0xff;
783 Pico_mcd->s68k_regs[0x04+1] = 0x0c;
784 return (cdc.wa >> 8) & 0xff;
786 case 0x0c: /* STAT0 */
787 Pico_mcd->s68k_regs[0x04+1] = 0x0d;
790 case 0x0d: /* STAT1 (always return 0) */
791 Pico_mcd->s68k_regs[0x04+1] = 0x0e;
794 case 0x0e: /* STAT2 */
795 Pico_mcd->s68k_regs[0x04+1] = 0x0f;
798 case 0x0f: /* STAT3 */
800 uint8 data = cdc.stat[3];
802 /* clear !VALST (note: this is not 100% correct but BIOS do not seem to care) */
803 cdc.stat[3] = BIT_VALST;
805 /* clear pending decoder interrupt */
806 cdc.ifstat |= BIT_DECI;
808 /* no pending data transfer end interrupt */
809 if ((cdc.ifstat & BIT_DTEI) || !(cdc.ifctrl & BIT_DTEIEN))
811 /* clear pending level 5 interrupt */
815 Pico_mcd->s68k_regs[0x04+1] = 0x10;
819 default: /* by default, COMIN is always empty */
820 Pico_mcd->s68k_regs[0x04+1] = (Pico_mcd->s68k_regs[0x04+1] + 1) & 0x1f;
825 unsigned short cdc_host_r(int sub)
827 int dir = Pico_mcd->s68k_regs[0x04+0] & 0x07;
829 /* sync sub cpu if DSR bit not there (yet?) on main cpu */
830 if (!(Pico_mcd->s68k_regs[0x04+0] & 0x40))
831 if (!sub) pcd_sync_s68k(SekCyclesDone()+8, 0); /* HACK, mcd-verificator */
833 /* check if data is available */
834 if (!(cdc.ifstat & BIT_DTEN))
836 /* read data word from CDC RAM buffer */
837 uint8 *datap = cdc.ram + (cdc.dac & 0x3ffe);
838 uint16 data = (datap[0] << 8) | datap[1];
841 error("CDC host read 0x%04x -> 0x%04x (dbc=0x%x) (%X)\n", cdc.dac, data, cdc.dbc, s68k.pc);
844 /* only the configured cpu access advances the DMA */
845 if ((sub && dir != 3) || (!sub && dir != 2))
848 /* increment data address counter */
851 /* decrement data byte counter */
854 /* end of transfer ? */
855 if ((int16)cdc.dbc <= 0)
857 /* reset data byte counter (DBCH bits 4-7 should be set to 1) */
860 /* clear !DTEN and !DTBSY */
861 cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
863 /* clear DSR bit & set EDT bit (SCD register $04) */
864 Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0x80;
866 } else if ((int16)cdc.dbc <= 2)
868 if (cdc.ifstat & BIT_DTEI) {
869 /* pending Data Transfer End interrupt */
870 cdc.ifstat &= ~BIT_DTEI;
872 /* Data Transfer End interrupt enabled ? */
873 if (!check_decoder_irq_pending() && (cdc.ifctrl & BIT_DTEIEN))
875 /* level 5 interrupt enabled ? */
876 if (Pico_mcd->s68k_regs[0x32+1] & PCDS_IEN5)
878 /* update IRQ level */
879 elprintf(EL_INTS, "cdc DTE irq 5");
884 /* set DSR and EDT bit (SCD register $04) */
885 Pico_mcd->s68k_regs[0x04+0] = (Pico_mcd->s68k_regs[0x04+0] & 0x07) | 0xc0;
892 error("error reading CDC host (data transfer disabled)\n");
897 // vim:shiftwidth=2:ts=2:expandtab