2 * PicoDrive - Internal Header File
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3 * (c) Copyright Dave, 2004
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4 * (C) notaz, 2006-2010
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6 * This work is licensed under the terms of MAME license.
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7 * See COPYING file in the top-level directory.
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10 #ifndef PICO_INTERNAL_INCLUDED
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11 #define PICO_INTERNAL_INCLUDED
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17 #include "carthw/carthw.h"
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20 #define USE_POLL_DETECT
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22 #ifndef PICO_INTERNAL
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23 #define PICO_INTERNAL
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25 #ifndef PICO_INTERNAL_ASM
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26 #define PICO_INTERNAL_ASM
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29 // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project
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36 // ----------------------- 68000 CPU -----------------------
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38 #include "../cpu/cyclone/Cyclone.h"
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39 extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;
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40 #define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run
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41 #define SekCyclesLeft \
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42 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)
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43 #define SekCyclesLeftS68k \
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44 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)
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45 #define SekEndTimeslice(after) PicoCpuCM68k.cycles=after
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46 #define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after
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47 #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)
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48 #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)
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49 #define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])
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50 #define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])
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51 #define SekSr CycloneGetSr(&PicoCpuCM68k)
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52 #define SekSrS68k CycloneGetSr(&PicoCpuCS68k)
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53 #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }
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54 #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }
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55 #define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)
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56 #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)
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57 #define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))
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59 #define SekInterrupt(i) PicoCpuCM68k.irq=i
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60 #define SekIrqLevel PicoCpuCM68k.irq
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63 #define EMU_CORE_DEBUG
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68 #include "../cpu/fame/fame.h"
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69 extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;
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70 #define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter
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71 #define SekCyclesLeft \
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72 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)
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73 #define SekCyclesLeftS68k \
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74 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)
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75 #define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after
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76 #define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after
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77 #define SekPc fm68k_get_pc(&PicoCpuFM68k)
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78 #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)
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79 #define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)
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80 #define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)
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81 #define SekSr PicoCpuFM68k.sr
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82 #define SekSrS68k PicoCpuFS68k.sr
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83 #define SekSetStop(x) { \
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84 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \
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85 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \
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87 #define SekSetStopS68k(x) { \
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88 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \
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89 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \
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91 #define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)
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92 #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)
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93 #define SekShouldInterrupt fm68k_would_interrupt()
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95 #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq
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96 #define SekIrqLevel PicoCpuFM68k.interrupts[0]
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99 #define EMU_CORE_DEBUG
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104 #include "../cpu/musashi/m68kcpu.h"
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105 extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
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106 #ifndef SekCyclesLeft
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107 #define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles
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108 #define SekCyclesLeft \
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109 (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)
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110 #define SekCyclesLeftS68k \
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111 ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)
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112 #define SekEndTimeslice(after) SET_CYCLES(after)
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113 #define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after
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114 #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)
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115 #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)
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116 #define SekDar(x) PicoCpuMM68k.dar[x]
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117 #define SekDarS68k(x) PicoCpuMS68k.dar[x]
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118 #define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)
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119 #define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)
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120 #define SekSetStop(x) { \
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121 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \
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122 else PicoCpuMM68k.stopped=0; \
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124 #define SekSetStopS68k(x) { \
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125 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \
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126 else PicoCpuMS68k.stopped=0; \
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128 #define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)
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129 #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)
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130 #define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)
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132 #define SekInterrupt(irq) { \
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133 void *oldcontext = m68ki_cpu_p; \
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134 m68k_set_context(&PicoCpuMM68k); \
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135 m68k_set_irq(irq); \
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136 m68k_set_context(oldcontext); \
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138 #define SekIrqLevel (PicoCpuMM68k.int_level >> 8)
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143 extern int SekCycleCnt; // cycles done in this frame
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144 extern int SekCycleAim; // cycle aim
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145 extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame
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147 #define SekCyclesReset() { \
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148 SekCycleCntT+=SekCycleAim; \
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149 SekCycleCnt-=SekCycleAim; \
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152 #define SekCyclesBurn(c) SekCycleCnt+=c
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153 #define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)
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154 #define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom
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155 #define SekCyclesDoneT2() (SekCycleCntT + SekCycleCnt) // same as above but not from memhandlers
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157 #define SekEndRun(after) { \
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158 SekCycleCnt -= SekCyclesLeft - (after); \
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159 if (SekCycleCnt < 0) SekCycleCnt = 0; \
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160 SekEndTimeslice(after); \
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163 #define SekEndRunS68k(after) { \
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164 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \
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165 if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \
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166 SekEndTimesliceS68k(after); \
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169 extern int SekCycleCntS68k;
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170 extern int SekCycleAimS68k;
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172 #define SekCyclesResetS68k() { \
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173 SekCycleCntS68k-=SekCycleAimS68k; \
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174 SekCycleAimS68k=0; \
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176 #define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)
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178 #ifdef EMU_CORE_DEBUG
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179 extern int dbg_irq_level;
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180 #undef SekEndTimeslice
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181 #undef SekCyclesBurn
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183 #undef SekInterrupt
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184 #define SekEndTimeslice(c)
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185 #define SekCyclesBurn(c) c
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186 #define SekEndRun(c)
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187 #define SekInterrupt(irq) dbg_irq_level=irq
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190 // ----------------------- Z80 CPU -----------------------
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192 #if defined(_USE_DRZ80)
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193 #include "../cpu/DrZ80/drz80.h"
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195 extern struct DrZ80 drZ80;
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197 #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))
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198 #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)
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199 #define z80_int() drZ80.Z80_IRQ = 1
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201 #define z80_cyclesLeft drZ80.cycles
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202 #define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)
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204 #elif defined(_USE_CZ80)
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205 #include "../cpu/cz80/cz80.h"
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207 #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)
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208 #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)
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209 #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)
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211 #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)
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212 #define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)
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216 #define z80_run(cycles) (cycles)
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217 #define z80_run_nr(cycles)
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222 #define Z80_STATE_SIZE 0x60
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224 extern int z80stopCycle; /* in 68k cycles */
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225 extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */
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226 extern int z80_cycle_aim;
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227 extern int z80_scanline;
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228 extern int z80_scanline_cycles; /* cycles done until z80_scanline */
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230 #define z80_resetCycles() \
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231 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;
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233 #define z80_cyclesDone() \
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234 (z80_cycle_aim - z80_cyclesLeft)
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236 #define cycles_68k_to_z80(x) ((x)*957 >> 11)
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238 // ----------------------- SH2 CPU -----------------------
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240 #include "cpu/sh2/sh2.h"
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242 extern SH2 sh2s[2];
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243 #define msh2 sh2s[0]
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244 #define ssh2 sh2s[1]
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247 # define sh2_end_run(sh2, after_) do { \
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248 if ((sh2)->icount > (after_)) { \
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249 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \
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250 (sh2)->icount = after_; \
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253 # define sh2_cycles_left(sh2) (sh2)->icount
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254 # define sh2_burn_cycles(sh2, n) (sh2)->icount -= n
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255 # define sh2_pc(sh2) (sh2)->ppc
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257 # define sh2_end_run(sh2, after_) do { \
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258 int left_ = (signed int)(sh2)->sr >> 12; \
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259 if (left_ > (after_)) { \
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260 (sh2)->cycles_timeslice -= left_ - (after_); \
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261 (sh2)->sr &= 0xfff; \
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262 (sh2)->sr |= (after_) << 12; \
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265 # define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)
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266 # define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)
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267 # define sh2_pc(sh2) (sh2)->pc
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270 #define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))
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271 #define sh2_cycles_done_t(sh2) \
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272 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))
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273 #define sh2_cycles_done_m68k(sh2) \
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274 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))
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276 #define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]
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277 #define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr
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278 #define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr
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279 #define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)
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281 #define sh2_set_gbr(c, v) \
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282 { if (c) ssh2.gbr = v; else msh2.gbr = v; }
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283 #define sh2_set_vbr(c, v) \
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284 { if (c) ssh2.vbr = v; else msh2.vbr = v; }
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286 #define elprintf_sh2(sh2, w, f, ...) \
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287 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)
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289 // ---------------------------------------------------------
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291 // main oscillator clock which controls timing
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292 #define OSC_NTSC 53693100
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293 #define OSC_PAL 53203424
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297 unsigned char reg[0x20];
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298 unsigned int command; // 32-bit Command
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299 unsigned char pending; // 1 if waiting for second half of 32-bit command
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300 unsigned char type; // Command type (v/c/vsram read/write)
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301 unsigned short addr; // Read/Write address
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302 int status; // Status bits
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303 unsigned char pending_ints; // pending interrupts: ??VH????
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304 signed char lwrite_cnt; // VDP write count during active display line
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305 unsigned short v_counter; // V-counter
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306 unsigned char pad[0x10];
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311 unsigned char rotate;
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312 unsigned char z80Run;
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313 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches
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314 unsigned short scanline; // 04 0 to 261||311
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315 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)
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316 unsigned char hardware; // 07 Hardware value for country
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317 unsigned char pal; // 08 1=PAL 0=NTSC
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318 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below
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319 unsigned short z80_bank68k; // 0a
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320 unsigned short pad0;
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321 unsigned char pad1;
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322 unsigned char z80_reset; // 0f z80 reset held
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323 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay
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324 unsigned short eeprom_addr; // EEPROM address register
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325 unsigned char eeprom_cycle; // EEPROM cycle number
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326 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs
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327 unsigned char eeprom_status;
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328 unsigned char pad2;
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329 unsigned short dma_xfers; // 18
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330 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer
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331 unsigned int frame_count; // 1c for movies and idle det
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336 unsigned char carthw[0x10];
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337 unsigned char io_ctl;
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338 unsigned char pad[0x4f];
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341 // some assembly stuff depend on these, do not touch!
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344 unsigned char ram[0x10000]; // 0x00000 scratch ram
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345 union { // vram is byteswapped for easier reads when drawing
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346 unsigned short vram[0x8000]; // 0x10000
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347 unsigned char vramb[0x4000]; // VRAM in SMS mode
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349 unsigned char zram[0x2000]; // 0x20000 Z80 ram
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350 unsigned char ioports[0x10]; // XXX: fix asm and mv
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351 unsigned char pad[0xf0]; // unused
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352 unsigned short cram[0x40]; // 0x22100
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353 unsigned short vsram[0x40]; // 0x22180
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355 unsigned char *rom; // 0x22200
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356 unsigned int romsize; // 0x22204
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359 struct PicoVideo video;
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364 #define SRR_MAPPED (1 << 0)
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365 #define SRR_READONLY (1 << 1)
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367 #define SRF_ENABLED (1 << 0)
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368 #define SRF_EEPROM (1 << 1)
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372 unsigned char *data; // actual data
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373 unsigned int start; // start address in 68k address space
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375 unsigned char flags; // 0c: SRF_*
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376 unsigned char unused2;
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377 unsigned char changed;
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378 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words
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379 unsigned char unused3;
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380 unsigned char eeprom_bit_cl; // bit number for cl
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381 unsigned char eeprom_bit_in; // bit number for in
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382 unsigned char eeprom_bit_out; // bit number for out
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387 #include "cd/cd_sys.h"
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388 #include "cd/LC89510.h"
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389 #include "cd/gfx_cd.h"
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393 unsigned char control; // reg7
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394 unsigned char enabled; // reg8
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395 unsigned char cur_ch;
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396 unsigned char bank;
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399 struct pcm_chan // 08, size 0x10
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401 unsigned char regs[8];
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402 unsigned int addr; // .08: played sample address
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409 unsigned short hint_vector;
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410 unsigned char busreq;
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411 unsigned char s68k_pend_ints;
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412 unsigned int state_flags; // 04: emu state: reset_pending
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413 unsigned int counter75hz;
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415 int timer_int3; // 10
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416 unsigned int timer_stopwatch;
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417 unsigned char bcram_reg; // 18: battery-backed RAM cart register
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418 unsigned char pad2;
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419 unsigned short pad3;
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425 unsigned char bios[0x20000]; // 000000: 128K
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426 union { // 020000: 512K
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427 unsigned char prg_ram[0x80000];
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428 unsigned char prg_ram_b[4][0x20000];
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430 union { // 0a0000: 256K
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432 unsigned char word_ram2M[0x40000];
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433 unsigned char unused0[0x20000];
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436 unsigned char unused1[0x20000];
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437 unsigned char word_ram1M[2][0x20000];
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440 union { // 100000: 64K
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441 unsigned char pcm_ram[0x10000];
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442 unsigned char pcm_ram_b[0x10][0x1000];
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444 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs
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445 unsigned char bram[0x2000]; // 110200: 8K
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446 struct mcd_misc m; // 112200: misc
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447 struct mcd_pcm pcm; // 112240:
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448 _scd_toc TOC; // not to be saved
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455 // XXX: this will need to be reworked for cart+cd support.
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456 #define Pico_mcd ((mcd_state *)Pico.rom)
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459 #define P32XS_FM (1<<15)
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460 #define P32XS_REN (1<< 7)
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461 #define P32XS_nRES (1<< 1)
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462 #define P32XS_ADEN (1<< 0)
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463 #define P32XS2_ADEN (1<< 9)
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464 #define P32XS_FULL (1<< 7) // DREQ FIFO full
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465 #define P32XS_68S (1<< 2)
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466 #define P32XS_DMA (1<< 1)
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467 #define P32XS_RV (1<< 0)
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469 #define P32XV_nPAL (1<<15) // VDP
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470 #define P32XV_PRI (1<< 7)
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471 #define P32XV_Mx (3<< 0) // display mode mask
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473 #define P32XV_SFT (1<< 0)
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475 #define P32XV_VBLK (1<<15)
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476 #define P32XV_HBLK (1<<14)
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477 #define P32XV_PEN (1<<13)
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478 #define P32XV_nFEN (1<< 1)
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479 #define P32XV_FS (1<< 0)
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481 #define P32XP_RTP (1<<7) // PWM control
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482 #define P32XP_FULL (1<<15) // PWM pulse
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483 #define P32XP_EMPTY (1<<14)
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485 #define P32XF_68KCPOLL (1 << 0)
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486 #define P32XF_68KVPOLL (1 << 1)
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488 #define P32XI_VRES (1 << 14/2) // IRL/2
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489 #define P32XI_VINT (1 << 12/2)
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490 #define P32XI_HINT (1 << 10/2)
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491 #define P32XI_CMD (1 << 8/2)
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492 #define P32XI_PWM (1 << 6/2)
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494 // peripheral reg access
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495 #define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]
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497 #define DMAC_FIFO_LEN (4*2)
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498 #define PWM_BUFF_LEN 1024 // in one channel samples
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500 #define SH2_DRCBLK_RAM_SHIFT 1
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501 #define SH2_DRCBLK_DA_SHIFT 1
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503 #define SH2_READ_SHIFT 25
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504 #define SH2_WRITE_SHIFT 25
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508 unsigned short regs[0x20];
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509 unsigned short vdp_regs[0x10]; // 0x40
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510 unsigned short sh2_regs[3]; // 0x60
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511 unsigned char pending_fb;
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512 unsigned char dirty_pal;
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513 unsigned int emu_flags;
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514 unsigned char sh2irq_mask[2];
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515 unsigned char sh2irqi[2]; // individual
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516 unsigned int sh2irqs; // common irqs
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517 unsigned short dmac_fifo[DMAC_FIFO_LEN];
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518 unsigned int pad[4];
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519 unsigned int dmac0_fifo_ptr;
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520 unsigned short vdp_fbcr_fake;
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521 unsigned short pad2;
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522 unsigned char comm_dirty_68k;
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523 unsigned char comm_dirty_sh2;
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524 unsigned char pwm_irq_cnt;
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525 unsigned char pad1;
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526 unsigned short pwm_p[2]; // pwm pos in fifo
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527 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)
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528 unsigned int reserved[6];
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533 unsigned char sdram[0x40000];
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535 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];
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537 unsigned short dram[2][0x20000/2]; // AKA fb
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539 unsigned char m68k_rom[0x100];
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540 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE
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543 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];
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545 unsigned char sh2_rom_m[0x800];
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546 unsigned char sh2_rom_s[0x400];
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547 unsigned short pal[0x100];
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548 unsigned short pal_native[0x100]; // converted to native (for renderer)
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549 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame
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550 signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries
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554 extern void (*PicoLoadStateHook)(void);
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560 } carthw_state_chunk;
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561 extern carthw_state_chunk *carthw_chunks;
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562 #define CHUNK_CARTHW 64
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565 extern int PicoCartResize(int newsize);
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566 extern void Byteswap(void *dst, const void *src, int len);
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567 extern void (*PicoCartMemSetup)(void);
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568 extern void (*PicoCartUnloadHook)(void);
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571 int CM_compareRun(int cyc, int is_sub);
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574 PICO_INTERNAL void PicoFrameStart(void);
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575 void PicoDrawSync(int to, int blank_last_line);
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576 void BackFill(int reg7, int sh);
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577 void FinalizeLine555(int sh, int line);
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578 extern int (*PicoScanBegin)(unsigned int num);
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579 extern int (*PicoScanEnd)(unsigned int num);
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580 extern int DrawScanline;
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581 #define MAX_LINE_SPRITES 29
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582 extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];
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583 extern void *DrawLineDestBase;
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584 extern int DrawLineDestIncrement;
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587 PICO_INTERNAL void PicoFrameFull();
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590 void PicoFrameStartMode4(void);
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591 void PicoLineMode4(int line);
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592 void PicoDoHighPal555M4(void);
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593 void PicoDrawSetOutputMode4(pdso_t which);
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596 PICO_INTERNAL void PicoMemSetup(void);
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597 unsigned int PicoRead8_io(unsigned int a);
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598 unsigned int PicoRead16_io(unsigned int a);
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599 void PicoWrite8_io(unsigned int a, unsigned int d);
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600 void PicoWrite16_io(unsigned int a, unsigned int d);
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601 void p32x_dreq1_trigger(void);
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604 PICO_INTERNAL void PicoMemSetupPico(void);
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607 PICO_INTERNAL void PicoMemSetupCD(void);
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608 void PicoMemStateLoaded(void);
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611 extern struct Pico Pico;
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612 extern struct PicoSRAM SRam;
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613 extern int PicoPadInt[2];
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614 extern int emustatus;
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615 extern int scanlines_total;
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616 extern void (*PicoResetHook)(void);
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617 extern void (*PicoLineHook)(void);
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618 PICO_INTERNAL int CheckDMA(void);
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619 PICO_INTERNAL void PicoDetectRegion(void);
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620 PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);
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623 PICO_INTERNAL void PicoInitMCD(void);
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624 PICO_INTERNAL void PicoExitMCD(void);
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625 PICO_INTERNAL void PicoPowerMCD(void);
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626 PICO_INTERNAL int PicoResetMCD(void);
\r
627 PICO_INTERNAL void PicoFrameMCD(void);
\r
630 PICO_INTERNAL void PicoInitPico(void);
\r
631 PICO_INTERNAL void PicoReratePico(void);
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634 PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);
\r
635 PICO_INTERNAL void PicoPicoPCMReset(void);
\r
636 PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);
\r
639 PICO_INTERNAL void SekInit(void);
\r
640 PICO_INTERNAL int SekReset(void);
\r
641 PICO_INTERNAL void SekState(int *data);
\r
642 PICO_INTERNAL void SekSetRealTAS(int use_real);
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643 PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);
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644 PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);
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645 void SekStepM68k(void);
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646 void SekInitIdleDet(void);
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647 void SekFinishIdleDet(void);
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648 #if defined(CPU_CMP_R) || defined(CPU_CMP_W)
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649 void SekTrace(int is_s68k);
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651 #define SekTrace(x)
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655 PICO_INTERNAL void SekInitS68k(void);
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656 PICO_INTERNAL int SekResetS68k(void);
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657 PICO_INTERNAL int SekInterruptS68k(int irq);
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660 PICO_INTERNAL void cdda_start_play();
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661 extern short cdda_out_buffer[2*1152];
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662 extern int PsndLen_exc_cnt;
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663 extern int PsndLen_exc_add;
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664 extern int timer_a_next_oflow, timer_a_step; // in z80 cycles
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665 extern int timer_b_next_oflow, timer_b_step;
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667 void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);
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668 void ym2612_pack_state(void);
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669 void ym2612_unpack_state(void);
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671 #define TIMER_NO_OFLOW 0x70000000
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672 // tA = 72 * (1024 - NA) / M
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673 #define TIMER_A_TICK_ZCYCLES 17203
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674 // tB = 1152 * (256 - NA) / M
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675 #define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura
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677 #define timers_cycle() \
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678 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \
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679 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \
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680 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \
\r
681 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \
\r
682 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);
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684 #define timers_reset() \
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685 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \
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686 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \
\r
687 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;
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691 PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);
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692 PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);
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693 PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);
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694 extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);
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697 PICO_INTERNAL_ASM void memcpy16(unsigned short *dest, unsigned short *src, int count);
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698 PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);
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699 PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count
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700 PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);
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703 void EEPROM_write8(unsigned int a, unsigned int d);
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704 void EEPROM_write16(unsigned int d);
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705 unsigned int EEPROM_read(void);
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707 // z80 functionality wrappers
\r
708 PICO_INTERNAL void z80_init(void);
\r
709 PICO_INTERNAL void z80_pack(void *data);
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710 PICO_INTERNAL int z80_unpack(const void *data);
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711 PICO_INTERNAL void z80_reset(void);
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712 PICO_INTERNAL void z80_exit(void);
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715 PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);
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716 PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);
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719 PICO_INTERNAL void PicoCDBufferRead(void *dest, int lba);
\r
722 PICO_INTERNAL void PsndReset(void);
\r
723 PICO_INTERNAL void PsndDoDAC(int line_to);
\r
724 PICO_INTERNAL void PsndClear(void);
\r
725 PICO_INTERNAL void PsndGetSamples(int y);
\r
726 PICO_INTERNAL void PsndGetSamplesMS(void);
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727 extern int PsndDacLine;
\r
731 void PicoPowerMS(void);
\r
732 void PicoResetMS(void);
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733 void PicoMemSetupMS(void);
\r
734 void PicoStateLoadedMS(void);
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735 void PicoFrameMS(void);
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736 void PicoFrameDrawOnlyMS(void);
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738 #define PicoPowerMS()
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739 #define PicoResetMS()
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740 #define PicoMemSetupMS()
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741 #define PicoStateLoadedMS()
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742 #define PicoFrameMS()
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743 #define PicoFrameDrawOnlyMS()
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748 extern struct Pico32x Pico32x;
\r
751 P32X_EVENT_FILLEND,
\r
755 extern unsigned int event_times[P32X_EVENT_COUNT];
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757 void Pico32xInit(void);
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758 void PicoPower32x(void);
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759 void PicoReset32x(void);
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760 void Pico32xStartup(void);
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761 void PicoUnload32x(void);
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762 void PicoFrame32x(void);
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763 void Pico32xStateLoaded(int is_early);
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764 void p32x_sync_sh2s(unsigned int m68k_target);
\r
765 void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);
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766 void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);
\r
767 void p32x_reset_sh2s(void);
\r
768 void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);
\r
769 void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);
\r
770 void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);
\r
773 struct Pico32xMem *Pico32xMem;
\r
774 unsigned int PicoRead8_32x(unsigned int a);
\r
775 unsigned int PicoRead16_32x(unsigned int a);
\r
776 void PicoWrite8_32x(unsigned int a, unsigned int d);
\r
777 void PicoWrite16_32x(unsigned int a, unsigned int d);
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778 void PicoMemSetup32x(void);
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779 void Pico32xSwapDRAM(int b);
\r
780 void Pico32xMemStateLoaded(void);
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781 void p32x_m68k_poll_event(unsigned int flags);
\r
782 void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);
\r
785 void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);
\r
786 void FinalizeLine32xRGB555(int sh, int line);
\r
787 void PicoDraw32xLayer(int offs, int lines, int mdbg);
\r
788 void PicoDraw32xLayerMdOnly(int offs, int lines);
\r
789 extern int (*PicoScan32xBegin)(unsigned int num);
\r
790 extern int (*PicoScan32xEnd)(unsigned int num);
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796 extern int Pico32xDrawMode;
\r
799 unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,
\r
800 unsigned int m68k_cycles);
\r
801 void p32x_pwm_write16(unsigned int a, unsigned int d,
\r
802 SH2 *sh2, unsigned int m68k_cycles);
\r
803 void p32x_pwm_update(int *buf32, int length, int stereo);
\r
804 void p32x_pwm_ctl_changed(void);
\r
805 void p32x_pwm_schedule(unsigned int m68k_now);
\r
806 void p32x_pwm_schedule_sh2(SH2 *sh2);
\r
807 void p32x_pwm_irq_event(unsigned int m68k_now);
\r
808 void p32x_pwm_state_loaded(void);
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811 void p32x_dreq0_trigger(void);
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812 void p32x_dreq1_trigger(void);
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813 void p32x_timers_recalc(void);
\r
814 void p32x_timers_do(unsigned int m68k_slice);
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815 void sh2_peripheral_reset(SH2 *sh2);
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816 unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);
\r
817 unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);
\r
818 unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);
\r
819 void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);
\r
820 void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);
\r
821 void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);
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824 #define Pico32xInit()
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825 #define PicoPower32x()
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826 #define PicoReset32x()
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827 #define PicoFrame32x()
\r
828 #define PicoUnload32x()
\r
829 #define Pico32xStateLoaded()
\r
830 #define FinalizeLine32xRGB555 NULL
\r
831 #define p32x_pwm_update(...)
\r
832 #define p32x_timers_recalc()
\r
835 /* avoid dependency on newer glibc */
\r
836 static __inline int isspace_(int c)
\r
838 return (0x09 <= c && c <= 0x0d) || c == ' ';
\r
842 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
\r
845 // emulation event logging
\r
847 # ifdef __x86_64__ // HACK
\r
848 # define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)
\r
850 # define EL_LOGMASK (EL_STATUS)
\r
854 #define EL_HVCNT 0x00000001 /* hv counter reads */
\r
855 #define EL_SR 0x00000002 /* SR reads */
\r
856 #define EL_INTS 0x00000004 /* ints and acks */
\r
857 #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */
\r
858 #define EL_INTSW 0x00000010 /* log irq switching on/off */
\r
859 #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */
\r
860 #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */
\r
861 #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */
\r
862 #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */
\r
863 #define EL_SRAMIO 0x00000200 /* sram i/o */
\r
864 #define EL_EEPROM 0x00000400 /* eeprom debug */
\r
865 #define EL_UIO 0x00000800 /* unmapped i/o */
\r
866 #define EL_IO 0x00001000 /* all i/o */
\r
867 #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */
\r
868 #define EL_SVP 0x00004000 /* SVP stuff */
\r
869 #define EL_PICOHW 0x00008000 /* Pico stuff */
\r
870 #define EL_IDLE 0x00010000 /* idle loop det. */
\r
871 #define EL_CDREGS 0x00020000 /* MCD: register access */
\r
872 #define EL_CDREG3 0x00040000 /* MCD: register 3 only */
\r
873 #define EL_32X 0x00080000
\r
874 #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */
\r
875 #define EL_32XP 0x00200000 /* 32X peripherals */
\r
877 #define EL_STATUS 0x40000000 /* status messages */
\r
878 #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */
\r
881 #define elprintf(w,f,...) \
\r
883 if ((w) & EL_LOGMASK) \
\r
884 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \
\r
886 #elif defined(_MSC_VER)
\r
889 #define elprintf(w,f,...)
\r
894 #include <platform/linux/pprof.h>
\r
896 #define pprof_init()
\r
897 #define pprof_finish()
\r
898 #define pprof_start(x)
\r
899 #define pprof_end(...)
\r
900 #define pprof_end_sub(...)
\r
922 void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);
\r
923 void pevt_dump(void);
\r
925 #define pevt_log_m68k(e) \
\r
926 pevt_log(SekCyclesDoneT(), EVT_M68K, e)
\r
927 #define pevt_log_m68k_o(e) \
\r
928 pevt_log(SekCyclesDoneT2(), EVT_M68K, e)
\r
929 #define pevt_log_sh2(sh2, e) \
\r
930 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)
\r
931 #define pevt_log_sh2_o(sh2, e) \
\r
932 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)
\r
934 #define pevt_log(c, e)
\r
935 #define pevt_log_m68k(e)
\r
936 #define pevt_log_m68k_o(e)
\r
937 #define pevt_log_sh2(sh2, e)
\r
938 #define pevt_log_sh2_o(sh2, e)
\r
939 #define pevt_dump()
\r
946 #define cdprintf(x...)
\r
950 #define REGPARM(x) __attribute__((regparm(x)))
\r
956 #define NOINLINE __attribute__((noinline))
\r
962 } // End of extern "C"
\r
965 #endif // PICO_INTERNAL_INCLUDED
\r