1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Functions for PSX hardware control.
25 #include "psxevents.h"
31 //#define PSXHW_LOG printf
36 static u32 (*psxHwReadGpuSRptr)(void) = psxHwReadGpuSR;
39 memset(psxH, 0, 0x10000);
41 mdecInit(); // initialize mdec decoder
44 HW_GPU_STATUS = SWAP32(0x10802000);
45 psxHwReadGpuSRptr = Config.hacks.gpu_busy_hack
46 ? psxHwReadGpuSRbusyHack : psxHwReadGpuSR;
49 void psxHwWriteIstat(u32 value)
51 u32 stat = psxHu16(0x1070) & value;
52 psxHu16ref(0x1070) = SWAPu16(stat);
54 psxRegs.CP0.n.Cause &= ~0x400;
55 if (stat & psxHu16(0x1074))
56 psxRegs.CP0.n.Cause |= 0x400;
59 void psxHwWriteImask(u32 value)
61 u32 stat = psxHu16(0x1070);
62 psxHu16ref(0x1074) = SWAPu16(value);
64 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
65 // log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
66 set_event(PSXINT_NEWDRC_CHECK, 1);
68 psxRegs.CP0.n.Cause &= ~0x400;
70 psxRegs.CP0.n.Cause |= 0x400;
73 void psxHwWriteDmaIcr32(u32 value)
75 u32 tmp = value & 0x00ff803f;
76 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
77 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
78 || tmp & HW_DMA_ICR_BUS_ERROR) {
79 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
80 psxHu32ref(0x1070) |= SWAP32(8);
81 tmp |= HW_DMA_ICR_IRQ_SENT;
83 HW_DMA_ICR = SWAPu32(tmp);
86 void psxHwWriteGpuSR(u32 value)
88 u32 old_sr = HW_GPU_STATUS, new_sr;
89 GPU_writeStatus(value);
91 new_sr = HW_GPU_STATUS;
92 // "The Next Tetris" seems to rely on the field order after enable
93 if ((old_sr ^ new_sr) & new_sr & SWAP32(PSXGPU_ILACE))
97 u32 psxHwReadGpuSR(void)
99 u32 v, c = psxRegs.cycle;
101 // meh2, syncing for img bit, might want to avoid it..
103 v = SWAP32(HW_GPU_STATUS);
104 v |= ((s32)(psxRegs.gpuIdleAfter - c) >> 31) & PSXGPU_nBUSY;
106 // XXX: because of large timeslices can't use hSyncCount, using rough
107 // approximization instead. Perhaps better use hcounter code here or something.
108 if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
109 v |= PSXGPU_LCF & (c << 20);
113 // a hack due to poor timing of gpu idle bit
114 // to get rid of this, GPU draw times, DMAs, cpu timing has to fall within
115 // certain timing window or else games like "ToHeart" softlock
116 u32 psxHwReadGpuSRbusyHack(void)
118 u32 v = psxHwReadGpuSR();
125 u8 psxHwRead8(u32 add) {
128 switch (add & 0x1fffffff) {
129 case 0x1f801040: hard = sioRead8(); break;
130 case 0x1f801800: hard = cdrRead0(); break;
131 case 0x1f801801: hard = cdrRead1(); break;
132 case 0x1f801802: hard = cdrRead2(); break;
133 case 0x1f801803: hard = cdrRead3(); break;
135 case 0x1f801041: case 0x1f801042: case 0x1f801043:
136 case 0x1f801044: case 0x1f801045:
137 case 0x1f801046: case 0x1f801047:
138 case 0x1f801048: case 0x1f801049:
139 case 0x1f80104a: case 0x1f80104b:
140 case 0x1f80104c: case 0x1f80104d:
141 case 0x1f80104e: case 0x1f80104f:
142 case 0x1f801050: case 0x1f801051:
143 case 0x1f801054: case 0x1f801055:
144 case 0x1f801058: case 0x1f801059:
145 case 0x1f80105a: case 0x1f80105b:
146 case 0x1f80105c: case 0x1f80105d:
147 case 0x1f801100: case 0x1f801101:
148 case 0x1f801104: case 0x1f801105:
149 case 0x1f801108: case 0x1f801109:
150 case 0x1f801110: case 0x1f801111:
151 case 0x1f801114: case 0x1f801115:
152 case 0x1f801118: case 0x1f801119:
153 case 0x1f801120: case 0x1f801121:
154 case 0x1f801124: case 0x1f801125:
155 case 0x1f801128: case 0x1f801129:
156 case 0x1f801810: case 0x1f801811:
157 case 0x1f801812: case 0x1f801813:
158 case 0x1f801814: case 0x1f801815:
159 case 0x1f801816: case 0x1f801817:
160 case 0x1f801820: case 0x1f801821:
161 case 0x1f801822: case 0x1f801823:
162 case 0x1f801824: case 0x1f801825:
163 case 0x1f801826: case 0x1f801827:
164 log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc);
167 if (0x1f801c00 <= add && add < 0x1f802000) {
168 u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
169 hard = (add & 1) ? val >> 8 : val;
174 PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
180 PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
185 u16 psxHwRead16(u32 add) {
188 switch (add & 0x1fffffff) {
190 case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070));
191 return psxHu16(0x1070);
192 case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074));
193 return psxHu16(0x1074);
197 hard|= sioRead8() << 8;
198 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
201 hard = sioReadStat16();
202 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
205 hard = sioReadMode16();
206 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
209 hard = sioReadCtrl16();
210 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
213 hard = sioReadBaud16();
214 PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
217 /* Fixes Armored Core misdetecting the Link cable being detected.
218 * We want to turn that thing off and force it to do local multiplayer instead.
219 * Thanks Sony for the fix, they fixed it in their PS Classic fork.
225 hard = psxRcntRcount0();
227 PSXHW_LOG("T0 count read16: %x\n", hard);
231 hard = psxRcntRmode(0);
233 PSXHW_LOG("T0 mode read16: %x\n", hard);
237 hard = psxRcntRtarget(0);
239 PSXHW_LOG("T0 target read16: %x\n", hard);
243 hard = psxRcntRcount1();
245 PSXHW_LOG("T1 count read16: %x\n", hard);
249 hard = psxRcntRmode(1);
251 PSXHW_LOG("T1 mode read16: %x\n", hard);
255 hard = psxRcntRtarget(1);
257 PSXHW_LOG("T1 target read16: %x\n", hard);
261 hard = psxRcntRcount2();
263 PSXHW_LOG("T2 count read16: %x\n", hard);
267 hard = psxRcntRmode(2);
269 PSXHW_LOG("T2 mode read16: %x\n", hard);
273 hard = psxRcntRtarget(2);
275 PSXHW_LOG("T2 target read16: %x\n", hard);
279 //case 0x1f802030: hard = //int_2000????
280 //case 0x1f802040: hard =//dip switches...??
299 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
302 if (0x1f801c00 <= add && add < 0x1f802000)
303 return SPU_readRegister(add, psxRegs.cycle);
306 PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
312 PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
317 u32 psxHwRead32(u32 add) {
320 switch (add & 0x1fffffff) {
323 hard |= sioRead8() << 8;
324 hard |= sioRead8() << 16;
325 hard |= sioRead8() << 24;
326 PAD_LOG("sio read32 ;ret = %x\n", hard);
329 hard = sioReadStat16();
330 PAD_LOG("sio read32 %x; ret = %x\n", add&0xf, hard);
334 PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
335 return psxHu32(0x1060);
336 case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
337 return psxHu32(0x1070);
338 case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
339 return psxHu32(0x1074);
343 hard = GPU_readData();
345 PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
349 hard = psxHwReadGpuSRptr();
351 PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
355 case 0x1f801820: hard = mdecRead0(); break;
356 case 0x1f801824: hard = mdecRead1(); break;
360 PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
361 return SWAPu32(HW_DMA2_MADR);
363 PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
364 return SWAPu32(HW_DMA2_BCR);
366 PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
367 return SWAPu32(HW_DMA2_CHCR);
372 PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
373 return SWAPu32(HW_DMA3_MADR);
375 PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
376 return SWAPu32(HW_DMA3_BCR);
378 PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
379 return SWAPu32(HW_DMA3_CHCR);
384 PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
385 return SWAPu32(HW_DMA_PCR); // dma rest channel
387 PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
388 return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
391 // time for rootcounters :)
393 hard = psxRcntRcount0();
395 PSXHW_LOG("T0 count read32: %x\n", hard);
399 hard = psxRcntRmode(0);
401 PSXHW_LOG("T0 mode read32: %x\n", hard);
405 hard = psxRcntRtarget(0);
407 PSXHW_LOG("T0 target read32: %x\n", hard);
411 hard = psxRcntRcount1();
413 PSXHW_LOG("T1 count read32: %x\n", hard);
417 hard = psxRcntRmode(1);
419 PSXHW_LOG("T1 mode read32: %x\n", hard);
423 hard = psxRcntRtarget(1);
425 PSXHW_LOG("T1 target read32: %x\n", hard);
429 hard = psxRcntRcount2();
431 PSXHW_LOG("T2 count read32: %x\n", hard);
435 hard = psxRcntRmode(2);
437 PSXHW_LOG("T2 mode read32: %x\n", hard);
441 hard = psxRcntRtarget(2);
443 PSXHW_LOG("T2 target read32: %x\n", hard);
454 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
457 if (0x1f801c00 <= add && add < 0x1f802000) {
458 hard = SPU_readRegister(add, psxRegs.cycle);
459 hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
464 PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
469 PSXHW_LOG("*Known 32bit read at address %x\n", add);
474 void psxHwWrite8(u32 add, u8 value) {
475 switch (add & 0x1fffffff) {
476 case 0x1f801040: sioWrite8(value); break;
\r
477 case 0x1f801800: cdrWrite0(value); break;
478 case 0x1f801801: cdrWrite1(value); break;
479 case 0x1f801802: cdrWrite2(value); break;
480 case 0x1f801803: cdrWrite3(value); break;
482 case 0x1f801041: case 0x1f801042: case 0x1f801043:
483 case 0x1f801044: case 0x1f801045:
484 case 0x1f801046: case 0x1f801047:
485 case 0x1f801048: case 0x1f801049:
486 case 0x1f80104a: case 0x1f80104b:
487 case 0x1f80104c: case 0x1f80104d:
488 case 0x1f80104e: case 0x1f80104f:
489 case 0x1f801050: case 0x1f801051:
490 case 0x1f801054: case 0x1f801055:
491 case 0x1f801058: case 0x1f801059:
492 case 0x1f80105a: case 0x1f80105b:
493 case 0x1f80105c: case 0x1f80105d:
494 case 0x1f801100: case 0x1f801101:
495 case 0x1f801104: case 0x1f801105:
496 case 0x1f801108: case 0x1f801109:
497 case 0x1f801110: case 0x1f801111:
498 case 0x1f801114: case 0x1f801115:
499 case 0x1f801118: case 0x1f801119:
500 case 0x1f801120: case 0x1f801121:
501 case 0x1f801124: case 0x1f801125:
502 case 0x1f801128: case 0x1f801129:
503 case 0x1f801810: case 0x1f801811:
504 case 0x1f801812: case 0x1f801813:
505 case 0x1f801814: case 0x1f801815:
506 case 0x1f801816: case 0x1f801817:
507 case 0x1f801820: case 0x1f801821:
508 case 0x1f801822: case 0x1f801823:
509 case 0x1f801824: case 0x1f801825:
510 case 0x1f801826: case 0x1f801827:
511 log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc);
514 if (0x1f801c00 <= add && add < 0x1f802000) {
515 log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
517 SPU_writeRegister(add, value, psxRegs.cycle);
523 PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
529 PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
533 void psxHwWrite16(u32 add, u16 value) {
534 switch (add & 0x1fffffff) {
536 sioWrite8((unsigned char)value);
537 sioWrite8((unsigned char)(value>>8));
538 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
541 sioWriteStat16(value);
542 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
545 sioWriteMode16(value);
546 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
548 case 0x1f80104a: // control register
549 sioWriteCtrl16(value);
550 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
552 case 0x1f80104e: // baudrate register
553 sioWriteBaud16(value);
554 PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
558 PSXHW_LOG("IREG 16bit write %x\n", value);
560 psxHwWriteIstat(value);
565 PSXHW_LOG("IMASK 16bit write %x\n", value);
567 psxHwWriteImask(value);
572 PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value);
574 psxRcntWcount(0, value); return;
577 PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value);
579 psxRcntWmode(0, value); return;
582 PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value);
584 psxRcntWtarget(0, value); return;
588 PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value);
590 psxRcntWcount(1, value); return;
593 PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value);
595 psxRcntWmode(1, value); return;
598 PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value);
600 psxRcntWtarget(1, value); return;
604 PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value);
606 psxRcntWcount(2, value); return;
609 PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value);
611 psxRcntWmode(2, value); return;
614 PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value);
616 psxRcntWtarget(2, value); return;
636 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
639 if (0x1f801c00 <= add && add < 0x1f802000) {
640 SPU_writeRegister(add, value, psxRegs.cycle);
644 psxHu16ref(add) = SWAPu16(value);
646 PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
650 psxHu16ref(add) = SWAPu16(value);
652 PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
656 #define DmaExec(n) { \
657 if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
658 log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
659 HW_DMA##n##_CHCR = SWAPu32(value); \
661 if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \
662 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \
666 void psxHwWrite32(u32 add, u32 value) {
667 switch (add & 0x1fffffff) {
669 sioWrite8((unsigned char)value);
670 sioWrite8((unsigned char)((value&0xff) >> 8));
671 sioWrite8((unsigned char)((value&0xff) >> 16));
672 sioWrite8((unsigned char)((value&0xff) >> 24));
673 PAD_LOG("sio write32 %x\n", value);
677 PSXHW_LOG("RAM size write %x\n", value);
678 psxHu32ref(add) = SWAPu32(value);
684 PSXHW_LOG("IREG 32bit write %x\n", value);
686 psxHwWriteIstat(value);
690 PSXHW_LOG("IMASK 32bit write %x\n", value);
692 psxHwWriteImask(value);
697 PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
698 HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
700 PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
701 HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
705 PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
707 DmaExec(0); // DMA0 chcr (MDEC in DMA)
712 PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
713 HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
715 PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
716 HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
720 PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
722 DmaExec(1); // DMA1 chcr (MDEC out DMA)
727 PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
728 HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
730 PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
731 HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
735 PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
737 DmaExec(2); // DMA2 chcr (GPU DMA)
742 PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
743 HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
745 PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
746 HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
750 PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
752 DmaExec(3); // DMA3 chcr (CDROM DMA)
758 PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
759 HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
761 PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
762 HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
766 PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
768 DmaExec(4); // DMA4 chcr (SPU DMA)
772 case 0x1f8010d0: break; //DMA5write_madr();
773 case 0x1f8010d4: break; //DMA5write_bcr();
774 case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
779 PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
780 HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
782 PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
783 HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
787 PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
789 DmaExec(6); // DMA6 chcr (OT clear)
794 PSXHW_LOG("DMA PCR 32bit write %x\n", value);
795 HW_DMA_PCR = SWAPu32(value);
801 PSXHW_LOG("DMA ICR 32bit write %x\n", value);
803 psxHwWriteDmaIcr32(value);
808 PSXHW_LOG("GPU DATA 32bit write %x\n", value);
810 GPU_writeData(value); return;
813 PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
815 psxHwWriteGpuSR(value);
819 mdecWrite0(value); break;
821 mdecWrite1(value); break;
825 PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
827 psxRcntWcount(0, value & 0xffff); return;
830 PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
832 psxRcntWmode(0, value); return;
835 PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
837 psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000);
841 PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
843 psxRcntWcount(1, value & 0xffff); return;
846 PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
848 psxRcntWmode(1, value); return;
851 PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
853 psxRcntWtarget(1, value & 0xffff); return;
857 PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
859 psxRcntWcount(2, value & 0xffff); return;
862 PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
864 psxRcntWmode(2, value); return;
867 PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
869 psxRcntWtarget(2, value & 0xffff); return;
879 log_unhandled("unhandled w32 %08x @%08x\n", add, psxRegs.pc);
882 // Dukes of Hazard 2 - car engine noise
883 if (0x1f801c00 <= add && add < 0x1f802000) {
884 SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
885 SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
889 psxHu32ref(add) = SWAPu32(value);
891 PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
895 psxHu32ref(add) = SWAPu32(value);
897 PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
901 int psxHwFreeze(void *f, int Mode) {