1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
3 * Copyright (C) 2023 notaz *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
19 ***************************************************************************/
22 * PSX assembly interpreter.
25 #include "psxcommon.h"
29 #include "psxinterpreter.h"
32 #include "../include/compiler_features.h"
34 // these may cause issues: because of poor timing we may step
35 // on instructions that real hardware would never reach
36 #define DO_EXCEPTION_RESERVEDI
37 #define HANDLE_LOAD_DELAY
39 static int branchSeen = 0;
42 #define INT_ATTR __attribute__((regparm(2)))
47 #define INVALID_PTR NULL
51 static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code);
52 static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code);
55 static void doLoad(psxRegisters *regs, u32 r, u32 val)
57 #ifdef HANDLE_LOAD_DELAY
58 int sel = regs->dloadSel ^ 1;
59 assert(regs->dloadReg[sel] == 0);
60 regs->dloadReg[sel] = r;
61 regs->dloadVal[sel] = r ? val : 0;
62 if (regs->dloadReg[sel ^ 1] == r)
63 regs->dloadVal[sel ^ 1] = regs->dloadReg[sel ^ 1] = 0;
65 regs->GPR.r[r] = r ? val : 0;
69 static void dloadRt(psxRegisters *regs, u32 r, u32 val)
71 #ifdef HANDLE_LOAD_DELAY
72 int sel = regs->dloadSel;
73 if (unlikely(regs->dloadReg[sel] == r))
74 regs->dloadVal[sel] = regs->dloadReg[sel] = 0;
76 regs->GPR.r[r] = r ? val : 0;
79 static void dloadStep(psxRegisters *regs)
81 #ifdef HANDLE_LOAD_DELAY
82 int sel = regs->dloadSel;
83 regs->GPR.r[regs->dloadReg[sel]] = regs->dloadVal[sel];
84 regs->dloadVal[sel] = regs->dloadReg[sel] = 0;
86 assert(regs->GPR.r[0] == 0);
90 static void dloadFlush(psxRegisters *regs)
92 #ifdef HANDLE_LOAD_DELAY
93 regs->GPR.r[regs->dloadReg[0]] = regs->dloadVal[0];
94 regs->GPR.r[regs->dloadReg[1]] = regs->dloadVal[1];
95 regs->dloadVal[0] = regs->dloadVal[1] = 0;
96 regs->dloadReg[0] = regs->dloadReg[1] = 0;
97 assert(regs->GPR.r[0] == 0);
101 static void dloadClear(psxRegisters *regs)
103 #ifdef HANDLE_LOAD_DELAY
104 regs->dloadVal[0] = regs->dloadVal[1] = 0;
105 regs->dloadReg[0] = regs->dloadReg[1] = 0;
110 static void intException(psxRegisters *regs, u32 pc, u32 cause)
113 //FILE *f = fopen("/tmp/psx_ram.bin", "wb");
114 //fwrite(psxM, 1, 0x200000, f); fclose(f);
115 log_unhandled("exception %08x @%08x ra=%08x\n",
116 cause, pc, regs->GPR.n.ra);
120 psxException(cause, regs->branching, ®s->CP0);
121 regs->branching = R3000A_BRANCH_NONE_OR_EXCEPTION;
124 // exception caused by current instruction (excluding unkasking)
125 static void intExceptionInsn(psxRegisters *regs, u32 cause)
127 cause |= (regs->code & 0x0c000000) << 2;
128 intException(regs, regs->pc - 4, cause);
131 // 29 Enable for 80000000-ffffffff
132 // 30 Enable for 00000000-7fffffff
133 // 31 Enable exception
134 #define DBR_ABIT(dc, a) ((dc) & (1u << (29+(((a)>>31)^1))))
135 #define DBR_EN_EXEC(dc, a) (((dc) & 0x01800000) == 0x01800000 && DBR_ABIT(dc, a))
136 #define DBR_EN_LD(dc, a) (((dc) & 0x06800000) == 0x06800000 && DBR_ABIT(dc, a))
137 #define DBR_EN_ST(dc, a) (((dc) & 0x0a800000) == 0x0a800000 && DBR_ABIT(dc, a))
138 static void intExceptionDebugBp(psxRegisters *regs, u32 pc)
140 psxCP0Regs *cp0 = ®s->CP0;
142 cp0->n.Cause &= 0x300;
143 cp0->n.Cause |= (regs->branching << 30) | (R3000E_Bp << 2);
144 cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2);
145 cp0->n.EPC = regs->branching ? pc - 4 : pc;
146 psxRegs.pc = 0x80000040;
149 static int execBreakCheck(psxRegisters *regs, u32 pc)
151 if (unlikely(DBR_EN_EXEC(regs->CP0.n.DCIC, pc) &&
152 ((pc ^ regs->CP0.n.BPC) & regs->CP0.n.BPCM) == 0))
154 regs->CP0.n.DCIC |= 0x03;
155 if (regs->CP0.n.DCIC & (1u << 31)) {
156 intExceptionDebugBp(regs, pc);
163 // get an opcode without triggering exceptions or affecting cache
164 u32 intFakeFetch(u32 pc)
166 u8 *base = psxMemRLUT[pc >> 16];
168 if (unlikely(base == INVALID_PTR))
170 code = (u32 *)(base + (pc & 0xfffc));
171 return SWAP32(*code);
175 static u32 INT_ATTR fetchNoCache(psxRegisters *regs, u8 **memRLUT, u32 pc)
177 u8 *base = memRLUT[pc >> 16];
179 if (unlikely(base == INVALID_PTR)) {
180 SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
181 intException(regs, pc, R3000E_IBE << 2);
182 return 0; // execute as nop
184 code = (u32 *)(base + (pc & 0xfffc));
185 return SWAP32(*code);
190 Use old CPU cache code when the RAM location is updated with new code (affects in-game racing)
192 static struct cache_entry {
197 static u32 INT_ATTR fetchICache(psxRegisters *regs, u8 **memRLUT, u32 pc)
202 // this is not how the hardware works but whatever
203 struct cache_entry *entry = &ICache[(pc & 0xff0) >> 4];
205 if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag)
207 const u8 *base = memRLUT[pc >> 16];
209 if (unlikely(base == INVALID_PTR)) {
210 SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
211 intException(regs, pc, R3000E_IBE << 2);
212 return 0; // execute as nop
214 code = (u32 *)(base + (pc & 0xfff0));
217 // treat as 4 words, although other configurations are said to be possible
220 case 0x00: entry->data[0] = SWAP32(code[0]);
221 case 0x04: entry->data[1] = SWAP32(code[1]);
222 case 0x08: entry->data[2] = SWAP32(code[2]);
223 case 0x0c: entry->data[3] = SWAP32(code[3]);
226 return entry->data[(pc & 0x0f) >> 2];
229 return fetchNoCache(regs, memRLUT, pc);
232 static u32 (INT_ATTR *fetch)(psxRegisters *regs_, u8 **memRLUT, u32 pc) = fetchNoCache;
234 // Make the timing events trigger faster as we are currently assuming everything
235 // takes one cycle, which is not the case on real hardware.
236 // FIXME: count cache misses, memory latencies, stalls to get rid of this
237 static inline void addCycle(psxRegisters *regs)
239 assert(regs->subCycleStep >= 0x10000);
240 regs->subCycle += regs->subCycleStep;
241 regs->cycle += regs->subCycle >> 16;
242 regs->subCycle &= 0xffff;
245 /**** R3000A Instruction Macros ****/
246 #define _PC_ regs_->pc // The next PC to be executed
248 #define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
249 #define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
250 #define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
251 #define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
252 #define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
253 #define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register
254 #define _fIm_(code) ((u16)code) // The immediate part of the instruction register
255 #define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register
257 #define _fImm_(code) ((s16)code) // sign-extended immediate
258 #define _fImmU_(code) (code&0xffff) // zero-extended immediate
260 #define _Op_ _fOp_(code)
261 #define _Funct_ _fFunct_(code)
262 #define _Rd_ _fRd_(code)
263 #define _Rt_ _fRt_(code)
264 #define _Rs_ _fRs_(code)
265 #define _Sa_ _fSa_(code)
266 #define _Im_ _fIm_(code)
267 #define _Target_ _fTarget_(code)
269 #define _Imm_ _fImm_(code)
270 #define _ImmU_ _fImmU_(code)
272 #define _rRs_ regs_->GPR.r[_Rs_] // Rs register
273 #define _rRt_ regs_->GPR.r[_Rt_] // Rt register
274 #define _rSa_ regs_->GPR.r[_Sa_] // Sa register
276 #define _rHi_ regs_->GPR.n.hi // The HI register
277 #define _rLo_ regs_->GPR.n.lo // The LO register
279 #define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
280 #define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction
282 #define _SetLink(x) dloadRt(regs_, x, _PC_ + 4); // Sets the return address in the link register
285 static inline INT_ATTR void name(psxRegisters *regs_, u32 code)
287 // this defines shall be used with the tmp
288 // of the next func (instead of _Funct_...)
289 #define _tFunct_ ((tmp ) & 0x3F) // The funct part of the instruction register
290 #define _tRd_ ((tmp >> 11) & 0x1F) // The rd part of the instruction register
291 #define _tRt_ ((tmp >> 16) & 0x1F) // The rt part of the instruction register
292 #define _tRs_ ((tmp >> 21) & 0x1F) // The rs part of the instruction register
293 #define _tSa_ ((tmp >> 6) & 0x1F) // The sa part of the instruction register
295 #define _i32(x) (s32)(x)
296 #define _u32(x) (u32)(x)
298 #define isBranch(c_) \
299 ((1 <= ((c_) >> 26) && ((c_) >> 26) <= 7) || ((c_) & 0xfc00003e) == 8)
300 #define swap_(a_, b_) { u32 t_ = a_; a_ = b_; b_ = t_; }
302 // tar1 is main branch target, 'code' is opcode in DS
303 static u32 psxBranchNoDelay(psxRegisters *regs_, u32 tar1, u32 code, int *taken) {
306 assert(isBranch(code));
308 switch (code >> 26) {
309 case 0x00: // SPECIAL
316 regs_->GPR.r[_Rd_] = tar1 + 4;
324 regs_->GPR.n.ra = tar1 + 4;
326 return tar1 + (s16)_Im_ * 4;
329 regs_->GPR.n.ra = tar1 + 4;
330 if (_i32(_rRs_) >= 0)
331 return tar1 + (s16)_Im_ * 4;
334 if (rt & 1) { // BGEZ
335 if (_i32(_rRs_) >= 0)
336 return tar1 + (s16)_Im_ * 4;
340 return tar1 + (s16)_Im_ * 4;
346 return (tar1 & 0xf0000000u) + _Target_ * 4;
348 regs_->GPR.n.ra = tar1 + 4;
349 return (tar1 & 0xf0000000u) + _Target_ * 4;
351 if (_i32(_rRs_) == _i32(_rRt_))
352 return tar1 + (s16)_Im_ * 4;
355 if (_i32(_rRs_) != _i32(_rRt_))
356 return tar1 + (s16)_Im_ * 4;
359 if (_i32(_rRs_) <= 0)
360 return tar1 + (s16)_Im_ * 4;
364 return tar1 + (s16)_Im_ * 4;
372 static void psxDoDelayBranch(psxRegisters *regs, u32 tar1, u32 code1) {
376 tar2 = psxBranchNoDelay(regs, tar1, code1, &taken);
382 * taken branch in delay slot:
383 * - execute 1 instruction at tar1
384 * - jump to tar2 (target of branch in delay slot; this branch
385 * has no normal delay slot, instruction at tar1 was fetched instead)
387 for (lim = 0; lim < 8; lim++) {
388 regs->code = code = fetch(regs, psxMemRLUT, tar1);
390 if (likely(!isBranch(code))) {
392 psxBSC[code >> 26](regs, code);
396 tar1 = psxBranchNoDelay(regs, tar2, code, &taken);
402 SysPrintf("Evil chained DS branches @ %08x %08x %08x\n", regs->pc, tar1, tar2);
405 static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
406 u32 code, pc, pc_final;
408 branchSeen = regs->branching = taken;
409 pc_final = taken == R3000A_BRANCH_TAKEN ? tar : regs->pc + 4;
411 // fetch the delay slot
414 regs->code = code = fetch(regs, psxMemRLUT, pc);
418 // check for branch in delay slot
419 if (unlikely(isBranch(code))) {
421 if (taken == R3000A_BRANCH_TAKEN)
422 psxDoDelayBranch(regs, tar, code);
423 log_unhandled("branch in DS: %08x->%08x\n", pc, regs->pc);
430 psxBSC[code >> 26](regs, code);
432 if (likely(regs->branching != R3000A_BRANCH_NONE_OR_EXCEPTION))
435 regs->CP0.n.Target = pc_final;
441 static void doBranchReg(psxRegisters *regs, u32 tar) {
442 doBranch(regs, tar & ~3, R3000A_BRANCH_TAKEN);
445 static void doBranchRegE(psxRegisters *regs, u32 tar) {
446 if (unlikely(DBR_EN_EXEC(regs->CP0.n.DCIC, tar) &&
447 ((tar ^ regs->CP0.n.BPC) & regs->CP0.n.BPCM) == 0))
448 regs->CP0.n.DCIC |= 0x03;
449 if (unlikely(tar & 3)) {
450 SysPrintf("game crash @%08x, ra=%08x\n", tar, regs->GPR.n.ra);
451 regs->CP0.n.BadVAddr = tar;
452 intException(regs, tar, R3000E_AdEL << 2);
455 doBranch(regs, tar, R3000A_BRANCH_TAKEN);
458 static void addExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) {
460 if (add_overflow(a1, a2, val)) {
461 //printf("ov %08x + %08x = %08x\n", a1, a2, val);
462 intExceptionInsn(regs, R3000E_Ov << 2);
465 dloadRt(regs, rt, val);
468 static void subExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) {
470 if (sub_overflow(a1, a2, val)) {
471 intExceptionInsn(regs, R3000E_Ov << 2);
474 dloadRt(regs, rt, val);
477 /*********************************************************
478 * Arithmetic with immediate operand *
479 * Format: OP rt, rs, immediate *
480 *********************************************************/
481 OP(psxADDI) { addExc (regs_, _Rt_, _i32(_rRs_), _Imm_); } // Rt = Rs + Im (Exception on Integer Overflow)
482 OP(psxADDIU) { dloadRt(regs_, _Rt_, _u32(_rRs_) + _Imm_ ); } // Rt = Rs + Im
483 OP(psxANDI) { dloadRt(regs_, _Rt_, _u32(_rRs_) & _ImmU_); } // Rt = Rs And Im
484 OP(psxORI) { dloadRt(regs_, _Rt_, _u32(_rRs_) | _ImmU_); } // Rt = Rs Or Im
485 OP(psxXORI) { dloadRt(regs_, _Rt_, _u32(_rRs_) ^ _ImmU_); } // Rt = Rs Xor Im
486 OP(psxSLTI) { dloadRt(regs_, _Rt_, _i32(_rRs_) < _Imm_ ); } // Rt = Rs < Im (Signed)
487 OP(psxSLTIU) { dloadRt(regs_, _Rt_, _u32(_rRs_) < ((u32)_Imm_)); } // Rt = Rs < Im (Unsigned)
489 /*********************************************************
490 * Register arithmetic *
491 * Format: OP rd, rs, rt *
492 *********************************************************/
493 OP(psxADD) { addExc (regs_, _Rd_, _i32(_rRs_), _i32(_rRt_)); } // Rd = Rs + Rt (Exception on Integer Overflow)
494 OP(psxSUB) { subExc (regs_, _Rd_, _i32(_rRs_), _i32(_rRt_)); } // Rd = Rs - Rt (Exception on Integer Overflow)
495 OP(psxADDU) { dloadRt(regs_, _Rd_, _u32(_rRs_) + _u32(_rRt_)); } // Rd = Rs + Rt
496 OP(psxSUBU) { dloadRt(regs_, _Rd_, _u32(_rRs_) - _u32(_rRt_)); } // Rd = Rs - Rt
497 OP(psxAND) { dloadRt(regs_, _Rd_, _u32(_rRs_) & _u32(_rRt_)); } // Rd = Rs And Rt
498 OP(psxOR) { dloadRt(regs_, _Rd_, _u32(_rRs_) | _u32(_rRt_)); } // Rd = Rs Or Rt
499 OP(psxXOR) { dloadRt(regs_, _Rd_, _u32(_rRs_) ^ _u32(_rRt_)); } // Rd = Rs Xor Rt
500 OP(psxNOR) { dloadRt(regs_, _Rd_, ~_u32(_rRs_ | _u32(_rRt_))); } // Rd = Rs Nor Rt
501 OP(psxSLT) { dloadRt(regs_, _Rd_, _i32(_rRs_) < _i32(_rRt_)); } // Rd = Rs < Rt (Signed)
502 OP(psxSLTU) { dloadRt(regs_, _Rd_, _u32(_rRs_) < _u32(_rRt_)); } // Rd = Rs < Rt (Unsigned)
504 /*********************************************************
505 * Register mult/div & Register trap logic *
506 * Format: OP rs, rt *
507 *********************************************************/
511 if (_rRs_ & 0x80000000) {
517 #if !defined(__arm__) && !defined(__aarch64__)
518 else if (_rRs_ == 0x80000000 && _rRt_ == 0xFFFFFFFF) {
524 _rLo_ = _i32(_rRs_) / _i32(_rRt_);
525 _rHi_ = _i32(_rRs_) % _i32(_rRt_);
530 regs_->muldivBusyCycle = regs_->cycle + 37;
536 _rLo_ = _rRs_ / _rRt_;
537 _rHi_ = _rRs_ % _rRt_;
546 regs_->muldivBusyCycle = regs_->cycle + 37;
547 psxDIVU(regs_, code);
551 u64 res = (s64)_i32(_rRs_) * _i32(_rRt_);
553 regs_->GPR.n.lo = (u32)res;
554 regs_->GPR.n.hi = (u32)(res >> 32);
558 // approximate, but maybe good enough
560 u32 lz = __builtin_clz(((rs ^ ((s32)rs >> 21)) | 1));
561 u32 c = 7 + (2 - (lz / 11)) * 4;
562 regs_->muldivBusyCycle = regs_->cycle + c;
563 psxMULT(regs_, code);
567 u64 res = (u64)_u32(_rRs_) * _u32(_rRt_);
569 regs_->GPR.n.lo = (u32)(res & 0xffffffff);
570 regs_->GPR.n.hi = (u32)((res >> 32) & 0xffffffff);
574 // approximate, but maybe good enough
575 u32 lz = __builtin_clz(_rRs_ | 1);
576 u32 c = 7 + (2 - (lz / 11)) * 4;
577 regs_->muldivBusyCycle = regs_->cycle + c;
578 psxMULTU(regs_, code);
581 /*********************************************************
582 * Register branch logic *
583 * Format: OP rs, offset *
584 *********************************************************/
585 #define BrCond(c) (c) ? R3000A_BRANCH_TAKEN : R3000A_BRANCH_NOT_TAKEN
586 #define RepZBranchi32(op) \
587 doBranch(regs_, _BranchTarget_, BrCond(_i32(_rRs_) op 0));
588 #define RepZBranchLinki32(op) { \
589 s32 temp = _i32(_rRs_); \
592 doBranch(regs_, _BranchTarget_, BrCond(temp op 0)); \
595 OP(psxBGEZ) { RepZBranchi32(>=) } // Branch if Rs >= 0
596 OP(psxBGEZAL) { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link
597 OP(psxBGTZ) { RepZBranchi32(>) } // Branch if Rs > 0
598 OP(psxBLEZ) { RepZBranchi32(<=) } // Branch if Rs <= 0
599 OP(psxBLTZ) { RepZBranchi32(<) } // Branch if Rs < 0
600 OP(psxBLTZAL) { RepZBranchLinki32(<) } // Branch if Rs < 0 and link
602 /*********************************************************
603 * Shift arithmetic with constant shift *
604 * Format: OP rd, rt, sa *
605 *********************************************************/
606 OP(psxSLL) { dloadRt(regs_, _Rd_, _u32(_rRt_) << _Sa_); } // Rd = Rt << sa
607 OP(psxSRA) { dloadRt(regs_, _Rd_, _i32(_rRt_) >> _Sa_); } // Rd = Rt >> sa (arithmetic)
608 OP(psxSRL) { dloadRt(regs_, _Rd_, _u32(_rRt_) >> _Sa_); } // Rd = Rt >> sa (logical)
610 /*********************************************************
611 * Shift arithmetic with variant register shift *
612 * Format: OP rd, rt, rs *
613 *********************************************************/
614 OP(psxSLLV) { dloadRt(regs_, _Rd_, _u32(_rRt_) << (_u32(_rRs_) & 0x1F)); } // Rd = Rt << rs
615 OP(psxSRAV) { dloadRt(regs_, _Rd_, _i32(_rRt_) >> (_u32(_rRs_) & 0x1F)); } // Rd = Rt >> rs (arithmetic)
616 OP(psxSRLV) { dloadRt(regs_, _Rd_, _u32(_rRt_) >> (_u32(_rRs_) & 0x1F)); } // Rd = Rt >> rs (logical)
618 /*********************************************************
619 * Load higher 16 bits of the first word in GPR with imm *
620 * Format: OP rt, immediate *
621 *********************************************************/
622 OP(psxLUI) { dloadRt(regs_, _Rt_, code << 16); } // Upper halfword of Rt = Im
624 /*********************************************************
625 * Move from HI/LO to GPR *
627 *********************************************************/
628 OP(psxMFHI) { dloadRt(regs_, _Rd_, _rHi_); } // Rd = Hi
629 OP(psxMFLO) { dloadRt(regs_, _Rd_, _rLo_); } // Rd = Lo
631 static void mflohiCheckStall(psxRegisters *regs_)
633 u32 left = regs_->muldivBusyCycle - regs_->cycle;
635 //printf("muldiv stall %u\n", left);
636 regs_->cycle = regs_->muldivBusyCycle;
640 OP(psxMFHI_stall) { mflohiCheckStall(regs_); psxMFHI(regs_, code); }
641 OP(psxMFLO_stall) { mflohiCheckStall(regs_); psxMFLO(regs_, code); }
643 /*********************************************************
644 * Move to GPR to HI/LO & Register jump *
646 *********************************************************/
647 OP(psxMTHI) { _rHi_ = _rRs_; } // Hi = Rs
648 OP(psxMTLO) { _rLo_ = _rRs_; } // Lo = Rs
650 /*********************************************************
651 * Special purpose instructions *
653 *********************************************************/
655 intExceptionInsn(regs_, R3000E_Bp << 2);
659 intExceptionInsn(regs_, R3000E_Syscall << 2);
662 static inline void execI_(u8 **memRLUT, psxRegisters *regs_);
664 static inline void psxTestSWInts(psxRegisters *regs_, int step) {
665 if ((regs_->CP0.n.Cause & regs_->CP0.n.SR & 0x0300) &&
666 (regs_->CP0.n.SR & 0x1)) {
668 execI_(psxMemRLUT, regs_);
669 regs_->CP0.n.Cause &= ~0x7c;
670 intException(regs_, regs_->pc, regs_->CP0.n.Cause);
675 regs_->CP0.n.SR = (regs_->CP0.n.SR & ~0x0f) | ((regs_->CP0.n.SR & 0x3c) >> 2);
676 psxTestSWInts(regs_, 0);
679 /*********************************************************
680 * Register branch logic *
681 * Format: OP rs, rt, offset *
682 *********************************************************/
683 #define RepBranchi32(op) \
684 doBranch(regs_, _BranchTarget_, BrCond(_i32(_rRs_) op _i32(_rRt_)));
686 OP(psxBEQ) { RepBranchi32(==) } // Branch if Rs == Rt
687 OP(psxBNE) { RepBranchi32(!=) } // Branch if Rs != Rt
689 /*********************************************************
691 * Format: OP target *
692 *********************************************************/
693 OP(psxJ) { doBranch(regs_, _JumpTarget_, R3000A_BRANCH_TAKEN); }
697 doBranch(regs_, _JumpTarget_, R3000A_BRANCH_TAKEN);
700 /*********************************************************
702 * Format: OP rs, rd *
703 *********************************************************/
705 doBranchReg(regs_, _rRs_);
710 doBranchRegE(regs_, _rRs_);
715 u32 temp = _u32(_rRs_);
717 if (_Rd_) { _SetLink(_Rd_); }
718 doBranchReg(regs_, temp);
722 u32 temp = _u32(_rRs_);
724 if (_Rd_) { _SetLink(_Rd_); }
725 doBranchRegE(regs_, temp);
728 /*********************************************************
729 *********************************************************/
731 // revisit: incomplete
732 #define BUS_LOCKED_ADDR(a) \
733 ((0x1fc80000u <= (a) && (a) < 0x80000000u) || \
734 (0xc0000000u <= (a) && (a) < 0xfffe0000u))
736 // exception checking order is important
737 static inline int checkLD(psxRegisters *regs, u32 addr, u32 m) {
739 if (unlikely(DBR_EN_LD(regs->CP0.n.DCIC, addr) &&
740 ((addr ^ regs->CP0.n.BDA) & regs->CP0.n.BDAM) == 0)) {
741 regs->CP0.n.DCIC |= 0x0d;
742 bpException = regs->CP0.n.DCIC >> 31;
744 if (unlikely(addr & m)) {
745 regs->CP0.n.BadVAddr = addr;
746 intExceptionInsn(regs, R3000E_AdEL << 2);
749 if (unlikely(bpException)) {
750 intExceptionDebugBp(regs, regs->pc - 4);
753 if (unlikely(BUS_LOCKED_ADDR(addr))) {
754 intException(regs, regs->pc - 4, R3000E_DBE << 2);
760 static inline int checkST(psxRegisters *regs, u32 addr, u32 m) {
762 if (unlikely(DBR_EN_ST(regs->CP0.n.DCIC, addr) &&
763 ((addr ^ regs->CP0.n.BDA) & regs->CP0.n.BDAM) == 0)) {
764 regs->CP0.n.DCIC |= 0x15;
765 bpException = regs->CP0.n.DCIC >> 31;
767 if (unlikely(addr & m)) {
768 regs->CP0.n.BadVAddr = addr;
769 intExceptionInsn(regs, R3000E_AdES << 2);
772 if (unlikely(bpException)) {
773 intExceptionDebugBp(regs, regs->pc - 4);
776 if (unlikely(BUS_LOCKED_ADDR(addr))) {
777 intException(regs, regs->pc - 4, R3000E_DBE << 2);
783 /*********************************************************
784 * Load and store for GPR *
785 * Format: OP rt, offset(base) *
786 *********************************************************/
788 /*********************************************************
789 * Load and store for GPR *
790 * Format: OP rt, offset(base) *
791 *********************************************************/
793 #define _oB_ (regs_->GPR.r[_Rs_] + _Imm_)
795 OP(psxLB) { doLoad(regs_, _Rt_, (s8)psxMemRead8(_oB_)); }
796 OP(psxLBU) { doLoad(regs_, _Rt_, psxMemRead8(_oB_)); }
797 OP(psxLH) { doLoad(regs_, _Rt_, (s16)psxMemRead16(_oB_ & ~1)); }
798 OP(psxLHU) { doLoad(regs_, _Rt_, psxMemRead16(_oB_ & ~1)); }
799 OP(psxLW) { doLoad(regs_, _Rt_, psxMemRead32(_oB_ & ~3)); }
801 OP(psxLBe) { if (checkLD(regs_, _oB_, 0)) doLoad(regs_, _Rt_, (s8)psxMemRead8(_oB_)); }
802 OP(psxLBUe) { if (checkLD(regs_, _oB_, 0)) doLoad(regs_, _Rt_, psxMemRead8(_oB_)); }
803 OP(psxLHe) { if (checkLD(regs_, _oB_, 1)) doLoad(regs_, _Rt_, (s16)psxMemRead16(_oB_)); }
804 OP(psxLHUe) { if (checkLD(regs_, _oB_, 1)) doLoad(regs_, _Rt_, psxMemRead16(_oB_)); }
805 OP(psxLWe) { if (checkLD(regs_, _oB_, 3)) doLoad(regs_, _Rt_, psxMemRead32(_oB_)); }
807 static void doLWL(psxRegisters *regs, u32 rt, u32 addr) {
808 static const u32 LWL_MASK[4] = { 0xffffff, 0xffff, 0xff, 0 };
809 static const u32 LWL_SHIFT[4] = { 24, 16, 8, 0 };
810 u32 shift = addr & 3;
812 u32 oldval = regs->GPR.r[rt];
814 #ifdef HANDLE_LOAD_DELAY
815 int sel = regs->dloadSel;
816 if (regs->dloadReg[sel] == rt)
817 oldval = regs->dloadVal[sel];
819 mem = psxMemRead32(addr & ~3);
820 val = (oldval & LWL_MASK[shift]) | (mem << LWL_SHIFT[shift]);
821 doLoad(regs, rt, val);
824 Mem = 1234. Reg = abcd
826 0 4bcd (mem << 24) | (reg & 0x00ffffff)
827 1 34cd (mem << 16) | (reg & 0x0000ffff)
828 2 234d (mem << 8) | (reg & 0x000000ff)
829 3 1234 (mem ) | (reg & 0x00000000)
833 static void doLWR(psxRegisters *regs, u32 rt, u32 addr) {
834 static const u32 LWR_MASK[4] = { 0, 0xff000000, 0xffff0000, 0xffffff00 };
835 static const u32 LWR_SHIFT[4] = { 0, 8, 16, 24 };
836 u32 shift = addr & 3;
838 u32 oldval = regs->GPR.r[rt];
840 #ifdef HANDLE_LOAD_DELAY
841 int sel = regs->dloadSel;
842 if (regs->dloadReg[sel] == rt)
843 oldval = regs->dloadVal[sel];
845 mem = psxMemRead32(addr & ~3);
846 val = (oldval & LWR_MASK[shift]) | (mem >> LWR_SHIFT[shift]);
847 doLoad(regs, rt, val);
850 Mem = 1234. Reg = abcd
852 0 1234 (mem ) | (reg & 0x00000000)
853 1 a123 (mem >> 8) | (reg & 0xff000000)
854 2 ab12 (mem >> 16) | (reg & 0xffff0000)
855 3 abc1 (mem >> 24) | (reg & 0xffffff00)
859 OP(psxLWL) { doLWL(regs_, _Rt_, _oB_); }
860 OP(psxLWR) { doLWR(regs_, _Rt_, _oB_); }
862 OP(psxLWLe) { if (checkLD(regs_, _oB_ & ~3, 0)) doLWL(regs_, _Rt_, _oB_); }
863 OP(psxLWRe) { if (checkLD(regs_, _oB_ , 0)) doLWR(regs_, _Rt_, _oB_); }
865 OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ & 0xff); }
866 OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); }
867 OP(psxSW) { psxMemWrite32(_oB_, _rRt_); }
869 OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_ & 0xff); }
870 OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_ & 0xffff); }
871 OP(psxSWe) { if (checkST(regs_, _oB_, 3)) psxMemWrite32(_oB_, _rRt_); }
873 static void doSWL(psxRegisters *regs, u32 rt, u32 addr) {
874 u32 val = regs->GPR.r[rt];
876 case 0: psxMemWrite8( addr , val >> 24); break;
877 case 1: psxMemWrite16(addr & ~3, val >> 16); break;
878 case 2: // revisit: should be a single 24bit write
879 psxMemWrite16(addr & ~3, (val >> 8) & 0xffff);
880 psxMemWrite8( addr , val >> 24); break;
881 case 3: psxMemWrite32(addr & ~3, val); break;
884 Mem = 1234. Reg = abcd
886 0 123a (reg >> 24) | (mem & 0xffffff00)
887 1 12ab (reg >> 16) | (mem & 0xffff0000)
888 2 1abc (reg >> 8) | (mem & 0xff000000)
889 3 abcd (reg ) | (mem & 0x00000000)
893 static void doSWR(psxRegisters *regs, u32 rt, u32 addr) {
894 u32 val = regs->GPR.r[rt];
896 case 0: psxMemWrite32(addr , val); break;
897 case 1: // revisit: should be a single 24bit write
898 psxMemWrite8 (addr , val & 0xff);
899 psxMemWrite16(addr + 1, (val >> 8) & 0xffff); break;
900 case 2: psxMemWrite16(addr , val & 0xffff); break;
901 case 3: psxMemWrite8 (addr , val & 0xff); break;
905 Mem = 1234. Reg = abcd
907 0 abcd (reg ) | (mem & 0x00000000)
908 1 bcd4 (reg << 8) | (mem & 0x000000ff)
909 2 cd34 (reg << 16) | (mem & 0x0000ffff)
910 3 d234 (reg << 24) | (mem & 0x00ffffff)
914 OP(psxSWL) { doSWL(regs_, _Rt_, _oB_); }
915 OP(psxSWR) { doSWR(regs_, _Rt_, _oB_); }
917 OP(psxSWLe) { if (checkST(regs_, _oB_ & ~3, 0)) doSWL(regs_, _Rt_, _oB_); }
918 OP(psxSWRe) { if (checkST(regs_, _oB_ , 0)) doSWR(regs_, _Rt_, _oB_); }
920 /*********************************************************
921 * Moves between GPR and COPx *
922 * Format: OP rt, fs *
923 *********************************************************/
926 #ifdef DO_EXCEPTION_RESERVEDI
927 if (unlikely(0x00000417u & (1u << r)))
928 intExceptionInsn(regs_, R3000E_RI << 2);
930 doLoad(regs_, _Rt_, regs_->CP0.r[r]);
933 static void setupCop(u32 sr);
935 void MTC0(psxRegisters *regs_, int reg, u32 val) {
936 // SysPrintf("MTC0 %d: %x\n", reg, val);
939 if (unlikely((regs_->CP0.n.SR ^ val) & (1 << 16)))
940 psxMemOnIsolate((val >> 16) & 1);
941 if (unlikely((regs_->CP0.n.SR ^ val) & (7 << 29)))
943 regs_->CP0.n.SR = val;
944 psxTestSWInts(regs_, 1);
948 regs_->CP0.n.Cause &= ~0x0300;
949 regs_->CP0.n.Cause |= val & 0x0300;
950 psxTestSWInts(regs_, 0);
954 if ((regs_->CP0.n.DCIC ^ val) & 0xff800000)
955 log_unhandled("DCIC: %08x->%08x\n", regs_->CP0.n.DCIC, val);
958 regs_->CP0.r[reg] = val;
963 OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
966 static inline void psxNULLne(psxRegisters *regs) {
967 log_unhandled("unhandled op %08x @%08x\n", regs->code, regs->pc - 4);
970 /*********************************************************
971 * Unknown instruction (would generate an exception) *
973 *********************************************************/
977 #ifdef DO_EXCEPTION_RESERVEDI
978 intExceptionInsn(regs_, R3000E_RI << 2);
982 void gteNULL(struct psxCP2Regs *regs) {
983 psxRegisters *regs_ = (psxRegisters *)((u8 *)regs - offsetof(psxRegisters, CP2));
988 psxSPC[_Funct_](regs_, code);
994 u32 op2 = code & 0x1f;
999 case 0x08: psxNULL(regs_, code); break;
1000 case 0x10: psxRFE(regs_, code); break;
1001 default: psxNULLne(regs_); break;
1006 case 0x00: psxMFC0(regs_, code); break;
1007 case 0x04: psxMTC0(regs_, code); break;
1009 case 0x06: psxNULL(regs_, code); break; // CTC -> exception
1011 case 0x0c: log_unhandled("BC0 %08x @%08x\n", code, regs_->pc - 4);
1012 default: psxNULLne(regs_); break;
1017 // ??? what actually happens here?
1018 log_unhandled("COP1 %08x @%08x\n", code, regs_->pc - 4);
1022 u32 rt = _Rt_, rd = _Rd_, rs = _Rs_;
1024 psxCP2[_Funct_](®s_->CP2);
1028 case 0x00: doLoad(regs_, rt, MFC2(®s_->CP2, rd)); break; // MFC2
1029 case 0x02: doLoad(regs_, rt, regs_->CP2C.r[rd]); break; // CFC2
1030 case 0x04: MTC2(®s_->CP2, regs_->GPR.r[rt], rd); break; // MTC2
1031 case 0x06: CTC2(®s_->CP2, regs_->GPR.r[rt], rd); break; // CTC2
1033 case 0x0c: log_unhandled("BC2 %08x @%08x\n", code, regs_->pc - 4);
1034 default: psxNULLne(regs_); break;
1041 psxCOP2(regs_, code);
1045 MTC2(®s_->CP2, psxMemRead32(_oB_), _Rt_);
1050 gteLWC2(regs_, code);
1053 OP(gteLWC2e_stall) {
1055 if (checkLD(regs_, _oB_, 3))
1056 MTC2(®s_->CP2, psxMemRead32(_oB_), _Rt_);
1060 psxMemWrite32(_oB_, MFC2(®s_->CP2, _Rt_));
1065 gteSWC2(regs_, code);
1068 OP(gteSWC2e_stall) {
1070 if (checkST(regs_, _oB_, 3))
1071 gteSWC2(regs_, code);
1075 // ??? what actually happens here?
1076 log_unhandled("COP3 %08x @%08x\n", code, regs_->pc - 4);
1080 log_unhandled("disabled cop%d @%08x\n", (code >> 26) & 3, regs_->pc - 4);
1081 #ifdef DO_EXCEPTION_RESERVEDI
1082 intExceptionInsn(regs_, R3000E_CpU << 2);
1087 log_unhandled("LWCx %08x @%08x\n", code, regs_->pc - 4);
1088 checkLD(regs_, _oB_, 3);
1092 // does this write something to memory?
1093 log_unhandled("SWCx %08x @%08x\n", code, regs_->pc - 4);
1094 checkST(regs_, _oB_, 3);
1100 case 0x10: psxBLTZAL(regs_, code); break;
1101 case 0x11: psxBGEZAL(regs_, code); break;
1104 psxBGEZ(regs_, code);
1106 psxBLTZ(regs_, code);
1112 if (unlikely(!Config.HLE)) {
1113 psxSWCx(regs_, code);
1116 hleCode = code & 0x03ffffff;
1117 if (hleCode >= (sizeof(psxHLEt) / sizeof(psxHLEt[0]))) {
1118 psxSWCx(regs_, code);
1126 static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = {
1127 psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ,
1128 psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI ,
1129 psxCOP0 , psxCOPd , psxCOP2, psxCOPd, psxNULL, psxNULL, psxNULL, psxNULL,
1130 psxNULL , psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
1131 psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL,
1132 psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL,
1133 psxLWCx , psxLWCx , gteLWC2, psxLWCx , psxNULL, psxNULL, psxNULL, psxNULL,
1134 psxSWCx , psxSWCx , gteSWC2, psxHLE , psxNULL, psxNULL, psxNULL, psxNULL,
1137 static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code) = {
1138 psxSLL , psxNULL , psxSRL , psxSRA , psxSLLV , psxNULL , psxSRLV, psxSRAV,
1139 psxJR , psxJALR , psxNULL, psxNULL, psxSYSCALL, psxBREAK, psxNULL, psxNULL,
1140 psxMFHI, psxMTHI , psxMFLO, psxMTLO, psxNULL , psxNULL , psxNULL, psxNULL,
1141 psxMULT, psxMULTU, psxDIV , psxDIVU, psxNULL , psxNULL , psxNULL, psxNULL,
1142 psxADD , psxADDU , psxSUB , psxSUBU, psxAND , psxOR , psxXOR , psxNOR ,
1143 psxNULL, psxNULL , psxSLT , psxSLTU, psxNULL , psxNULL , psxNULL, psxNULL,
1144 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL,
1145 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL
1148 void (*psxCP2[64])(struct psxCP2Regs *regs) = {
1149 gteNULL , gteRTPS , gteNULL , gteNULL, gteNULL, gteNULL , gteNCLIP, gteNULL, // 00
1150 gteNULL , gteNULL , gteNULL , gteNULL, gteOP , gteNULL , gteNULL , gteNULL, // 08
1151 gteDPCS , gteINTPL, gteMVMVA, gteNCDS, gteCDP , gteNULL , gteNCDT , gteNULL, // 10
1152 gteNULL , gteNULL , gteNULL , gteNCCS, gteCC , gteNULL , gteNCS , gteNULL, // 18
1153 gteNCT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 20
1154 gteSQR , gteDCPL , gteDPCT , gteNULL, gteNULL, gteAVSZ3, gteAVSZ4, gteNULL, // 28
1155 gteRTPT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 30
1156 gteNULL , gteNULL , gteNULL , gteNULL, gteNULL, gteGPF , gteGPL , gteNCCT // 38
1159 ///////////////////////////////////////////
1161 static int intInit() {
1165 static void intReset() {
1166 dloadClear(&psxRegs);
1167 psxRegs.subCycle = 0;
1170 static inline void execI_(u8 **memRLUT, psxRegisters *regs) {
1177 regs->code = fetch(regs, memRLUT, pc);
1178 psxBSC[regs->code >> 26](regs, regs->code);
1181 static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
1187 if (execBreakCheck(regs, pc))
1191 regs->code = fetch(regs, memRLUT, pc);
1192 psxBSC[regs->code >> 26](regs, regs->code);
1195 static void intExecute() {
1196 psxRegisters *regs_ = &psxRegs;
1197 u8 **memRLUT = psxMemRLUT;
1201 execI_(memRLUT, regs_);
1204 static void intExecuteBp() {
1205 psxRegisters *regs_ = &psxRegs;
1206 u8 **memRLUT = psxMemRLUT;
1210 execIbp(memRLUT, regs_);
1213 void intExecuteBlock(enum blockExecCaller caller) {
1214 psxRegisters *regs_ = &psxRegs;
1215 u8 **memRLUT = psxMemRLUT;
1219 execI_(memRLUT, regs_);
1222 static void intClear(u32 Addr, u32 Size) {
1225 static void intNotify(enum R3000Anote note, void *data) {
1227 case R3000ACPU_NOTIFY_BEFORE_SAVE:
1228 dloadFlush(&psxRegs);
1230 case R3000ACPU_NOTIFY_AFTER_LOAD:
1231 dloadClear(&psxRegs);
1232 psxRegs.subCycle = 0;
1233 setupCop(psxRegs.CP0.n.SR);
1235 case R3000ACPU_NOTIFY_CACHE_ISOLATED: // Armored Core?
1236 memset(&ICache, 0xff, sizeof(ICache));
1238 case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
1243 static void setupCop(u32 sr)
1245 if (sr & (1u << 29))
1246 psxBSC[17] = psxCOP1;
1248 psxBSC[17] = psxCOPd;
1249 if (sr & (1u << 30))
1250 psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall;
1252 psxBSC[18] = psxCOPd;
1253 if (sr & (1u << 31))
1254 psxBSC[19] = psxCOP3;
1256 psxBSC[19] = psxCOPd;
1259 void intApplyConfig() {
1262 assert(psxSPC[16] == psxMFHI || psxSPC[16] == psxMFHI_stall);
1263 assert(psxSPC[18] == psxMFLO || psxSPC[18] == psxMFLO_stall);
1264 assert(psxSPC[24] == psxMULT || psxSPC[24] == psxMULT_stall);
1265 assert(psxSPC[25] == psxMULTU || psxSPC[25] == psxMULTU_stall);
1266 assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall);
1267 assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall);
1269 if (Config.DisableStalls) {
1270 psxBSC[18] = psxCOP2;
1271 psxBSC[50] = gteLWC2;
1272 psxBSC[58] = gteSWC2;
1273 psxSPC[16] = psxMFHI;
1274 psxSPC[18] = psxMFLO;
1275 psxSPC[24] = psxMULT;
1276 psxSPC[25] = psxMULTU;
1277 psxSPC[26] = psxDIV;
1278 psxSPC[27] = psxDIVU;
1280 psxBSC[18] = psxCOP2_stall;
1281 psxBSC[50] = gteLWC2_stall;
1282 psxBSC[58] = gteSWC2_stall;
1283 psxSPC[16] = psxMFHI_stall;
1284 psxSPC[18] = psxMFLO_stall;
1285 psxSPC[24] = psxMULT_stall;
1286 psxSPC[25] = psxMULTU_stall;
1287 psxSPC[26] = psxDIV_stall;
1288 psxSPC[27] = psxDIVU_stall;
1290 setupCop(psxRegs.CP0.n.SR);
1292 if (Config.PreciseExceptions) {
1293 psxBSC[0x20] = psxLBe;
1294 psxBSC[0x21] = psxLHe;
1295 psxBSC[0x22] = psxLWLe;
1296 psxBSC[0x23] = psxLWe;
1297 psxBSC[0x24] = psxLBUe;
1298 psxBSC[0x25] = psxLHUe;
1299 psxBSC[0x26] = psxLWRe;
1300 psxBSC[0x28] = psxSBe;
1301 psxBSC[0x29] = psxSHe;
1302 psxBSC[0x2a] = psxSWLe;
1303 psxBSC[0x2b] = psxSWe;
1304 psxBSC[0x2e] = psxSWRe;
1305 psxBSC[0x32] = gteLWC2e_stall;
1306 psxBSC[0x3a] = gteSWC2e_stall;
1307 psxSPC[0x08] = psxJRe;
1308 psxSPC[0x09] = psxJALRe;
1309 psxInt.Execute = intExecuteBp;
1311 psxBSC[0x20] = psxLB;
1312 psxBSC[0x21] = psxLH;
1313 psxBSC[0x22] = psxLWL;
1314 psxBSC[0x23] = psxLW;
1315 psxBSC[0x24] = psxLBU;
1316 psxBSC[0x25] = psxLHU;
1317 psxBSC[0x26] = psxLWR;
1318 psxBSC[0x28] = psxSB;
1319 psxBSC[0x29] = psxSH;
1320 psxBSC[0x2a] = psxSWL;
1321 psxBSC[0x2b] = psxSW;
1322 psxBSC[0x2e] = psxSWR;
1323 // LWC2, SWC2 handled by Config.DisableStalls
1324 psxSPC[0x08] = psxJR;
1325 psxSPC[0x09] = psxJALR;
1326 psxInt.Execute = intExecute;
1329 // the dynarec may occasionally call the interpreter, in such a case the
1330 // cache won't work (cache only works right if all fetches go through it)
1331 if (!Config.icache_emulation || psxCpu != &psxInt)
1332 fetch = fetchNoCache;
1334 fetch = fetchICache;
1336 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
1337 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
1338 psxRegs.subCycleStep = 0x10000 * cycle_mult / 100;
1341 static void intShutdown() {
1342 dloadClear(&psxRegs);
1345 // single step (may do several ops in case of a branch or load delay)
1346 // called by asm/dynarec
1347 void execI(psxRegisters *regs) {
1349 execIbp(psxMemRLUT, regs);
1350 } while (regs->dloadReg[0] || regs->dloadReg[1]);
1353 R3000Acpu psxInt = {