4 ! Master Vector Base Table at 0x06000000
6 .long mstart /* Cold Start PC */
7 .long 0x06040000 /* Cold Start SP */
8 .long mstart /* Manual Reset PC */
9 .long 0x06040000 /* Manual Reset SP */
10 .long master_e4 /* Illegal instruction */
11 .long master_e5 /* reserved */
12 .long master_e6 /* Invalid slot instruction */
13 .long master_e7 /* reserved */
14 .long master_e8 /* reserved */
15 .long master_e9 /* CPU address error */
16 .long master_e10 /* DMA address error */
17 .long master_e11 /* NMI vector */
18 .long master_e12 /* User break vector */
20 .long main_err /* reserved */
23 .long main_err /* TRAPA #32-63 */
25 .long main_irq /* Level 1 IRQ */
26 .long main_irq /* Level 2 & 3 IRQ's */
27 .long main_irq /* Level 4 & 5 IRQ's */
28 .long main_irq /* PWM interupt */
29 .long main_irq /* Command interupt */
30 .long main_irq /* H Blank interupt */
31 .long main_irq /* V Blank interupt */
32 .long main_irq /* Reset Button */
34 .long main_err /* peripherals */
37 ! Slave Vector Base Table at 0x06000200
39 .long sstart /* Cold Start PC */
40 .long 0x0603f800 /* Cold Start SP */
41 .long sstart /* Manual Reset PC */
42 .long 0x0603f800 /* Manual Reset SP */
43 .long slave_e4 /* Illegal instruction */
44 .long slave_e5 /* reserved */
45 .long slave_e6 /* Invalid slot instruction */
46 .long slave_e7 /* reserved */
47 .long slave_e8 /* reserved */
48 .long slave_e9 /* CPU address error */
49 .long slave_e10 /* DMA address error */
50 .long slave_e11 /* NMI vector */
51 .long slave_e12 /* User break vector */
53 .long slave_err /* reserved */
56 .long slave_err /* TRAPA #32-63 */
58 .long slave_irq /* Level 1 IRQ */
59 .long slave_irq /* Level 2 & 3 IRQ's */
60 .long slave_irq /* Level 4 & 5 IRQ's */
61 .long slave_irq /* PWM interupt */
62 .long slave_irq /* Command interupt */
63 .long slave_irq /* H Blank interupt */
64 .long slave_irq /* V Blank interupt */
65 .long slave_irq /* Reset Button */
67 .long slave_err /* peripherals */
71 .macro mov_bc const ofs reg
76 mov.b r0, @(\ofs, \reg)
80 ! Stacks set up by BIOS
82 ! The main SH2 starts here at 0x06000400
88 ! The slave SH2 starts here at 0x06000404
95 ! cache init - done by BIOS with single 0x11 write
96 mov.l l_cctl, r1 /* cache */
97 mov_bc 0x00, 0, r1 /* disable */
98 mov.b @r1, r0 /* dummy read */
99 mov_bc 0x10, 0, r1 /* purge */
101 mov_bc 0x01, 0, r1 /* enable */
103 mov #0xd0, r0 /* enable irqs */
112 stc sr, r0 /* SR holds IRQ level in I3-I0 */
123 mov.w r0, @(0x14, gbr) /* ack */
124 mov.b @(7, gbr), r0 /* RV */
128 ! Try to set FTOB pin that's wired to 32X hard reset.
129 ! Doesn't seem to be working right though, it somehow disturbs
130 ! 68k reset PC fetch which mysteriously ends up at range
131 ! 2c8 - 304 in multiples of 4, proportionally to reset delay
132 ! (0 - ~300 (?) sh2 cycles). Longer delay just hangs, presumably
135 mov_bc 0xf1, 7, r1 /* TOCR sel OCRB, pin on B match */
137 mov.b r0, @(4, r1) /* OCRB H - output compare B */
138 mov.b r0, @(5, r1) /* OCRB L */
139 mov.b r0, @(2, r1) /* FRC H */
140 mov.b r0, @(3, r1) /* FRC L */
142 ! sleep - docs say not to use
183 .macro exc_master num
216 mov.w r0, @(0x2c, gbr)
222 mov.w r0, @(0x2e, gbr)
234 ! vim:ts=8:sw=8:expandtab