1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - gr4300.c *
3 * Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
4 * Copyright (C) 2002 Hacktarux *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
23 #include "interpret.h"
26 #include "api/debugger.h"
28 #include "r4300/r4300.h"
29 #include "r4300/macros.h"
30 #include "r4300/interupt.h"
31 #include "r4300/ops.h"
32 #include "r4300/recomph.h"
33 #include "r4300/exception.h"
35 #include "memory/memory.h"
37 extern unsigned int op;
39 static precomp_instr fake_instr;
41 static int eax, ebx, ecx, edx, esp, ebp, esi, edi;
46 /* static functions */
48 static void genupdate_count(unsigned int addr)
52 mov_reg32_imm32(EAX, addr);
53 sub_reg32_m32(EAX, (unsigned int*)(&last_addr));
54 shr_reg32_imm8(EAX, 1);
55 add_m32_reg32((unsigned int*)(&Count), EAX);
57 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
58 mov_reg32_imm32(EAX, (unsigned int)update_count);
62 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
63 mov_reg32_imm32(EAX, (unsigned int)update_count);
68 static void gencheck_interupt(unsigned int instr_structure)
70 mov_eax_memoffs32(&next_interupt);
71 cmp_reg32_m32(EAX, &Count);
73 mov_m32_imm32((unsigned int*)(&PC), instr_structure); // 10
74 mov_reg32_imm32(EAX, (unsigned int)gen_interupt); // 5
78 static void gencheck_interupt_out(unsigned int addr)
80 mov_eax_memoffs32(&next_interupt);
81 cmp_reg32_m32(EAX, &Count);
83 mov_m32_imm32((unsigned int*)(&fake_instr.addr), addr);
84 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(&fake_instr));
85 mov_reg32_imm32(EAX, (unsigned int)gen_interupt);
89 static void genbeq_test(void)
91 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
92 int rt_64bit = is64((unsigned int *)dst->f.i.rt);
94 if (!rs_64bit && !rt_64bit)
96 int rs = allocate_register((unsigned int *)dst->f.i.rs);
97 int rt = allocate_register((unsigned int *)dst->f.i.rt);
99 cmp_reg32_reg32(rs, rt);
101 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
102 jmp_imm_short(10); // 2
103 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
105 else if (rs_64bit == -1)
107 int rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
108 int rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
110 cmp_reg32_m32(rt1, (unsigned int *)dst->f.i.rs);
112 cmp_reg32_m32(rt2, ((unsigned int *)dst->f.i.rs)+1); // 6
114 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
115 jmp_imm_short(10); // 2
116 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
118 else if (rt_64bit == -1)
120 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
121 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
123 cmp_reg32_m32(rs1, (unsigned int *)dst->f.i.rt);
125 cmp_reg32_m32(rs2, ((unsigned int *)dst->f.i.rt)+1); // 6
127 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
128 jmp_imm_short(10); // 2
129 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
133 int rs1, rs2, rt1, rt2;
136 rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
137 rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
138 rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
139 rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
143 rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
144 rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
145 rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
146 rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
148 cmp_reg32_reg32(rs1, rt1);
150 cmp_reg32_reg32(rs2, rt2); // 2
152 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
153 jmp_imm_short(10); // 2
154 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
158 static void genbne_test(void)
160 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
161 int rt_64bit = is64((unsigned int *)dst->f.i.rt);
163 if (!rs_64bit && !rt_64bit)
165 int rs = allocate_register((unsigned int *)dst->f.i.rs);
166 int rt = allocate_register((unsigned int *)dst->f.i.rt);
168 cmp_reg32_reg32(rs, rt);
170 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
171 jmp_imm_short(10); // 2
172 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
174 else if (rs_64bit == -1)
176 int rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
177 int rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
179 cmp_reg32_m32(rt1, (unsigned int *)dst->f.i.rs);
181 cmp_reg32_m32(rt2, ((unsigned int *)dst->f.i.rs)+1); // 6
183 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
184 jmp_imm_short(10); // 2
185 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
187 else if (rt_64bit == -1)
189 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
190 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
192 cmp_reg32_m32(rs1, (unsigned int *)dst->f.i.rt);
194 cmp_reg32_m32(rs2, ((unsigned int *)dst->f.i.rt)+1); // 6
196 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
197 jmp_imm_short(10); // 2
198 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
202 int rs1, rs2, rt1, rt2;
205 rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
206 rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
207 rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
208 rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
212 rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
213 rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
214 rt1 = allocate_64_register1((unsigned int *)dst->f.i.rt);
215 rt2 = allocate_64_register2((unsigned int *)dst->f.i.rt);
217 cmp_reg32_reg32(rs1, rt1);
219 cmp_reg32_reg32(rs2, rt2); // 2
221 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
222 jmp_imm_short(10); // 2
223 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
227 static void genblez_test(void)
229 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
233 int rs = allocate_register((unsigned int *)dst->f.i.rs);
235 cmp_reg32_imm32(rs, 0);
237 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
238 jmp_imm_short(10); // 2
239 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
241 else if (rs_64bit == -1)
243 cmp_m32_imm32(((unsigned int *)dst->f.i.rs)+1, 0);
246 cmp_m32_imm32((unsigned int *)dst->f.i.rs, 0); // 10
248 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
249 jmp_imm_short(10); // 2
250 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
254 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
255 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
257 cmp_reg32_imm32(rs2, 0);
260 cmp_reg32_imm32(rs1, 0); // 6
262 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
263 jmp_imm_short(10); // 2
264 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
268 static void genbgtz_test(void)
270 int rs_64bit = is64((unsigned int *)dst->f.i.rs);
274 int rs = allocate_register((unsigned int *)dst->f.i.rs);
276 cmp_reg32_imm32(rs, 0);
278 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
279 jmp_imm_short(10); // 2
280 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
282 else if (rs_64bit == -1)
284 cmp_m32_imm32(((unsigned int *)dst->f.i.rs)+1, 0);
287 cmp_m32_imm32((unsigned int *)dst->f.i.rs, 0); // 10
289 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
290 jmp_imm_short(10); // 2
291 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
295 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
296 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
298 cmp_reg32_imm32(rs2, 0);
301 cmp_reg32_imm32(rs1, 0); // 6
303 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10
304 jmp_imm_short(10); // 2
305 mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10
310 /* global functions */
312 void gennotcompiled(void)
314 free_all_registers();
317 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst));
318 mov_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED);
322 void genlink_subblock(void)
324 free_all_registers();
331 free_all_registers();
332 mov_m32_reg32((unsigned int*)&eax, EAX);
333 mov_m32_reg32((unsigned int*)&ebx, EBX);
334 mov_m32_reg32((unsigned int*)&ecx, ECX);
335 mov_m32_reg32((unsigned int*)&edx, EDX);
336 mov_m32_reg32((unsigned int*)&esp, ESP);
337 mov_m32_reg32((unsigned int*)&ebp, EBP);
338 mov_m32_reg32((unsigned int*)&esi, ESI);
339 mov_m32_reg32((unsigned int*)&edi, EDI);
341 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst));
342 mov_m32_imm32((unsigned int*)(&op), (unsigned int)(src));
343 mov_reg32_imm32(EAX, (unsigned int) CoreCompareCallback);
346 mov_reg32_m32(EAX, (unsigned int*)&eax);
347 mov_reg32_m32(EBX, (unsigned int*)&ebx);
348 mov_reg32_m32(ECX, (unsigned int*)&ecx);
349 mov_reg32_m32(EDX, (unsigned int*)&edx);
350 mov_reg32_m32(ESP, (unsigned int*)&esp);
351 mov_reg32_m32(EBP, (unsigned int*)&ebp);
352 mov_reg32_m32(ESI, (unsigned int*)&esi);
353 mov_reg32_m32(EDI, (unsigned int*)&edi);
357 void gencallinterp(unsigned long addr, int jump)
359 free_all_registers();
362 mov_m32_imm32((unsigned int*)(&dyna_interp), 1);
363 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst));
364 mov_reg32_imm32(EAX, addr);
368 mov_m32_imm32((unsigned int*)(&dyna_interp), 0);
369 mov_reg32_imm32(EAX, (unsigned int)dyna_jump);
374 void gendelayslot(void)
376 mov_m32_imm32(&delay_slot, 1);
379 free_all_registers();
380 genupdate_count(dst->addr+4);
382 mov_m32_imm32(&delay_slot, 0);
387 gencallinterp((unsigned int)cached_interpreter_table.NI, 0);
390 void genreserved(void)
392 gencallinterp((unsigned int)cached_interpreter_table.RESERVED, 0);
395 void genfin_block(void)
397 gencallinterp((unsigned int)cached_interpreter_table.FIN_BLOCK, 0);
400 void gencheck_interupt_reg(void) // addr is in EAX
402 mov_reg32_m32(EBX, &next_interupt);
403 cmp_reg32_m32(EBX, &Count);
405 mov_memoffs32_eax((unsigned int*)(&fake_instr.addr)); // 5
406 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(&fake_instr)); // 10
407 mov_reg32_imm32(EAX, (unsigned int)gen_interupt); // 5
408 call_reg32(EAX); // 2
418 gencallinterp((unsigned int)cached_interpreter_table.J, 1);
422 if (((dst->addr & 0xFFF) == 0xFFC &&
423 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
425 gencallinterp((unsigned int)cached_interpreter_table.J, 1);
430 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
432 mov_m32_imm32(&last_addr, naddr);
433 gencheck_interupt((unsigned int)&actual->block[(naddr-actual->start)/4]);
440 #ifdef INTERPRET_J_OUT
441 gencallinterp((unsigned int)cached_interpreter_table.J_OUT, 1);
445 if (((dst->addr & 0xFFF) == 0xFFC &&
446 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
448 gencallinterp((unsigned int)cached_interpreter_table.J_OUT, 1);
453 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
455 mov_m32_imm32(&last_addr, naddr);
456 gencheck_interupt_out(naddr);
457 mov_m32_imm32(&jump_to_address, naddr);
458 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
459 mov_reg32_imm32(EAX, (unsigned int)jump_to_func);
466 #ifdef INTERPRET_J_IDLE
467 gencallinterp((unsigned int)cached_interpreter_table.J_IDLE, 1);
469 if (((dst->addr & 0xFFF) == 0xFFC &&
470 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
472 gencallinterp((unsigned int)cached_interpreter_table.J_IDLE, 1);
476 mov_eax_memoffs32((unsigned int *)(&next_interupt));
477 sub_reg32_m32(EAX, (unsigned int *)(&Count));
478 cmp_reg32_imm8(EAX, 3);
481 and_eax_imm32(0xFFFFFFFC); // 5
482 add_m32_reg32((unsigned int *)(&Count), EAX); // 6
491 gencallinterp((unsigned int)cached_interpreter_table.JAL, 1);
495 if (((dst->addr & 0xFFF) == 0xFFC &&
496 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
498 gencallinterp((unsigned int)cached_interpreter_table.JAL, 1);
504 mov_m32_imm32((unsigned int *)(reg + 31), dst->addr + 4);
505 if (((dst->addr + 4) & 0x80000000))
506 mov_m32_imm32((unsigned int *)(®[31])+1, 0xFFFFFFFF);
508 mov_m32_imm32((unsigned int *)(®[31])+1, 0);
510 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
512 mov_m32_imm32(&last_addr, naddr);
513 gencheck_interupt((unsigned int)&actual->block[(naddr-actual->start)/4]);
518 void genjal_out(void)
520 #ifdef INTERPRET_JAL_OUT
521 gencallinterp((unsigned int)cached_interpreter_table.JAL_OUT, 1);
525 if (((dst->addr & 0xFFF) == 0xFFC &&
526 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
528 gencallinterp((unsigned int)cached_interpreter_table.JAL_OUT, 1);
534 mov_m32_imm32((unsigned int *)(reg + 31), dst->addr + 4);
535 if (((dst->addr + 4) & 0x80000000))
536 mov_m32_imm32((unsigned int *)(®[31])+1, 0xFFFFFFFF);
538 mov_m32_imm32((unsigned int *)(®[31])+1, 0);
540 naddr = ((dst-1)->f.j.inst_index<<2) | (dst->addr & 0xF0000000);
542 mov_m32_imm32(&last_addr, naddr);
543 gencheck_interupt_out(naddr);
544 mov_m32_imm32(&jump_to_address, naddr);
545 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
546 mov_reg32_imm32(EAX, (unsigned int)jump_to_func);
551 void genjal_idle(void)
553 #ifdef INTERPRET_JAL_IDLE
554 gencallinterp((unsigned int)cached_interpreter_table.JAL_IDLE, 1);
556 if (((dst->addr & 0xFFF) == 0xFFC &&
557 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
559 gencallinterp((unsigned int)cached_interpreter_table.JAL_IDLE, 1);
563 mov_eax_memoffs32((unsigned int *)(&next_interupt));
564 sub_reg32_m32(EAX, (unsigned int *)(&Count));
565 cmp_reg32_imm8(EAX, 3);
568 and_eax_imm32(0xFFFFFFFC);
569 add_m32_reg32((unsigned int *)(&Count), EAX);
577 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
582 mov_m32_imm32(&last_addr, dst->addr + (dst-1)->f.i.immediate*4);
583 gencheck_interupt((unsigned int)(dst + (dst-1)->f.i.immediate));
584 jmp(dst->addr + (dst-1)->f.i.immediate*4);
588 mov_m32_imm32(&last_addr, dst->addr + 4);
589 gencheck_interupt((unsigned int)(dst + 1));
596 gencallinterp((unsigned int)cached_interpreter_table.BEQ, 1);
598 if (((dst->addr & 0xFFF) == 0xFFC &&
599 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
601 gencallinterp((unsigned int)cached_interpreter_table.BEQ, 1);
611 void gentest_out(void)
613 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
618 mov_m32_imm32(&last_addr, dst->addr + (dst-1)->f.i.immediate*4);
619 gencheck_interupt_out(dst->addr + (dst-1)->f.i.immediate*4);
620 mov_m32_imm32(&jump_to_address, dst->addr + (dst-1)->f.i.immediate*4);
621 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
622 mov_reg32_imm32(EAX, (unsigned int)jump_to_func);
627 mov_m32_imm32(&last_addr, dst->addr + 4);
628 gencheck_interupt((unsigned int)(dst + 1));
632 void genbeq_out(void)
634 #ifdef INTERPRET_BEQ_OUT
635 gencallinterp((unsigned int)cached_interpreter_table.BEQ_OUT, 1);
637 if (((dst->addr & 0xFFF) == 0xFFC &&
638 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
640 gencallinterp((unsigned int)cached_interpreter_table.BEQ_OUT, 1);
650 void gentest_idle(void)
654 reg = lru_register();
657 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
662 mov_reg32_m32(reg, (unsigned int *)(&next_interupt));
663 sub_reg32_m32(reg, (unsigned int *)(&Count));
664 cmp_reg32_imm8(reg, 5);
667 sub_reg32_imm32(reg, 2); // 6
668 and_reg32_imm32(reg, 0xFFFFFFFC); // 6
669 add_m32_reg32((unsigned int *)(&Count), reg); // 6
674 void genbeq_idle(void)
676 #ifdef INTERPRET_BEQ_IDLE
677 gencallinterp((unsigned int)cached_interpreter_table.BEQ_IDLE, 1);
679 if (((dst->addr & 0xFFF) == 0xFFC &&
680 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
682 gencallinterp((unsigned int)cached_interpreter_table.BEQ_IDLE, 1);
695 gencallinterp((unsigned int)cached_interpreter_table.BNE, 1);
697 if (((dst->addr & 0xFFF) == 0xFFC &&
698 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
700 gencallinterp((unsigned int)cached_interpreter_table.BNE, 1);
710 void genbne_out(void)
712 #ifdef INTERPRET_BNE_OUT
713 gencallinterp((unsigned int)cached_interpreter_table.BNE_OUT, 1);
715 if (((dst->addr & 0xFFF) == 0xFFC &&
716 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
718 gencallinterp((unsigned int)cached_interpreter_table.BNE_OUT, 1);
728 void genbne_idle(void)
730 #ifdef INTERPRET_BNE_IDLE
731 gencallinterp((unsigned int)cached_interpreter_table.BNE_IDLE, 1);
733 if (((dst->addr & 0xFFF) == 0xFFC &&
734 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
736 gencallinterp((unsigned int)cached_interpreter_table.BNE_IDLE, 1);
748 #ifdef INTERPRET_BLEZ
749 gencallinterp((unsigned int)cached_interpreter_table.BLEZ, 1);
751 if (((dst->addr & 0xFFF) == 0xFFC &&
752 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
754 gencallinterp((unsigned int)cached_interpreter_table.BLEZ, 1);
764 void genblez_out(void)
766 #ifdef INTERPRET_BLEZ_OUT
767 gencallinterp((unsigned int)cached_interpreter_table.BLEZ_OUT, 1);
769 if (((dst->addr & 0xFFF) == 0xFFC &&
770 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
772 gencallinterp((unsigned int)cached_interpreter_table.BLEZ_OUT, 1);
782 void genblez_idle(void)
784 #ifdef INTERPRET_BLEZ_IDLE
785 gencallinterp((unsigned int)cached_interpreter_table.BLEZ_IDLE, 1);
787 if (((dst->addr & 0xFFF) == 0xFFC &&
788 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
790 gencallinterp((unsigned int)cached_interpreter_table.BLEZ_IDLE, 1);
802 #ifdef INTERPRET_BGTZ
803 gencallinterp((unsigned int)cached_interpreter_table.BGTZ, 1);
805 if (((dst->addr & 0xFFF) == 0xFFC &&
806 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
808 gencallinterp((unsigned int)cached_interpreter_table.BGTZ, 1);
818 void genbgtz_out(void)
820 #ifdef INTERPRET_BGTZ_OUT
821 gencallinterp((unsigned int)cached_interpreter_table.BGTZ_OUT, 1);
823 if (((dst->addr & 0xFFF) == 0xFFC &&
824 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
826 gencallinterp((unsigned int)cached_interpreter_table.BGTZ_OUT, 1);
836 void genbgtz_idle(void)
838 #ifdef INTERPRET_BGTZ_IDLE
839 gencallinterp((unsigned int)cached_interpreter_table.BGTZ_IDLE, 1);
841 if (((dst->addr & 0xFFF) == 0xFFC &&
842 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
844 gencallinterp((unsigned int)cached_interpreter_table.BGTZ_IDLE, 1);
856 #ifdef INTERPRET_ADDI
857 gencallinterp((unsigned int)cached_interpreter_table.ADDI, 0);
859 int rs = allocate_register((unsigned int *)dst->f.i.rs);
860 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
862 mov_reg32_reg32(rt, rs);
863 add_reg32_imm32(rt,(int)dst->f.i.immediate);
869 #ifdef INTERPRET_ADDIU
870 gencallinterp((unsigned int)cached_interpreter_table.ADDIU, 0);
872 int rs = allocate_register((unsigned int *)dst->f.i.rs);
873 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
875 mov_reg32_reg32(rt, rs);
876 add_reg32_imm32(rt,(int)dst->f.i.immediate);
882 #ifdef INTERPRET_SLTI
883 gencallinterp((unsigned int)cached_interpreter_table.SLTI, 0);
885 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
886 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
887 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
888 long long imm = (long long)dst->f.i.immediate;
890 cmp_reg32_imm32(rs2, (unsigned int)(imm >> 32));
893 cmp_reg32_imm32(rs1, (unsigned int)imm); // 6
895 mov_reg32_imm32(rt, 0); // 5
896 jmp_imm_short(5); // 2
897 mov_reg32_imm32(rt, 1); // 5
903 #ifdef INTERPRET_SLTIU
904 gencallinterp((unsigned int)cached_interpreter_table.SLTIU, 0);
906 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
907 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
908 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
909 long long imm = (long long)dst->f.i.immediate;
911 cmp_reg32_imm32(rs2, (unsigned int)(imm >> 32));
914 cmp_reg32_imm32(rs1, (unsigned int)imm); // 6
916 mov_reg32_imm32(rt, 0); // 5
917 jmp_imm_short(5); // 2
918 mov_reg32_imm32(rt, 1); // 5
924 #ifdef INTERPRET_ANDI
925 gencallinterp((unsigned int)cached_interpreter_table.ANDI, 0);
927 int rs = allocate_register((unsigned int *)dst->f.i.rs);
928 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
930 mov_reg32_reg32(rt, rs);
931 and_reg32_imm32(rt, (unsigned short)dst->f.i.immediate);
938 gencallinterp((unsigned int)cached_interpreter_table.ORI, 0);
940 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
941 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
942 int rt1 = allocate_64_register1_w((unsigned int *)dst->f.i.rt);
943 int rt2 = allocate_64_register2_w((unsigned int *)dst->f.i.rt);
945 mov_reg32_reg32(rt1, rs1);
946 mov_reg32_reg32(rt2, rs2);
947 or_reg32_imm32(rt1, (unsigned short)dst->f.i.immediate);
953 #ifdef INTERPRET_XORI
954 gencallinterp((unsigned int)cached_interpreter_table.XORI, 0);
956 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
957 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
958 int rt1 = allocate_64_register1_w((unsigned int *)dst->f.i.rt);
959 int rt2 = allocate_64_register2_w((unsigned int *)dst->f.i.rt);
961 mov_reg32_reg32(rt1, rs1);
962 mov_reg32_reg32(rt2, rs2);
963 xor_reg32_imm32(rt1, (unsigned short)dst->f.i.immediate);
970 gencallinterp((unsigned int)cached_interpreter_table.LUI, 0);
972 int rt = allocate_register_w((unsigned int *)dst->f.i.rt);
974 mov_reg32_imm32(rt, (unsigned int)dst->f.i.immediate << 16);
980 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
986 mov_m32_imm32(&last_addr, dst->addr + (dst-1)->f.i.immediate*4);
987 gencheck_interupt((unsigned int)(dst + (dst-1)->f.i.immediate));
988 jmp(dst->addr + (dst-1)->f.i.immediate*4);
992 genupdate_count(dst->addr+4);
993 mov_m32_imm32(&last_addr, dst->addr + 4);
994 gencheck_interupt((unsigned int)(dst + 1));
1000 #ifdef INTERPRET_BEQL
1001 gencallinterp((unsigned int)cached_interpreter_table.BEQL, 1);
1003 if (((dst->addr & 0xFFF) == 0xFFC &&
1004 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1006 gencallinterp((unsigned int)cached_interpreter_table.BEQL, 1);
1011 free_all_registers();
1016 void gentestl_out(void)
1018 cmp_m32_imm32((unsigned int *)(&branch_taken), 0);
1024 mov_m32_imm32(&last_addr, dst->addr + (dst-1)->f.i.immediate*4);
1025 gencheck_interupt_out(dst->addr + (dst-1)->f.i.immediate*4);
1026 mov_m32_imm32(&jump_to_address, dst->addr + (dst-1)->f.i.immediate*4);
1027 mov_m32_imm32((unsigned int*)(&PC), (unsigned int)(dst+1));
1028 mov_reg32_imm32(EAX, (unsigned int)jump_to_func);
1033 genupdate_count(dst->addr+4);
1034 mov_m32_imm32(&last_addr, dst->addr + 4);
1035 gencheck_interupt((unsigned int)(dst + 1));
1039 void genbeql_out(void)
1041 #ifdef INTERPRET_BEQL_OUT
1042 gencallinterp((unsigned int)cached_interpreter_table.BEQL_OUT, 1);
1044 if (((dst->addr & 0xFFF) == 0xFFC &&
1045 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1047 gencallinterp((unsigned int)cached_interpreter_table.BEQL_OUT, 1);
1052 free_all_registers();
1057 void genbeql_idle(void)
1059 #ifdef INTERPRET_BEQL_IDLE
1060 gencallinterp((unsigned int)cached_interpreter_table.BEQL_IDLE, 1);
1062 if (((dst->addr & 0xFFF) == 0xFFC &&
1063 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1065 gencallinterp((unsigned int)cached_interpreter_table.BEQL_IDLE, 1);
1077 #ifdef INTERPRET_BNEL
1078 gencallinterp((unsigned int)cached_interpreter_table.BNEL, 1);
1080 if (((dst->addr & 0xFFF) == 0xFFC &&
1081 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1083 gencallinterp((unsigned int)cached_interpreter_table.BNEL, 1);
1088 free_all_registers();
1093 void genbnel_out(void)
1095 #ifdef INTERPRET_BNEL_OUT
1096 gencallinterp((unsigned int)cached_interpreter_table.BNEL_OUT, 1);
1098 if (((dst->addr & 0xFFF) == 0xFFC &&
1099 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1101 gencallinterp((unsigned int)cached_interpreter_table.BNEL_OUT, 1);
1106 free_all_registers();
1111 void genbnel_idle(void)
1113 #ifdef INTERPRET_BNEL_IDLE
1114 gencallinterp((unsigned int)cached_interpreter_table.BNEL_IDLE, 1);
1116 if (((dst->addr & 0xFFF) == 0xFFC &&
1117 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1119 gencallinterp((unsigned int)cached_interpreter_table.BNEL_IDLE, 1);
1131 #ifdef INTERPRET_BLEZL
1132 gencallinterp((unsigned int)cached_interpreter_table.BLEZL, 1);
1134 if (((dst->addr & 0xFFF) == 0xFFC &&
1135 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1137 gencallinterp((unsigned int)cached_interpreter_table.BLEZL, 1);
1142 free_all_registers();
1147 void genblezl_out(void)
1149 #ifdef INTERPRET_BLEZL_OUT
1150 gencallinterp((unsigned int)cached_interpreter_table.BLEZL_OUT, 1);
1152 if (((dst->addr & 0xFFF) == 0xFFC &&
1153 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1155 gencallinterp((unsigned int)cached_interpreter_table.BLEZL_OUT, 1);
1160 free_all_registers();
1165 void genblezl_idle(void)
1167 #ifdef INTERPRET_BLEZL_IDLE
1168 gencallinterp((unsigned int)cached_interpreter_table.BLEZL_IDLE, 1);
1170 if (((dst->addr & 0xFFF) == 0xFFC &&
1171 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1173 gencallinterp((unsigned int)cached_interpreter_table.BLEZL_IDLE, 1);
1185 #ifdef INTERPRET_BGTZL
1186 gencallinterp((unsigned int)cached_interpreter_table.BGTZL, 1);
1188 if (((dst->addr & 0xFFF) == 0xFFC &&
1189 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1191 gencallinterp((unsigned int)cached_interpreter_table.BGTZL, 1);
1196 free_all_registers();
1201 void genbgtzl_out(void)
1203 #ifdef INTERPRET_BGTZL_OUT
1204 gencallinterp((unsigned int)cached_interpreter_table.BGTZL_OUT, 1);
1206 if (((dst->addr & 0xFFF) == 0xFFC &&
1207 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1209 gencallinterp((unsigned int)cached_interpreter_table.BGTZL_OUT, 1);
1214 free_all_registers();
1219 void genbgtzl_idle(void)
1221 #ifdef INTERPRET_BGTZL_IDLE
1222 gencallinterp((unsigned int)cached_interpreter_table.BGTZL_IDLE, 1);
1224 if (((dst->addr & 0xFFF) == 0xFFC &&
1225 (dst->addr < 0x80000000 || dst->addr >= 0xC0000000))||no_compiled_jump)
1227 gencallinterp((unsigned int)cached_interpreter_table.BGTZL_IDLE, 1);
1239 #ifdef INTERPRET_DADDI
1240 gencallinterp((unsigned int)cached_interpreter_table.DADDI, 0);
1242 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
1243 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
1244 int rt1 = allocate_64_register1_w((unsigned int *)dst->f.i.rt);
1245 int rt2 = allocate_64_register2_w((unsigned int *)dst->f.i.rt);
1247 mov_reg32_reg32(rt1, rs1);
1248 mov_reg32_reg32(rt2, rs2);
1249 add_reg32_imm32(rt1, dst->f.i.immediate);
1250 adc_reg32_imm32(rt2, (int)dst->f.i.immediate>>31);
1254 void gendaddiu(void)
1256 #ifdef INTERPRET_DADDIU
1257 gencallinterp((unsigned int)cached_interpreter_table.DADDIU, 0);
1259 int rs1 = allocate_64_register1((unsigned int *)dst->f.i.rs);
1260 int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs);
1261 int rt1 = allocate_64_register1_w((unsigned int *)dst->f.i.rt);
1262 int rt2 = allocate_64_register2_w((unsigned int *)dst->f.i.rt);
1264 mov_reg32_reg32(rt1, rs1);
1265 mov_reg32_reg32(rt2, rs2);
1266 add_reg32_imm32(rt1, dst->f.i.immediate);
1267 adc_reg32_imm32(rt2, (int)dst->f.i.immediate>>31);
1273 gencallinterp((unsigned int)cached_interpreter_table.LDL, 0);
1278 gencallinterp((unsigned int)cached_interpreter_table.LDR, 0);
1284 gencallinterp((unsigned int)cached_interpreter_table.LB, 0);
1286 free_all_registers();
1288 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1289 add_eax_imm32((int)dst->f.i.immediate);
1290 mov_reg32_reg32(EBX, EAX);
1293 and_eax_imm32(0xDF800000);
1294 cmp_eax_imm32(0x80000000);
1298 shr_reg32_imm8(EAX, 16);
1299 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemb);
1300 cmp_reg32_imm32(EAX, (unsigned int)read_rdramb);
1304 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1305 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1306 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1307 shr_reg32_imm8(EBX, 16); // 3
1308 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemb); // 7
1309 call_reg32(EBX); // 2
1310 movsx_reg32_m8(EAX, (unsigned char *)dst->f.i.rt); // 7
1311 jmp_imm_short(16); // 2
1313 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1314 xor_reg8_imm8(BL, 3); // 3
1315 movsx_reg32_8preg32pimm32(EAX, EBX, (unsigned int)rdram); // 7
1317 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1324 gencallinterp((unsigned int)cached_interpreter_table.LH, 0);
1326 free_all_registers();
1328 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1329 add_eax_imm32((int)dst->f.i.immediate);
1330 mov_reg32_reg32(EBX, EAX);
1333 and_eax_imm32(0xDF800000);
1334 cmp_eax_imm32(0x80000000);
1338 shr_reg32_imm8(EAX, 16);
1339 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemh);
1340 cmp_reg32_imm32(EAX, (unsigned int)read_rdramh);
1344 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1345 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1346 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1347 shr_reg32_imm8(EBX, 16); // 3
1348 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemh); // 7
1349 call_reg32(EBX); // 2
1350 movsx_reg32_m16(EAX, (unsigned short *)dst->f.i.rt); // 7
1351 jmp_imm_short(16); // 2
1353 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1354 xor_reg8_imm8(BL, 2); // 3
1355 movsx_reg32_16preg32pimm32(EAX, EBX, (unsigned int)rdram); // 7
1357 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1363 gencallinterp((unsigned int)cached_interpreter_table.LWL, 0);
1369 gencallinterp((unsigned int)cached_interpreter_table.LW, 0);
1371 free_all_registers();
1373 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1374 add_eax_imm32((int)dst->f.i.immediate);
1375 mov_reg32_reg32(EBX, EAX);
1378 and_eax_imm32(0xDF800000);
1379 cmp_eax_imm32(0x80000000);
1383 shr_reg32_imm8(EAX, 16);
1384 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmem);
1385 cmp_reg32_imm32(EAX, (unsigned int)read_rdram);
1389 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1390 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1391 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1392 shr_reg32_imm8(EBX, 16); // 3
1393 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmem); // 7
1394 call_reg32(EBX); // 2
1395 mov_eax_memoffs32((unsigned int *)(dst->f.i.rt)); // 5
1396 jmp_imm_short(12); // 2
1398 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1399 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1401 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1407 #ifdef INTERPRET_LBU
1408 gencallinterp((unsigned int)cached_interpreter_table.LBU, 0);
1410 free_all_registers();
1412 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1413 add_eax_imm32((int)dst->f.i.immediate);
1414 mov_reg32_reg32(EBX, EAX);
1417 and_eax_imm32(0xDF800000);
1418 cmp_eax_imm32(0x80000000);
1422 shr_reg32_imm8(EAX, 16);
1423 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemb);
1424 cmp_reg32_imm32(EAX, (unsigned int)read_rdramb);
1428 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1429 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1430 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1431 shr_reg32_imm8(EBX, 16); // 3
1432 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemb); // 7
1433 call_reg32(EBX); // 2
1434 mov_reg32_m32(EAX, (unsigned int *)dst->f.i.rt); // 6
1435 jmp_imm_short(15); // 2
1437 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1438 xor_reg8_imm8(BL, 3); // 3
1439 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1441 and_eax_imm32(0xFF);
1443 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1449 #ifdef INTERPRET_LHU
1450 gencallinterp((unsigned int)cached_interpreter_table.LHU, 0);
1452 free_all_registers();
1454 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1455 add_eax_imm32((int)dst->f.i.immediate);
1456 mov_reg32_reg32(EBX, EAX);
1459 and_eax_imm32(0xDF800000);
1460 cmp_eax_imm32(0x80000000);
1464 shr_reg32_imm8(EAX, 16);
1465 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemh);
1466 cmp_reg32_imm32(EAX, (unsigned int)read_rdramh);
1470 mov_m32_imm32((unsigned int *)&PC, (unsigned int)(dst+1)); // 10
1471 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1472 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1473 shr_reg32_imm8(EBX, 16); // 3
1474 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemh); // 7
1475 call_reg32(EBX); // 2
1476 mov_reg32_m32(EAX, (unsigned int *)dst->f.i.rt); // 6
1477 jmp_imm_short(15); // 2
1479 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1480 xor_reg8_imm8(BL, 2); // 3
1481 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1483 and_eax_imm32(0xFFFF);
1485 set_register_state(EAX, (unsigned int*)dst->f.i.rt, 1);
1491 gencallinterp((unsigned int)cached_interpreter_table.LWR, 0);
1496 #ifdef INTERPRET_LWU
1497 gencallinterp((unsigned int)cached_interpreter_table.LWU, 0);
1499 free_all_registers();
1501 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1502 add_eax_imm32((int)dst->f.i.immediate);
1503 mov_reg32_reg32(EBX, EAX);
1506 and_eax_imm32(0xDF800000);
1507 cmp_eax_imm32(0x80000000);
1511 shr_reg32_imm8(EAX, 16);
1512 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmem);
1513 cmp_reg32_imm32(EAX, (unsigned int)read_rdram);
1517 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1518 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1519 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1520 shr_reg32_imm8(EBX, 16); // 3
1521 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmem); // 7
1522 call_reg32(EBX); // 2
1523 mov_eax_memoffs32((unsigned int *)(dst->f.i.rt)); // 5
1524 jmp_imm_short(12); // 2
1526 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1527 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1529 xor_reg32_reg32(EBX, EBX);
1531 set_64_register_state(EAX, EBX, (unsigned int*)dst->f.i.rt, 1);
1538 gencallinterp((unsigned int)cached_interpreter_table.SB, 0);
1540 free_all_registers();
1542 mov_reg8_m8(CL, (unsigned char *)dst->f.i.rt);
1543 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1544 add_eax_imm32((int)dst->f.i.immediate);
1545 mov_reg32_reg32(EBX, EAX);
1548 and_eax_imm32(0xDF800000);
1549 cmp_eax_imm32(0x80000000);
1553 shr_reg32_imm8(EAX, 16);
1554 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writememb);
1555 cmp_reg32_imm32(EAX, (unsigned int)write_rdramb);
1559 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1560 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1561 mov_m8_reg8((unsigned char *)(&cpu_byte), CL); // 6
1562 shr_reg32_imm8(EBX, 16); // 3
1563 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writememb); // 7
1564 call_reg32(EBX); // 2
1565 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1566 jmp_imm_short(17); // 2
1568 mov_reg32_reg32(EAX, EBX); // 2
1569 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1570 xor_reg8_imm8(BL, 3); // 3
1571 mov_preg32pimm32_reg8(EBX, (unsigned int)rdram, CL); // 6
1573 mov_reg32_reg32(EBX, EAX);
1574 shr_reg32_imm8(EBX, 12);
1575 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1577 mov_reg32_reg32(ECX, EBX); // 2
1578 shl_reg32_imm8(EBX, 2); // 3
1579 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1580 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1581 and_eax_imm32(0xFFF); // 5
1582 shr_reg32_imm8(EAX, 2); // 3
1583 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1584 mul_reg32(EDX); // 2
1585 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1586 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1588 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1595 gencallinterp((unsigned int)cached_interpreter_table.SH, 0);
1597 free_all_registers();
1599 mov_reg16_m16(CX, (unsigned short *)dst->f.i.rt);
1600 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1601 add_eax_imm32((int)dst->f.i.immediate);
1602 mov_reg32_reg32(EBX, EAX);
1605 and_eax_imm32(0xDF800000);
1606 cmp_eax_imm32(0x80000000);
1610 shr_reg32_imm8(EAX, 16);
1611 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writememh);
1612 cmp_reg32_imm32(EAX, (unsigned int)write_rdramh);
1616 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1617 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1618 mov_m16_reg16((unsigned short *)(&hword), CX); // 7
1619 shr_reg32_imm8(EBX, 16); // 3
1620 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writememh); // 7
1621 call_reg32(EBX); // 2
1622 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1623 jmp_imm_short(18); // 2
1625 mov_reg32_reg32(EAX, EBX); // 2
1626 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1627 xor_reg8_imm8(BL, 2); // 3
1628 mov_preg32pimm32_reg16(EBX, (unsigned int)rdram, CX); // 7
1630 mov_reg32_reg32(EBX, EAX);
1631 shr_reg32_imm8(EBX, 12);
1632 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1634 mov_reg32_reg32(ECX, EBX); // 2
1635 shl_reg32_imm8(EBX, 2); // 3
1636 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1637 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1638 and_eax_imm32(0xFFF); // 5
1639 shr_reg32_imm8(EAX, 2); // 3
1640 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1641 mul_reg32(EDX); // 2
1642 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1643 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1645 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1651 gencallinterp((unsigned int)cached_interpreter_table.SWL, 0);
1657 gencallinterp((unsigned int)cached_interpreter_table.SW, 0);
1659 free_all_registers();
1661 mov_reg32_m32(ECX, (unsigned int *)dst->f.i.rt);
1662 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1663 add_eax_imm32((int)dst->f.i.immediate);
1664 mov_reg32_reg32(EBX, EAX);
1667 and_eax_imm32(0xDF800000);
1668 cmp_eax_imm32(0x80000000);
1672 shr_reg32_imm8(EAX, 16);
1673 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writemem);
1674 cmp_reg32_imm32(EAX, (unsigned int)write_rdram);
1678 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1679 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1680 mov_m32_reg32((unsigned int *)(&word), ECX); // 6
1681 shr_reg32_imm8(EBX, 16); // 3
1682 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writemem); // 7
1683 call_reg32(EBX); // 2
1684 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1685 jmp_imm_short(14); // 2
1687 mov_reg32_reg32(EAX, EBX); // 2
1688 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1689 mov_preg32pimm32_reg32(EBX, (unsigned int)rdram, ECX); // 6
1691 mov_reg32_reg32(EBX, EAX);
1692 shr_reg32_imm8(EBX, 12);
1693 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1695 mov_reg32_reg32(ECX, EBX); // 2
1696 shl_reg32_imm8(EBX, 2); // 3
1697 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1698 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1699 and_eax_imm32(0xFFF); // 5
1700 shr_reg32_imm8(EAX, 2); // 3
1701 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1702 mul_reg32(EDX); // 2
1703 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1704 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1706 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1712 gencallinterp((unsigned int)cached_interpreter_table.SDL, 0);
1717 gencallinterp((unsigned int)cached_interpreter_table.SDR, 0);
1722 gencallinterp((unsigned int)cached_interpreter_table.SWR, 0);
1725 void gencheck_cop1_unusable(void)
1727 free_all_registers();
1729 test_m32_imm32((unsigned int*)&Status, 0x20000000);
1734 gencallinterp((unsigned int)check_cop1_unusable, 0);
1741 #ifdef INTERPRET_LWC1
1742 gencallinterp((unsigned int)cached_interpreter_table.LWC1, 0);
1744 gencheck_cop1_unusable();
1746 mov_eax_memoffs32((unsigned int *)(®[dst->f.lf.base]));
1747 add_eax_imm32((int)dst->f.lf.offset);
1748 mov_reg32_reg32(EBX, EAX);
1751 and_eax_imm32(0xDF800000);
1752 cmp_eax_imm32(0x80000000);
1756 shr_reg32_imm8(EAX, 16);
1757 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmem);
1758 cmp_reg32_imm32(EAX, (unsigned int)read_rdram);
1762 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1763 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1764 mov_reg32_m32(EDX, (unsigned int*)(®_cop1_simple[dst->f.lf.ft])); // 6
1765 mov_m32_reg32((unsigned int *)(&rdword), EDX); // 6
1766 shr_reg32_imm8(EBX, 16); // 3
1767 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmem); // 7
1768 call_reg32(EBX); // 2
1769 jmp_imm_short(20); // 2
1771 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1772 mov_reg32_preg32pimm32(EAX, EBX, (unsigned int)rdram); // 6
1773 mov_reg32_m32(EBX, (unsigned int*)(®_cop1_simple[dst->f.lf.ft])); // 6
1774 mov_preg32_reg32(EBX, EAX); // 2
1780 #ifdef INTERPRET_LDC1
1781 gencallinterp((unsigned int)cached_interpreter_table.LDC1, 0);
1783 gencheck_cop1_unusable();
1785 mov_eax_memoffs32((unsigned int *)(®[dst->f.lf.base]));
1786 add_eax_imm32((int)dst->f.lf.offset);
1787 mov_reg32_reg32(EBX, EAX);
1790 and_eax_imm32(0xDF800000);
1791 cmp_eax_imm32(0x80000000);
1795 shr_reg32_imm8(EAX, 16);
1796 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemd);
1797 cmp_reg32_imm32(EAX, (unsigned int)read_rdramd);
1801 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1802 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1803 mov_reg32_m32(EDX, (unsigned int*)(®_cop1_double[dst->f.lf.ft])); // 6
1804 mov_m32_reg32((unsigned int *)(&rdword), EDX); // 6
1805 shr_reg32_imm8(EBX, 16); // 3
1806 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemd); // 7
1807 call_reg32(EBX); // 2
1808 jmp_imm_short(32); // 2
1810 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1811 mov_reg32_preg32pimm32(EAX, EBX, ((unsigned int)rdram)+4); // 6
1812 mov_reg32_preg32pimm32(ECX, EBX, ((unsigned int)rdram)); // 6
1813 mov_reg32_m32(EBX, (unsigned int*)(®_cop1_double[dst->f.lf.ft])); // 6
1814 mov_preg32_reg32(EBX, EAX); // 2
1815 mov_preg32pimm32_reg32(EBX, 4, ECX); // 6
1826 gencallinterp((unsigned int)cached_interpreter_table.LD, 0);
1828 free_all_registers();
1830 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1831 add_eax_imm32((int)dst->f.i.immediate);
1832 mov_reg32_reg32(EBX, EAX);
1835 and_eax_imm32(0xDF800000);
1836 cmp_eax_imm32(0x80000000);
1840 shr_reg32_imm8(EAX, 16);
1841 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)readmemd);
1842 cmp_reg32_imm32(EAX, (unsigned int)read_rdramd);
1846 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1847 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1848 mov_m32_imm32((unsigned int *)(&rdword), (unsigned int)dst->f.i.rt); // 10
1849 shr_reg32_imm8(EBX, 16); // 3
1850 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)readmemd); // 7
1851 call_reg32(EBX); // 2
1852 mov_eax_memoffs32((unsigned int *)(dst->f.i.rt)); // 5
1853 mov_reg32_m32(ECX, (unsigned int *)(dst->f.i.rt)+1); // 6
1854 jmp_imm_short(18); // 2
1856 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1857 mov_reg32_preg32pimm32(EAX, EBX, ((unsigned int)rdram)+4); // 6
1858 mov_reg32_preg32pimm32(ECX, EBX, ((unsigned int)rdram)); // 6
1860 set_64_register_state(EAX, ECX, (unsigned int*)dst->f.i.rt, 1);
1866 #ifdef INTERPRET_SWC1
1867 gencallinterp((unsigned int)cached_interpreter_table.SWC1, 0);
1869 gencheck_cop1_unusable();
1871 mov_reg32_m32(EDX, (unsigned int*)(®_cop1_simple[dst->f.lf.ft]));
1872 mov_reg32_preg32(ECX, EDX);
1873 mov_eax_memoffs32((unsigned int *)(®[dst->f.lf.base]));
1874 add_eax_imm32((int)dst->f.lf.offset);
1875 mov_reg32_reg32(EBX, EAX);
1878 and_eax_imm32(0xDF800000);
1879 cmp_eax_imm32(0x80000000);
1883 shr_reg32_imm8(EAX, 16);
1884 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writemem);
1885 cmp_reg32_imm32(EAX, (unsigned int)write_rdram);
1889 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1890 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1891 mov_m32_reg32((unsigned int *)(&word), ECX); // 6
1892 shr_reg32_imm8(EBX, 16); // 3
1893 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writemem); // 7
1894 call_reg32(EBX); // 2
1895 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1896 jmp_imm_short(14); // 2
1898 mov_reg32_reg32(EAX, EBX); // 2
1899 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1900 mov_preg32pimm32_reg32(EBX, (unsigned int)rdram, ECX); // 6
1902 mov_reg32_reg32(EBX, EAX);
1903 shr_reg32_imm8(EBX, 12);
1904 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1906 mov_reg32_reg32(ECX, EBX); // 2
1907 shl_reg32_imm8(EBX, 2); // 3
1908 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1909 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1910 and_eax_imm32(0xFFF); // 5
1911 shr_reg32_imm8(EAX, 2); // 3
1912 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1913 mul_reg32(EDX); // 2
1914 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1915 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1917 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1923 #ifdef INTERPRET_SDC1
1924 gencallinterp((unsigned int)cached_interpreter_table.SDC1, 0);
1926 gencheck_cop1_unusable();
1928 mov_reg32_m32(ESI, (unsigned int*)(®_cop1_double[dst->f.lf.ft]));
1929 mov_reg32_preg32(ECX, ESI);
1930 mov_reg32_preg32pimm32(EDX, ESI, 4);
1931 mov_eax_memoffs32((unsigned int *)(®[dst->f.lf.base]));
1932 add_eax_imm32((int)dst->f.lf.offset);
1933 mov_reg32_reg32(EBX, EAX);
1936 and_eax_imm32(0xDF800000);
1937 cmp_eax_imm32(0x80000000);
1941 shr_reg32_imm8(EAX, 16);
1942 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writememd);
1943 cmp_reg32_imm32(EAX, (unsigned int)write_rdramd);
1947 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
1948 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
1949 mov_m32_reg32((unsigned int *)(&dword), ECX); // 6
1950 mov_m32_reg32((unsigned int *)(&dword)+1, EDX); // 6
1951 shr_reg32_imm8(EBX, 16); // 3
1952 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writememd); // 7
1953 call_reg32(EBX); // 2
1954 mov_eax_memoffs32((unsigned int *)(&address)); // 5
1955 jmp_imm_short(20); // 2
1957 mov_reg32_reg32(EAX, EBX); // 2
1958 and_reg32_imm32(EBX, 0x7FFFFF); // 6
1959 mov_preg32pimm32_reg32(EBX, ((unsigned int)rdram)+4, ECX); // 6
1960 mov_preg32pimm32_reg32(EBX, ((unsigned int)rdram)+0, EDX); // 6
1962 mov_reg32_reg32(EBX, EAX);
1963 shr_reg32_imm8(EBX, 12);
1964 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
1966 mov_reg32_reg32(ECX, EBX); // 2
1967 shl_reg32_imm8(EBX, 2); // 3
1968 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
1969 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
1970 and_eax_imm32(0xFFF); // 5
1971 shr_reg32_imm8(EAX, 2); // 3
1972 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
1973 mul_reg32(EDX); // 2
1974 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
1975 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
1977 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
1984 gencallinterp((unsigned int)cached_interpreter_table.SD, 0);
1986 free_all_registers();
1989 mov_reg32_m32(ECX, (unsigned int *)dst->f.i.rt);
1990 mov_reg32_m32(EDX, ((unsigned int *)dst->f.i.rt)+1);
1991 mov_eax_memoffs32((unsigned int *)dst->f.i.rs);
1992 add_eax_imm32((int)dst->f.i.immediate);
1993 mov_reg32_reg32(EBX, EAX);
1996 and_eax_imm32(0xDF800000);
1997 cmp_eax_imm32(0x80000000);
2001 shr_reg32_imm8(EAX, 16);
2002 mov_reg32_preg32x4pimm32(EAX, EAX, (unsigned int)writememd);
2003 cmp_reg32_imm32(EAX, (unsigned int)write_rdramd);
2007 mov_m32_imm32((unsigned int *)(&PC), (unsigned int)(dst+1)); // 10
2008 mov_m32_reg32((unsigned int *)(&address), EBX); // 6
2009 mov_m32_reg32((unsigned int *)(&dword), ECX); // 6
2010 mov_m32_reg32((unsigned int *)(&dword)+1, EDX); // 6
2011 shr_reg32_imm8(EBX, 16); // 3
2012 mov_reg32_preg32x4pimm32(EBX, EBX, (unsigned int)writememd); // 7
2013 call_reg32(EBX); // 2
2014 mov_eax_memoffs32((unsigned int *)(&address)); // 5
2015 jmp_imm_short(20); // 2
2017 mov_reg32_reg32(EAX, EBX); // 2
2018 and_reg32_imm32(EBX, 0x7FFFFF); // 6
2019 mov_preg32pimm32_reg32(EBX, ((unsigned int)rdram)+4, ECX); // 6
2020 mov_preg32pimm32_reg32(EBX, ((unsigned int)rdram)+0, EDX); // 6
2022 mov_reg32_reg32(EBX, EAX);
2023 shr_reg32_imm8(EBX, 12);
2024 cmp_preg32pimm32_imm8(EBX, (unsigned int)invalid_code, 0);
2026 mov_reg32_reg32(ECX, EBX); // 2
2027 shl_reg32_imm8(EBX, 2); // 3
2028 mov_reg32_preg32pimm32(EBX, EBX, (unsigned int)blocks); // 6
2029 mov_reg32_preg32pimm32(EBX, EBX, (int)&actual->block - (int)actual); // 6
2030 and_eax_imm32(0xFFF); // 5
2031 shr_reg32_imm8(EAX, 2); // 3
2032 mov_reg32_imm32(EDX, sizeof(precomp_instr)); // 5
2033 mul_reg32(EDX); // 2
2034 mov_reg32_preg32preg32pimm32(EAX, EAX, EBX, (int)&dst->ops - (int)dst); // 7
2035 cmp_reg32_imm32(EAX, (unsigned int)cached_interpreter_table.NOTCOMPILED); // 6
2037 mov_preg32pimm32_imm8(ECX, (unsigned int)invalid_code, 1); // 7
2043 gencallinterp((unsigned int)cached_interpreter_table.LL, 0);
2048 gencallinterp((unsigned int)cached_interpreter_table.SC, 0);