2 # --register-prefix-optional --bitwise-or
4 .macro ldarg arg, stacksz, reg
5 move.l (4 + \arg * 4 + \stacksz)(%sp), \reg
8 .macro ldargw arg, stacksz, reg
9 move.w (4 + \arg * 4 + 2 + \stacksz)(%sp), \reg
12 .global burn10 /* u16 val */
20 .global write16_x16 /* u32 a, u16 count, u16 d */
41 # read single phase from controller
46 move.b #0x40,(0xa10003)
51 move.b #0x00,(0xa10003)
52 andi.w #0x3f,d1 /* 00CB RLDU */
56 andi.w #0xc0,d0 /* SA00 0000 */
62 eor.w d0,d1 /* changed btns */
63 move.w d0,d7 /* old val */
65 and.w d0,d1 /* what changed now */
69 .global write_and_read1 /* u32 a, u16 d, void *dst */
76 /* different timing due to extra fetch of offset, */
77 /* less troulesome to emulate */
90 .global move_sr /* u16 sr */
96 .global move_sr_and_read /* u16 sr, u32 a */
109 .global memcpy_ /* void *dst, const void *src, u16 size */
116 move.b (a1)+, (a0)+ /* not in a hurry */
120 .global memset_ /* void *dst, int d, u16 size */
127 move.b d1, (a0)+ /* not in a hurry */
135 movem.l d2-d7/a2, -(sp)
136 movea.l #0xc00007, a0
137 movea.l #0xc00008, a1
138 movea.l #0xff0000, a2
139 moveq.l #0, d4 /* d4 = count */
140 moveq.l #0, d5 /* d5 = vcnt_expect */
142 move.l #1<<(3+16), d7 /* d7 = SR_VB */
145 beq 0b /* not blanking */
148 bne 0b /* blanking */
153 bne 0b /* not line 0 */
157 move.l d6, (a2)+ /* d0 = old */
160 move.b (a1), d2 /* 8 d2 = vcnt */
161 cmp.b (a1), d2 /* 8 reread for corruption */
162 bne 0b /* 10 on changing vcounter? */
163 cmp.b d2, d5 /* 4 vcnt == vcnt_expect? */
165 move.l (a0), d0 /* 12 */
169 addq.l #1, d4 /* count++ */
172 bne 2f /* vcnt == vcnt_expect + 1 */
175 and.l d7, d1 /* (old ^ val) & vb */
177 move.l d0, d6 /* old = val */
180 2: /* vcnt jump or vb change */
181 move.l d6, (a2)+ /* *ram++ = old */
182 move.l d0, (a2)+ /* *ram++ = val */
183 move.b d2, d5 /* vcnt_expect = vcnt */
184 move.l d0, d6 /* old = val */
190 bne 1b /* still in VB */
192 move.l d0, (a2)+ /* *ram++ = val */
193 move.l d4, (a2)+ /* *ram++ = count */
195 movem.l (sp)+, d2-d7/a2
200 move.w d0, -(sp) /* 8 */
201 move.w (0xc00008).l, d0 /* 16 */
202 addq.w #1, (0xf000).w /* 16 */
203 tst.w (0xf002).w /* 12 */
205 move.w d0, (0xf002).w /* 12 */
207 move.w d0, (0xf004).w /* 12 */
208 move.w (sp)+, d0 /* 8 */
210 .global test_hint_end
215 move.w d0, -(sp) /* 8 */
216 move.w (0xc00008).l, d0 /* 16 */
217 addq.w #1, (0xf008).w /* 16 */
218 tst.w (0xf00a).w /* 12 */
220 move.w d0, (0xf00a).w /* 12 */
222 move.w d0, (0xf00c).w /* 12 */
223 move.w (sp)+, d0 /* 8 */
225 .global test_vint_end
230 movea.l #0xa15100, a0
231 movea.l #0xa15122, a1
232 move.w #1, (a0) /* ADEN */
233 # wait for min(20_sh2_cycles, pll_setup_time)
234 # pll time is unclear, icd_mars.prg mentions 10ms which sounds
235 # way too much. Hope 40 68k cycles is enough
239 move.w #3, (a0) /* ADEN, nRES */
241 move.w #0xffff, d0 /* waste some cycles */
243 beq 0b /* master BIOS busy */
245 0: /* for slave, use a limit, as it */
246 tst.w 4(a1) /* won't respond on master error. */
247 dbne d0, 0b /* slave BIOS busy */
249 or.w #1, 6(a0) /* RV */
251 .global x32x_enable_end
256 movea.l #0xa15100, a0
257 move.w #1, (a0) /* ADEN (reset sh2) */
258 move.w #0, (a0) /* adapter disable, reset sh2 */
262 move.w #2, (a0) /* nRES - sh2s should see no ADEN and sleep */
264 .global x32x_disable_end
267 .global test_32x_b_c0
271 jsr (0xc0).l /* move.b d0, (a1); RV=0 */
272 bset #0, (0xa15107).l /* RV=1 */
274 .global test_32x_b_c0_end
277 # some nastyness from Fatal Rewind
281 move.w #0x8014, (0xFFC00004).l
282 move.w #0x8164, (0xFFC00004).l
292 movea.l #0xc00004, a0
295 move.w #480/2/10-1, d0
298 move.w #0x8164, (0xFFC00004).l
299 move.w #0x8014, (0xFFC00004).l
307 .global test_f_vint_end
312 movea.l #0xc00005, a0
313 movea.l #0xc00004, a1
321 movem.l d2-d7/a2, -(sp)
329 movea.l #0xff0000, a0
332 .macro test_lb_s sr, dr
343 movem.l (sp)+, d2-d7/a2
349 movea.l #0xc00004, a0
350 movea.l #0xc00008, a1
361 movea.l #0xff0000, a1
362 movea.l #0xff0000, a1
381 # vim:filetype=asmM68k:ts=4:sw=4:expandtab