3 @ ranges/opcodes (idle, normal):
4 @ 71xx, 73xx - bne.s (8bit offset)
5 @ 75xx, 77xx - beq.s (8bit offset)
6 @ 7dxx, 7fxx - bra.s (8bit offset)
14 .equ patch_desc_table_size, 10
17 .word (0x71fa<<16) | 0x66fa, idle_detector_bcc8, idle_bne, Op6602 @ bne.s
18 .word (0x71f8<<16) | 0x66f8, idle_detector_bcc8, idle_bne, Op6602 @ bne.s
19 .word (0x71f6<<16) | 0x66f6, idle_detector_bcc8, idle_bne, Op6602 @ bne.s
20 .word (0x71f2<<16) | 0x66f2, idle_detector_bcc8, idle_bne, Op6602 @ bne.s
21 .word (0x75fa<<16) | 0x67fa, idle_detector_bcc8, idle_beq, Op6702 @ beq.s
22 .word (0x75f8<<16) | 0x67f8, idle_detector_bcc8, idle_beq, Op6702 @ beq.s
23 .word (0x75f6<<16) | 0x67f6, idle_detector_bcc8, idle_beq, Op6702 @ beq.s
24 .word (0x75f2<<16) | 0x67f2, idle_detector_bcc8, idle_beq, Op6702 @ beq.s
25 .word (0x7dfe<<16) | 0x60fe, idle_detector_bcc8, idle_bra, Op6002 @ bra.s
26 .word (0x7dfc<<16) | 0x60fc, idle_detector_bcc8, idle_bra, Op6002 @ bra.s
33 .global CycloneInitIdle
36 ldr r3, =CycloneJumpTab
37 ldr r2, =patch_desc_table
38 mov r12,#patch_desc_table_size
42 ldr r1, [r2, #4] @ detector
43 str r1, [r3, r0, lsl #2]
45 ldr r1, [r2, #8] @ idle
46 add r0, r3, r0, lsl #2
48 ldr r1, [r2, #12] @ normal
60 .global CycloneFinishIdle
68 ldr r3, =CycloneJumpTab
69 ldr r2, =patch_desc_table
70 mov r12,#patch_desc_table_size
74 ldr r1, [r2, #12] @ normal
75 str r1, [r3, r0, lsl #2]
78 add r0, r3, r0, lsl #2
92 .macro inc_counter cond
93 @ ldr\cond r0, [r7, #0x60]
97 @ bl\cond SekRegisterIdleHit
108 movne r5, #2 @ 2 is intentional due to strange timing issues
113 msr cpsr_flg, r10 ;@ ARM flags = 68000 flags
124 beq exit_detector @ not yet
126 mov r0, r8, asl #24 @ Shift 8-bit signed offset up...
127 add r0, r4, r0, asr #24 @ jump dest
131 sub r1, r1, r8, lsl #24
140 orreq r2, r2, #0x0200
143 orrgt r2, r2, #0x0400 @ 67xx (beq)
144 orrlt r2, r2, #0x0c00 @ 60xx (bra)
151 bl SekRegisterIdlePatch
152 cmp r0, #1 @ 0 - ok to patch, 1 - no patch, 2 - remove detector
156 @ remove detector from Cyclone
163 ldr r3, =CycloneJumpTab
164 str r1, [r3, r8, lsl #2]