-// pending_exception?
-// swi 0 in do_unalignedwritestub?
+/*
+ * (C) GraÅžvydas "notaz" Ignotas, 2010
+ *
+ * This work is licensed under the terms of GNU GPL version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
#include <stdio.h>
#include "emu_if.h"
-#include "../psxmem.h"
+#include "pcsxmem.h"
#include "../psxhle.h"
+#include "../r3000a.h"
+#include "../cdrom.h"
+#include "../psxdma.h"
+#include "../mdec.h"
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
-//#define memprintf printf
-#define memprintf(...)
//#define evprintf printf
#define evprintf(...)
char invalid_code[0x100000];
-u32 event_cycles[6];
-
-void MTC0_()
-{
- extern void psxMTC0();
-
- memprintf("ari64 MTC0 %08x\n", psxRegs.code);
- psxMTC0();
- pending_exception = 1; /* FIXME? */
-}
+u32 event_cycles[PSXINT_COUNT];
static void schedule_timeslice(void)
{
#endif
}
+typedef void (irq_func)();
+
+static irq_func * const irq_funcs[] = {
+ [PSXINT_SIO] = sioInterrupt,
+ [PSXINT_CDR] = cdrInterrupt,
+ [PSXINT_CDREAD] = cdrReadInterrupt,
+ [PSXINT_GPUDMA] = gpuInterrupt,
+ [PSXINT_MDECOUTDMA] = mdec1Interrupt,
+ [PSXINT_SPUDMA] = spuInterrupt,
+ [PSXINT_MDECINDMA] = mdec0Interrupt,
+ [PSXINT_GPUOTCDMA] = gpuotcInterrupt,
+};
+
+/* local dupe of psxBranchTest, using event_cycles */
+static void irq_test(void)
+{
+ u32 irqs = psxRegs.interrupt;
+ u32 cycle = psxRegs.cycle;
+ u32 irq, irq_bits;
+
+ if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
+ psxRcntUpdate();
+
+ // irq_funcs() may queue more irqs
+ psxRegs.interrupt = 0;
+
+ for (irq = 0, irq_bits = irqs; irq_bits != 0; irq++, irq_bits >>= 1) {
+ if (!(irq_bits & 1))
+ continue;
+ if ((s32)(cycle - event_cycles[irq]) >= 0) {
+ irqs &= ~(1 << irq);
+ irq_funcs[irq]();
+ }
+ }
+ psxRegs.interrupt |= irqs;
+
+ if ((psxHu32(0x1070) & psxHu32(0x1074)) && (Status & 0x401) == 0x401) {
+ psxException(0x400, 0);
+ pending_exception = 1;
+ }
+}
+
void gen_interupt()
{
- //evprintf("ari64_gen_interupt\n");
evprintf(" +ge %08x, %u->%u\n", psxRegs.pc, psxRegs.cycle, next_interupt);
#ifdef DRC_DBG
psxRegs.cycle += 2;
#endif
- psxBranchTest();
+ irq_test();
+ //psxBranchTest();
+ //pending_exception = 1;
schedule_timeslice();
evprintf(" -ge %08x, %u->%u (%d)\n", psxRegs.pc, psxRegs.cycle,
next_interupt, next_interupt - psxRegs.cycle);
-
- pending_exception = 1; /* FIXME */
}
-void check_interupt()
-{
- printf("ari64_check_interupt\n");
-}
-
-void read_nomem_new()
-{
- printf("ari64_read_nomem_new\n");
-}
-
-static void read_mem8()
-{
- memprintf("ari64_read_mem8 %08x, PC~=%08x\n", address, psxRegs.pc);
- readmem_word = psxMemRead8(address) & 0xff;
-}
-
-static void read_mem16()
+void MTC0_()
{
- memprintf("ari64_read_mem16 %08x, PC~=%08x\n", address, psxRegs.pc);
- readmem_word = psxMemRead16(address) & 0xffff;
-}
+ extern void psxMTC0();
-static void read_mem32()
-{
- memprintf("ari64_read_mem32 %08x, PC~=%08x\n", address, psxRegs.pc);
- readmem_word = psxMemRead32(address);
+ evprintf("ari64 MTC0 %08x %08x %u\n", psxRegs.code, psxRegs.pc, psxRegs.cycle);
+ psxMTC0();
+ gen_interupt(); /* FIXME: checking pending irqs should be enough */
}
-static void write_mem8()
+void check_interupt()
{
- memprintf("ari64_write_mem8 %08x, %02x, PC~=%08x\n", address, byte, psxRegs.pc);
- psxMemWrite8(address, byte);
+ /* FIXME (also asm) */
+ printf("ari64_check_interupt\n");
}
-static void write_mem16()
+void new_dyna_save(void)
{
- memprintf("ari64_write_mem16 %08x, %04x, PC~=%08x\n", address, hword, psxRegs.pc);
- psxMemWrite16(address, hword);
+ // psxRegs.intCycle is always maintained, no need to convert
}
-static void write_mem32()
+void new_dyna_restore(void)
{
- memprintf("ari64_write_mem32 %08x, %08x, PC~=%08x\n", address, word, psxRegs.pc);
- psxMemWrite32(address, word);
+ int i;
+ for (i = 0; i < PSXINT_NEWDRC_CHECK; i++)
+ event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
}
-void (*readmem[0x10000])();
-void (*readmemb[0x10000])();
-void (*readmemh[0x10000])();
-void (*writemem[0x10000])();
-void (*writememb[0x10000])();
-void (*writememh[0x10000])();
-
void *gte_handlers[64];
/* from gte.txt.. not sure if this is any good. */
{
extern void (*psxCP2[64])();
extern void psxNULL();
+ extern void *psxH_ptr;
size_t i;
new_dynarec_init();
-
- for (i = 0; i < ARRAY_SIZE(readmem); i++) {
- readmemb[i] = read_mem8;
- readmemh[i] = read_mem16;
- readmem[i] = read_mem32;
- writememb[i] = write_mem8;
- writememh[i] = write_mem16;
- writemem[i] = write_mem32;
- }
+ new_dyna_pcsx_mem_init();
for (i = 0; i < ARRAY_SIZE(gte_handlers); i++)
if (psxCP2[i] != psxNULL)
gte_handlers[i] = psxCP2[i];
+ psxH_ptr = psxH;
+
return 0;
}
static void ari64_reset()
{
printf("ari64_reset\n");
+ new_dyna_pcsx_mem_reset();
invalidate_all_pages();
pending_exception = 1;
}
evprintf("ari64_clear %08x %04x\n", addr, size);
/* check for RAM mirrors */
- if ((start & ~0xe0000000) < 0x200000) {
- start &= ~0xe0000000;
- start |= 0x80000000;
+ if ((addr & ~0xe0600000) < 0x200000) {
+ addr &= ~0xe0600000;
+ addr |= 0x80000000;
}
start = addr >> 12;
unsigned int address, readmem_word, word;
unsigned short hword;
unsigned char byte;
-int pending_exception;
+int pending_exception, stop;
unsigned int next_interupt;
+void *psxH_ptr;
void new_dynarec_init() {}
void new_dyna_start() {}
void new_dynarec_cleanup() {}
+void invalidate_all_pages() {}
+void invalidate_block(unsigned int block) {}
+void new_dyna_pcsx_mem_init(void) {}
+void new_dyna_pcsx_mem_reset(void) {}
#endif
#ifdef DRC_DBG
printf("-- %d\n", bad);
for (i = 0; i < 8; i++)
printf("r%d=%08x r%2d=%08x r%2d=%08x r%2d=%08x\n", i, allregs_p[i],
- i+8, allregs_p[i+8], i+16, allregs_p[i+16], i+24, allregs_p[i+23]);
+ i+8, allregs_p[i+8], i+16, allregs_p[i+16], i+24, allregs_p[i+24]);
printf("PC: %08x/%08x, cycle %u\n", psxRegs.pc, ppc, psxRegs.cycle);
dump_mem("/mnt/ntz/dev/pnd/tmp/psxram.dump", psxM, 0x200000);
dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs.dump", psxH, 0x10000);