* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#include "arm_features.h"
+#include "new_dynarec_config.h"
#include "linkage_offsets.h"
DRC_VAR(FCR0, 4)
DRC_VAR(FCR31, 4)
-#ifdef __MACH__
+#ifdef TEXRELS_FORBIDDEN
.data
.align 2
ptr_jump_in:
#endif
.macro load_varadr reg var
-#if defined(__ARM_ARCH_7A__) && !defined(__PIC__)
- movw \reg, #:lower16:\var
- movt \reg, #:upper16:\var
-#elif defined(__ARM_ARCH_7A__) && defined(__MACH__)
+#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
movw \reg, #:lower16:(\var-(1678f+8))
movt \reg, #:upper16:(\var-(1678f+8))
1678:
add \reg, pc
+#elif defined(HAVE_ARMV7) && !defined(__PIC__)
+ movw \reg, #:lower16:\var
+ movt \reg, #:upper16:\var
#else
ldr \reg, =\var
#endif
.endm
.macro load_varadr_ext reg var
-#if defined(__ARM_ARCH_7A__) && defined(__MACH__) && defined(__PIC__)
+#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
movw \reg, #:lower16:(ptr_\var-(1678f+8))
movt \reg, #:upper16:(ptr_\var-(1678f+8))
1678:
.endm
.macro mov_16 reg imm
-#ifdef __ARM_ARCH_7A__
+#ifdef HAVE_ARMV7
movw \reg, #\imm
#else
mov \reg, #(\imm & 0x00ff)
.endm
.macro mov_24 reg imm
-#ifdef __ARM_ARCH_7A__
+#ifdef HAVE_ARMV7
movw \reg, #(\imm & 0xffff)
movt \reg, #(\imm >> 16)
#else
#endif
.endm
+/* r0 = virtual target address */
+/* r1 = instruction to patch */
.macro dyna_linker_main
- /* r0 = virtual target address */
- /* r1 = instruction to patch */
+#ifndef NO_WRITE_EXEC
load_varadr_ext r3, jump_in
/* get_page */
lsr r2, r0, #12
ldr r5, [r3, r2, lsl #2]
ldr r7, [r6, r4]!
teq r7, r0
- ldreq pc, [r6, #4]
- ldr r7, [r6, #8]
+ ldreq pc, [r6, #8]
+ ldr r7, [r6, #4]
teq r7, r0
ldreq pc, [r6, #12]
/* jump_dirty lookup */
ldr r1, [r4, #8]
/* hash_table insert */
ldr r2, [r6]
- ldr r3, [r6, #4]
+ ldr r3, [r6, #8]
str r0, [r6]
- str r1, [r6, #4]
- str r2, [r6, #8]
+ str r1, [r6, #8]
+ str r2, [r6, #4]
str r3, [r6, #12]
mov pc, r1
8:
+#else
+ /* XXX: should be able to do better than this... */
+ bl get_addr_ht
+ mov pc, r0
+#endif
.endm
and r2, r3, r2, lsr #12
ldr r2, [r1, r2]!
teq r2, r0
- ldreq pc, [r1, #4]
- ldr r2, [r1, #8]
+ ldreq pc, [r1, #8]
+ ldr r2, [r1, #4]
teq r2, r0
ldreq pc, [r1, #12]
str r10, [fp, #LO_cycle_count]