break;
SPU_writeDMAMem(ptr, words_copy * 2, psxRegs.cycle);
HW_DMA4_MADR = SWAPu32(madr + words_copy * 2);
+ // This should be much slower, like 12+ cycles/byte, it's like
+ // that because the CPU runs too fast and fifo is not emulated.
+ // See also set_dma_end().
SPUDMA_INT(words * 4);
return;
HW_DMA2_MADR = SWAPu32(madr + words_copy * 4);
+ // careful: gpu_state_change() also messes with this
+ HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
// already 32-bit word size ((size * 4) / 4)
GPUDMA_INT(words / 4);
return;
HW_DMA2_MADR = SWAPu32(madr);
+ // careful: gpu_state_change() also messes with this
+ HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
// already 32-bit word size ((size * 4) / 4)
GPUDMA_INT(words / 4);
return;
DMA_INTERRUPT(2);
}
+// note: this is also (ab)used for non-dma prim command
+// to delay gpu returning to idle state, see gpu_state_change()
void gpuInterrupt() {
if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000)))
{
mem = getDmaRam(madr, &words_max);
if (mem == INVALID_PTR) {
log_unhandled("bad6 dma madr %x\n", madr);
- HW_DMA6_CHCR &= SWAP32(~0x01000000);
+ HW_DMA6_CHCR &= SWAP32(~0x11000000);
DMA_INTERRUPT(6);
return;
}
log_unhandled("*** DMA6 OT - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
}
- HW_DMA6_CHCR &= SWAP32(~0x01000000);
+ HW_DMA6_CHCR &= SWAP32(~0x11000000);
DMA_INTERRUPT(6);
}
{
if (HW_DMA6_CHCR & SWAP32(0x01000000))
{
- HW_DMA6_CHCR &= SWAP32(~0x01000000);
+ HW_DMA6_CHCR &= SWAP32(~0x11000000);
DMA_INTERRUPT(6);
}
}