if (cause != 0x20) {
//FILE *f = fopen("/tmp/psx_ram.bin", "wb");
//fwrite(psxM, 1, 0x200000, f); fclose(f);
- log_unhandled("exception %08x @%08x\n", cause, pc);
+ log_unhandled("exception %08x @%08x ra=%08x\n",
+ cause, pc, regs->GPR.n.ra);
}
dloadFlush(regs);
regs->pc = pc;
intException(regs, regs->pc - 4, cause);
}
+static noinline void intExceptionReservedInsn(psxRegisters *regs)
+{
+#ifdef DO_EXCEPTION_RESERVEDI
+ static u32 ppc_ = ~0u;
+ if (regs->pc != ppc_) {
+ SysPrintf("reserved instruction %08x @%08x ra=%08x\n",
+ regs->code, regs->pc - 4, regs->GPR.n.ra);
+ ppc_ = regs->pc;
+ }
+ intExceptionInsn(regs, R3000E_RI << 2);
+#endif
+}
+
// 29 Enable for 80000000-ffffffff
// 30 Enable for 00000000-7fffffff
// 31 Enable exception
// get an opcode without triggering exceptions or affecting cache
u32 intFakeFetch(u32 pc)
{
- u8 *base = psxMemRLUT[pc >> 16];
- u32 *code;
- if (unlikely(base == INVALID_PTR))
+ u32 *code = (u32 *)psxm(pc & ~0x3, 0);
+ if (unlikely(code == INVALID_PTR))
return 0; // nop
- code = (u32 *)(base + (pc & 0xfffc));
return SWAP32(*code);
}
static u32 INT_ATTR fetchNoCache(psxRegisters *regs, u8 **memRLUT, u32 pc)
{
- u8 *base = memRLUT[pc >> 16];
- u32 *code;
- if (unlikely(base == INVALID_PTR)) {
+ u32 *code = (u32 *)psxm_lut(pc & ~0x3, 0, memRLUT);
+ if (unlikely(code == INVALID_PTR)) {
SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
intException(regs, pc, R3000E_IBE << 2);
return 0; // execute as nop
}
- code = (u32 *)(base + (pc & 0xfffc));
return SWAP32(*code);
}
if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag)
{
- const u8 *base = memRLUT[pc >> 16];
- const u32 *code;
- if (unlikely(base == INVALID_PTR)) {
+ const u32 *code = (u32 *)psxm_lut(pc & ~0xf, 0, memRLUT);
+ if (unlikely(code == INVALID_PTR)) {
SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
intException(regs, pc, R3000E_IBE << 2);
return 0; // execute as nop
}
- code = (u32 *)(base + (pc & 0xfff0));
entry->tag = pc;
// treat as 4 words, although other configurations are said to be possible
doBranch(regs, tar, R3000A_BRANCH_TAKEN);
}
-#if __has_builtin(__builtin_add_overflow) || (defined(__GNUC__) && __GNUC__ >= 5)
-#define add_overflow(a, b, r) __builtin_add_overflow(a, b, &(r))
-#define sub_overflow(a, b, r) __builtin_sub_overflow(a, b, &(r))
-#else
-#define add_overflow(a, b, r) ({r = (u32)a + (u32)b; (a ^ ~b) & (a ^ r) & (1u<<31);})
-#define sub_overflow(a, b, r) ({r = (u32)a - (u32)b; (a ^ b) & (a ^ r) & (1u<<31);})
-#endif
-
static void addExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) {
s32 val;
if (add_overflow(a1, a2, val)) {
*********************************************************/
OP(psxMFC0) {
u32 r = _Rd_;
-#ifdef DO_EXCEPTION_RESERVEDI
if (unlikely(0x00000417u & (1u << r)))
- intExceptionInsn(regs_, R3000E_RI << 2);
-#endif
+ intExceptionReservedInsn(regs_);
doLoad(regs_, _Rt_, regs_->CP0.r[r]);
}
OP(psxNULL) {
psxNULLne(regs_);
-#ifdef DO_EXCEPTION_RESERVEDI
- intExceptionInsn(regs_, R3000E_RI << 2);
-#endif
+ intExceptionReservedInsn(regs_);
}
void gteNULL(struct psxCP2Regs *regs) {
psxSWCx(regs_, code);
return;
}
+ dloadFlush(regs_);
psxHLEt[hleCode]();
+ branchSeen = 1;
}
static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = {
}
static void intShutdown() {
+ dloadClear(&psxRegs);
}
-// single step (may do several ops in case of a branch)
+// single step (may do several ops in case of a branch or load delay)
+// called by asm/dynarec
void execI(psxRegisters *regs) {
- execI_(psxMemRLUT, regs);
- dloadFlush(regs);
+ do {
+ execIbp(psxMemRLUT, regs);
+ } while (regs->dloadReg[0] || regs->dloadReg[1]);
}
R3000Acpu psxInt = {