+ // ldi ri, simm
+ case 0x0c ... 0x0f:
+ tmpv = (op>>8)&7;
+ known_regs.r[tmpv] = op;
+ known_regb |= 1 << (tmpv + 8);
+ dirty_regb |= 1 << (tmpv + 8);
+ ret++; break;
+
+ // call cond, addr
+ case 0x24: {
+ u32 *jump_op = NULL;
+ tmpv = tr_cond_check(op);
+ if (tmpv != A_COND_AL) {
+ jump_op = tcache_ptr;
+ EOP_MOV_IMM(0, 0, 0); // placeholder for branch
+ }
+ tr_mov16(0, *pc);
+ tr_r0_to_STACK(*pc);
+ if (tmpv != A_COND_AL) {
+ u32 *real_ptr = tcache_ptr;
+ tcache_ptr = jump_op;
+ EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
+ tcache_ptr = real_ptr;
+ }
+ tr_mov16_cond(tmpv, 0, imm);
+ if (tmpv != A_COND_AL) {
+ tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
+ }
+ tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
+ ret |= 0x10000;
+ ret += 2; break;
+ }
+
+ // ld d, (a)
+ case 0x25:
+ tmpv2 = (op >> 4) & 0xf; // dst
+ tr_A_to_r0(op);
+ EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
+ EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
+ EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
+ hostreg_r[0] = hostreg_r[1] = -1;
+ tr_write_funcs[tmpv2](-1);
+ if (tmpv2 == SSP_PC) ret |= 0x10000;
+ ret += 3; break;
+
+ // bra cond, addr
+ case 0x26:
+ tmpv = tr_cond_check(op);
+ tr_mov16_cond(tmpv, 0, imm);
+ if (tmpv != A_COND_AL) {
+ tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
+ }
+ tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
+ ret |= 0x10000;
+ ret += 2; break;
+
+ // mod cond, op
+ case 0x48: {
+ // check for repeats of this op
+ tmpv = 1; // count
+ while (PROGRAM(*pc) == op && (op & 7) != 6) {
+ (*pc)++; tmpv++;
+ n_in_ops++;
+ }
+ if ((op&0xf0) != 0) // !always
+ tr_make_dirty_ST();
+
+ tmpv2 = tr_cond_check(op);
+ switch (op & 7) {
+ case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
+ case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
+ case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
+ case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31
+ EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
+ hostreg_r[1] = -1; break; // abs
+ default: tr_unhandled();
+ }
+
+ hostreg_sspreg_changed(SSP_A);
+ dirty_regb |= KRREG_ST;
+ known_regb &= ~KRREG_ST;
+ known_regb &= ~(KRREG_A|KRREG_AL);
+ ret += tmpv; break;
+ }
+
+ // mpys?
+ case 0x1b:
+ tr_flush_dirty_P();
+ tr_mac_load_XY(op);
+ tr_make_dirty_ST();
+ EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+
+ // mpya (rj), (ri), b
+ case 0x4b:
+ tr_flush_dirty_P();
+ tr_mac_load_XY(op);
+ tr_make_dirty_ST();
+ EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+
+ // mld (rj), (ri), b
+ case 0x5b:
+ EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
+ hostreg_sspreg_changed(SSP_A);
+ known_regs.gr[SSP_A].v = 0;
+ known_regb |= (KRREG_A|KRREG_AL);
+ dirty_regb |= KRREG_ST;
+ tr_mac_load_XY(op);
+ ret++; break;
+
+ // OP a, s
+ case 0x10:
+ case 0x30:
+ case 0x40:
+ case 0x50:
+ case 0x60:
+ case 0x70:
+ tmpv = op & 0xf; // src
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ if (tmpv == SSP_P) {
+ tr_flush_dirty_P();
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
+ } else if (tmpv == SSP_A) {
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
+ } else {
+ tr_read_funcs[tmpv](op);
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
+ }
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+
+ // OP a, (ri)
+ case 0x11:
+ case 0x31:
+ case 0x41:
+ case 0x51:
+ case 0x61:
+ case 0x71:
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+
+ // OP a, adr
+ case 0x13:
+ case 0x33:
+ case 0x43:
+ case 0x53:
+ case 0x63:
+ case 0x73:
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ tr_bank_read(op&0x1ff);
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+
+ // OP a, imm
+ case 0x14:
+ case 0x34:
+ case 0x44:
+ case 0x54:
+ case 0x64:
+ case 0x74:
+ tmpv = (op & 0xf0) >> 4;
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ tr_mov16(0, imm);
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret += 2; break;
+
+ // OP a, ((ri))
+ case 0x15:
+ case 0x35:
+ case 0x45:
+ case 0x55:
+ case 0x65:
+ case 0x75:
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ tr_rX_read2(op);
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret += 3; break;
+
+ // OP a, ri
+ case 0x19:
+ case 0x39:
+ case 0x49:
+ case 0x59:
+ case 0x69:
+ case 0x79: {
+ int r;
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ r = (op&3) | ((op>>6)&4); // src
+ if ((r&3) == 3) tr_unhandled();
+
+ if (known_regb & (1 << (r+8))) {
+ EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
+ EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
+ EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
+ hostreg_r[0] = -1;
+ }
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret++; break;
+ }
+
+ // OP simm
+ case 0x1c:
+ case 0x3c:
+ case 0x4c:
+ case 0x5c:
+ case 0x6c:
+ case 0x7c:
+ tmpv2 = tr_aop_ssp2arm(op>>13); // op
+ tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
+ EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
+ hostreg_sspreg_changed(SSP_A);
+ known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
+ dirty_regb |= KRREG_ST;
+ ret++; break;