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bugfixes, famec tuning
[picodrive.git]
/
cpu
/
fame
/
famec_opcodes.h
diff --git
a/cpu/fame/famec_opcodes.h
b/cpu/fame/famec_opcodes.h
index
a9cc991
..
8586603
100644
(file)
--- a/
cpu/fame/famec_opcodes.h
+++ b/
cpu/fame/famec_opcodes.h
@@
-638,9
+638,7
@@
OPCODE(0x007C)
}
else
{
}
else
{
- u32 newPC = (u32)(PC) - BasePC;
- SET_PC(newPC-2);
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
#ifdef USE_CYCLONE_TIMING
RET(0)
#else
#ifdef USE_CYCLONE_TIMING
RET(0)
#else
@@
-1298,9
+1296,7
@@
OPCODE(0x027C)
}
else
{
}
else
{
- u32 newPC = (u32)(PC) - BasePC;
- SET_PC(newPC-2);
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(20)
RET(4)
}
RET(20)
@@
-1950,10
+1946,8
@@
OPCODE(0x0A7C)
}
else
{
}
else
{
- u32 newPC = (u32)(PC) - BasePC;
- SET_PC(newPC-2);
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
- RET(4)
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+ RET(0)
}
RET(20)
}
}
RET(20)
}
@@
-5213,7
+5207,11
@@
OPCODE(0x0108)
READ_BYTE_F(adr + 2, src)
DREGu16((Opcode >> 9) & 7) = (res << 8) | src;
POST_IO
READ_BYTE_F(adr + 2, src)
DREGu16((Opcode >> 9) & 7) = (res << 8) | src;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(24)
RET(24)
+#endif
}
// MOVEPLaD
}
// MOVEPLaD
@@
-5237,7
+5235,11
@@
OPCODE(0x0148)
READ_BYTE_F(adr, src)
DREG((Opcode >> 9) & 7) = res | src;
POST_IO
READ_BYTE_F(adr, src)
DREG((Opcode >> 9) & 7) = res | src;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(24)
+#else
RET(32)
RET(32)
+#endif
}
// MOVEPWDa
}
// MOVEPWDa
@@
-5253,7
+5255,11
@@
OPCODE(0x0188)
WRITE_BYTE_F(adr + 0, res >> 8)
WRITE_BYTE_F(adr + 2, res >> 0)
POST_IO
WRITE_BYTE_F(adr + 0, res >> 8)
WRITE_BYTE_F(adr + 2, res >> 0)
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(24)
RET(24)
+#endif
}
// MOVEPLDa
}
// MOVEPLDa
@@
-5274,7
+5280,11
@@
OPCODE(0x01C8)
adr += 2;
WRITE_BYTE_F(adr, res >> 0)
POST_IO
adr += 2;
WRITE_BYTE_F(adr, res >> 0)
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(24)
+#else
RET(32)
RET(32)
+#endif
}
// MOVEB
}
// MOVEB
@@
-5460,6
+5470,7
@@
OPCODE(0x1F00)
RET(8)
}
RET(8)
}
+#if 0
// MOVEB
OPCODE(0x1008)
{
// MOVEB
OPCODE(0x1008)
{
@@
-5692,6
+5703,7
@@
OPCODE(0x1F08)
*/
RET(8)
}
*/
RET(8)
}
+#endif
// MOVEB
OPCODE(0x1010)
// MOVEB
OPCODE(0x1010)
@@
-8167,7
+8179,7
@@
OPCODE(0x2100)
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
PRE_IO
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(12)
}
POST_IO
RET(12)
}
@@
-8279,7
+8291,7
@@
OPCODE(0x2F00)
adr = AREG(7) - 4;
AREG(7) = adr;
PRE_IO
adr = AREG(7) - 4;
AREG(7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(12)
}
POST_IO
RET(12)
}
@@
-8350,7
+8362,7
@@
OPCODE(0x2108)
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
PRE_IO
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(12)
}
POST_IO
RET(12)
}
@@
-8462,7
+8474,7
@@
OPCODE(0x2F08)
adr = AREG(7) - 4;
AREG(7) = adr;
PRE_IO
adr = AREG(7) - 4;
AREG(7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(12)
}
POST_IO
RET(12)
}
@@
-8539,7
+8551,7
@@
OPCODE(0x2110)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(20)
}
POST_IO
RET(20)
}
@@
-8657,7
+8669,7
@@
OPCODE(0x2F10)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(20)
}
POST_IO
RET(20)
}
@@
-8738,7
+8750,7
@@
OPCODE(0x2118)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(20)
}
POST_IO
RET(20)
}
@@
-8862,7
+8874,7
@@
OPCODE(0x2F18)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(20)
}
POST_IO
RET(20)
}
@@
-8943,7
+8955,7
@@
OPCODE(0x2120)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(22)
}
POST_IO
RET(22)
}
@@
-9067,7
+9079,7
@@
OPCODE(0x2F20)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(22)
}
POST_IO
RET(22)
}
@@
-9148,7
+9160,7
@@
OPCODE(0x2128)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(24)
}
POST_IO
RET(24)
}
@@
-9272,7
+9284,7
@@
OPCODE(0x2F28)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(24)
}
POST_IO
RET(24)
}
@@
-9353,7
+9365,7
@@
OPCODE(0x2130)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(26)
}
POST_IO
RET(26)
}
@@
-9477,7
+9489,7
@@
OPCODE(0x2F30)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(26)
}
POST_IO
RET(26)
}
@@
-9554,7
+9566,7
@@
OPCODE(0x2138)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(24)
}
POST_IO
RET(24)
}
@@
-9672,7
+9684,7
@@
OPCODE(0x2F38)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(24)
}
POST_IO
RET(24)
}
@@
-9749,7
+9761,7
@@
OPCODE(0x2139)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(28)
}
POST_IO
RET(28)
}
@@
-9867,7
+9879,7
@@
OPCODE(0x2F39)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(28)
}
POST_IO
RET(28)
}
@@
-9948,7
+9960,7
@@
OPCODE(0x213A)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(24)
}
POST_IO
RET(24)
}
@@
-10072,7
+10084,7
@@
OPCODE(0x2F3A)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(24)
}
POST_IO
RET(24)
}
@@
-10153,7
+10165,7
@@
OPCODE(0x213B)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(26)
}
POST_IO
RET(26)
}
@@
-10277,7
+10289,7
@@
OPCODE(0x2F3B)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(26)
}
POST_IO
RET(26)
}
@@
-10348,7
+10360,7
@@
OPCODE(0x213C)
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
PRE_IO
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(20)
}
POST_IO
RET(20)
}
@@
-10460,7
+10472,7
@@
OPCODE(0x2F3C)
adr = AREG(7) - 4;
AREG(7) = adr;
PRE_IO
adr = AREG(7) - 4;
AREG(7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(20)
}
POST_IO
RET(20)
}
@@
-10541,7
+10553,7
@@
OPCODE(0x211F)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(20)
}
POST_IO
RET(20)
}
@@
-10665,7
+10677,7
@@
OPCODE(0x2F1F)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(20)
}
POST_IO
RET(20)
}
@@
-10746,7
+10758,7
@@
OPCODE(0x2127)
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
flag_N = res >> 24;
adr = AREG((Opcode >> 9) & 7) - 4;
AREG((Opcode >> 9) & 7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(22)
}
POST_IO
RET(22)
}
@@
-10870,7
+10882,7
@@
OPCODE(0x2F27)
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_
DEC_
F(adr, res)
POST_IO
RET(22)
}
POST_IO
RET(22)
}
@@
-16552,9
+16564,7
@@
OPCODE(0x46C0)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(12)
RET(4)
}
RET(12)
@@
-16583,9
+16593,7
@@
OPCODE(0x46D0)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(16)
RET(4)
}
RET(16)
@@
-16615,9
+16623,7
@@
OPCODE(0x46D8)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(16)
RET(4)
}
RET(16)
@@
-16647,9
+16653,7
@@
OPCODE(0x46E0)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(18)
RET(4)
}
RET(18)
@@
-16679,9
+16683,7
@@
OPCODE(0x46E8)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(20)
RET(4)
}
RET(20)
@@
-16711,9
+16713,7
@@
OPCODE(0x46F0)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(22)
RET(4)
}
RET(22)
@@
-16743,9
+16743,7
@@
OPCODE(0x46F8)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(20)
RET(4)
}
RET(20)
@@
-16774,9
+16772,7
@@
OPCODE(0x46F9)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(24)
RET(4)
}
RET(24)
@@
-16802,13
+16798,11
@@
OPCODE(0x46FA)
ASP = res;
}
POST_IO
ASP = res;
}
POST_IO
- CHECK_INT_TO_JUMP(2
4
)
+ CHECK_INT_TO_JUMP(2
0
)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(20)
RET(4)
}
RET(20)
@@
-16838,9
+16832,7
@@
OPCODE(0x46FB)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(22)
RET(4)
}
RET(22)
@@
-16866,9
+16858,7
@@
OPCODE(0x46FC)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(16)
RET(4)
}
RET(16)
@@
-16898,9
+16888,7
@@
OPCODE(0x46DF)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(16)
RET(4)
}
RET(16)
@@
-16930,9
+16918,7
@@
OPCODE(0x46E7)
}
else
{
}
else
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
RET(18)
RET(4)
}
RET(18)
@@
-18455,28
+18441,22
@@
RET(10)
// ILLEGAL
OPCODE(0x4AFC)
{
// ILLEGAL
OPCODE(0x4AFC)
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_ILLEGAL_INSTRUCTION_EX);
-RET(4)
+ SET_PC(execute_exception(M68K_ILLEGAL_INSTRUCTION_EX, GET_PC-2, GET_SR));
+RET(0)
}
// ILLEGAL A000-AFFF
OPCODE(0xA000)
{
}
// ILLEGAL A000-AFFF
OPCODE(0xA000)
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_1010_EX);
-RET(4)
+ SET_PC(execute_exception(M68K_1010_EX, GET_PC-2, GET_SR));
+RET(0)
}
// ILLEGAL F000-FFFF
OPCODE(0xF000)
{
}
// ILLEGAL F000-FFFF
OPCODE(0xF000)
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_1111_EX);
-RET(4)
+ SET_PC(execute_exception(M68K_1111_EX, GET_PC-2, GET_SR));
+RET(0) // 4 already taken by exc. handler
}
// MOVEMaR
}
// MOVEMaR
@@
-19036,7
+19016,7
@@
RET(12)
// TRAP
OPCODE(0x4E40)
{
// TRAP
OPCODE(0x4E40)
{
-
execute_exception(M68K_TRAP_BASE_EX + (Opcode & 0xF
));
+
SET_PC(execute_exception(M68K_TRAP_BASE_EX + (Opcode & 0xF), GET_PC, GET_SR
));
RET(4)
}
RET(4)
}
@@
-19107,9
+19087,7
@@
OPCODE(0x4E60)
if (!flag_S)
{
if (!flag_S)
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
res = AREGu32((Opcode >> 0) & 7);
RET(4)
}
res = AREGu32((Opcode >> 0) & 7);
@@
-19125,9
+19103,7
@@
OPCODE(0x4E68)
if (!flag_S)
{
if (!flag_S)
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
res = ASP;
RET(4)
}
res = ASP;
@@
-19143,9
+19119,7
@@
OPCODE(0x4E70)
if (!flag_S)
{
if (!flag_S)
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
PRE_IO
RET(4)
}
PRE_IO
@@
-19169,9
+19143,7
@@
OPCODE(0x4E72)
if (!flag_S)
{
if (!flag_S)
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
FETCH_WORD(res);
RET(4)
}
FETCH_WORD(res);
@@
-19183,7
+19155,7
@@
OPCODE(0x4E72)
AREG(7) = ASP;
ASP = res;
}
AREG(7) = ASP;
ASP = res;
}
- m68kcontext.execinfo |= M68K_HALTED;
+ m68kcontext.execinfo |=
F
M68K_HALTED;
m68kcontext.io_cycle_counter = 0;
RET(4)
}
m68kcontext.io_cycle_counter = 0;
RET(4)
}
@@
-19196,9
+19168,7
@@
OPCODE(0x4E73)
if (!flag_S)
{
if (!flag_S)
{
- u32 oldPC=GET_PC;
- SET_PC(oldPC-2)
- execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
+ SET_PC(execute_exception(M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
RET(4)
}
PRE_IO
RET(4)
}
PRE_IO
@@
-19213,7
+19183,7
@@
OPCODE(0x4E73)
ASP = res;
}
POST_IO
ASP = res;
}
POST_IO
- m68kcontext.execinfo &= ~(
M68K_EMULATE_GROUP_0|M68K_EMULATE_TRACE|
M68K_DO_TRACE);
+ m68kcontext.execinfo &= ~(
FM68K_EMULATE_GROUP_0|FM68K_EMULATE_TRACE|F
M68K_DO_TRACE);
CHECK_INT_TO_JUMP(20)
RET(20)
}
CHECK_INT_TO_JUMP(20)
RET(20)
}
@@
-19236,7
+19206,7
@@
RET(16)
OPCODE(0x4E76)
{
if (flag_V & 0x80)
OPCODE(0x4E76)
{
if (flag_V & 0x80)
-
execute_exception(M68K_TRAPV_EX
);
+
SET_PC(execute_exception(M68K_TRAPV_EX, GET_PC, GET_SR)
);
RET(4)
}
RET(4)
}
@@
-19499,7
+19469,7
@@
OPCODE(0x4180)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
RET(10)
}
}
RET(10)
}
@@
-19517,7
+19487,7
@@
OPCODE(0x4190)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(14)
}
POST_IO
RET(14)
@@
-19537,7
+19507,7
@@
OPCODE(0x4198)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(14)
}
POST_IO
RET(14)
@@
-19557,7
+19527,7
@@
OPCODE(0x41A0)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(16)
}
POST_IO
RET(16)
@@
-19577,7
+19547,7
@@
OPCODE(0x41A8)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(18)
}
POST_IO
RET(18)
@@
-19597,7
+19567,7
@@
OPCODE(0x41B0)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(20)
}
POST_IO
RET(20)
@@
-19616,7
+19586,7
@@
OPCODE(0x41B8)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(18)
}
POST_IO
RET(18)
@@
-19635,7
+19605,7
@@
OPCODE(0x41B9)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(22)
}
POST_IO
RET(22)
@@
-19655,7
+19625,7
@@
OPCODE(0x41BA)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(18)
}
POST_IO
RET(18)
@@
-19675,7
+19645,7
@@
OPCODE(0x41BB)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(20)
}
POST_IO
RET(20)
@@
-19692,7
+19662,7
@@
OPCODE(0x41BC)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(14)
}
POST_IO
RET(14)
@@
-19712,7
+19682,7
@@
OPCODE(0x419F)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(14)
}
POST_IO
RET(14)
@@
-19732,7
+19702,7
@@
OPCODE(0x41A7)
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
if (((s32)res < 0) || (res > src))
{
flag_N = res >> 8;
-
execute_exception(M68K_CHK_EX
);
+
SET_PC(execute_exception(M68K_CHK_EX, GET_PC, GET_SR)
);
}
POST_IO
RET(16)
}
POST_IO
RET(16)
@@
-23892,7
+23862,7
@@
OPCODE(0x5048)
dst = AREGu32((Opcode >> 0) & 7);
res = dst + src;
AREG((Opcode >> 0) & 7) = res;
dst = AREGu32((Opcode >> 0) & 7);
res = dst + src;
AREG((Opcode >> 0) & 7) = res;
-#ifdef USE_CYCLONE_TIMING
_ // breaks Project-X
+#ifdef USE_CYCLONE_TIMING
RET(4)
#else
RET(8)
RET(4)
#else
RET(8)
@@
-26965,7
+26935,7
@@
OPCODE(0x80C0)
src = DREGu16((Opcode >> 0) & 7);
if (src == 0)
{
src = DREGu16((Opcode >> 0) & 7);
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(140)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(140)
#else
@@
-27013,7
+26983,7
@@
OPCODE(0x80D0)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(144)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(144)
#else
@@
-27062,7
+27032,7
@@
OPCODE(0x80D8)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(144)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(144)
#else
@@
-27111,7
+27081,7
@@
OPCODE(0x80E0)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(146)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(146)
#else
@@
-27160,7
+27130,7
@@
OPCODE(0x80E8)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(148)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(148)
#else
@@
-27209,7
+27179,7
@@
OPCODE(0x80F0)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(150)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(150)
#else
@@
-27257,7
+27227,7
@@
OPCODE(0x80F8)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(148)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(148)
#else
@@
-27305,7
+27275,7
@@
OPCODE(0x80F9)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(162)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(162)
#else
@@
-27354,7
+27324,7
@@
OPCODE(0x80FA)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(148)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(148)
#else
@@
-27403,7
+27373,7
@@
OPCODE(0x80FB)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(160)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(160)
#else
@@
-27449,7
+27419,7
@@
OPCODE(0x80FC)
FETCH_WORD(src);
if (src == 0)
{
FETCH_WORD(src);
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(144)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(144)
#else
@@
-27498,7
+27468,7
@@
OPCODE(0x80DF)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(144)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(144)
#else
@@
-27547,7
+27517,7
@@
OPCODE(0x80E7)
READ_WORD_F(adr, src)
if (src == 0)
{
READ_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
RET(146)
#else
#ifdef USE_CYCLONE_TIMING_DIV
RET(146)
#else
@@
-27593,9
+27563,9
@@
OPCODE(0x81C0)
src = (s32)DREGs16((Opcode >> 0) & 7);
if (src == 0)
{
src = (s32)DREGs16((Opcode >> 0) & 7);
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81C0
;
#endif
RET(10)
}
#endif
RET(10)
}
@@
-27607,7
+27577,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81C0
;
#endif
RET(50)
}
#endif
RET(50)
}
@@
-27621,7
+27591,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81C0
;
#endif
RET(80)
}
#endif
RET(80)
}
@@
-27633,7
+27603,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81C0:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(108)
}
#endif
RET(108)
}
@@
-27649,9
+27619,9
@@
OPCODE(0x81D0)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81D0
;
#endif
RET(14)
}
#endif
RET(14)
}
@@
-27663,7
+27633,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81D0
;
#endif
RET(54)
}
#endif
RET(54)
}
@@
-27677,7
+27647,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81D0
;
#endif
RET(84)
}
#endif
RET(84)
}
@@
-27689,7
+27659,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81D0:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(112)
}
#endif
RET(112)
}
@@
-27706,9
+27676,9
@@
OPCODE(0x81D8)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81D8
;
#endif
RET(14)
}
#endif
RET(14)
}
@@
-27720,7
+27690,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81D8
;
#endif
RET(54)
}
#endif
RET(54)
}
@@
-27734,7
+27704,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81D8
;
#endif
RET(84)
}
#endif
RET(84)
}
@@
-27746,7
+27716,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81D8:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(112)
}
#endif
RET(112)
}
@@
-27763,9
+27733,9
@@
OPCODE(0x81E0)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81E0
;
#endif
RET(16)
}
#endif
RET(16)
}
@@
-27777,7
+27747,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81E0
;
#endif
RET(56)
}
#endif
RET(56)
}
@@
-27791,7
+27761,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81E0
;
#endif
RET(86)
}
#endif
RET(86)
}
@@
-27803,7
+27773,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81E0:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(114)
}
#endif
RET(114)
}
@@
-27820,9
+27790,9
@@
OPCODE(0x81E8)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81E8
;
#endif
RET(18)
}
#endif
RET(18)
}
@@
-27834,7
+27804,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81E8
;
#endif
RET(58)
}
#endif
RET(58)
}
@@
-27848,7
+27818,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81E8
;
#endif
RET(88)
}
#endif
RET(88)
}
@@
-27860,7
+27830,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81E8:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(116)
}
#endif
RET(116)
}
@@
-27877,9
+27847,9
@@
OPCODE(0x81F0)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81F0
;
#endif
RET(20)
}
#endif
RET(20)
}
@@
-27891,7
+27861,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81F0
;
#endif
RET(60)
}
#endif
RET(60)
}
@@
-27905,7
+27875,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81F0
;
#endif
RET(90)
}
#endif
RET(90)
}
@@
-27917,7
+27887,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81F0:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(118)
}
#endif
RET(118)
}
@@
-27933,9
+27903,9
@@
OPCODE(0x81F8)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81F8
;
#endif
RET(18)
}
#endif
RET(18)
}
@@
-27947,7
+27917,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81F8
;
#endif
RET(58)
}
#endif
RET(58)
}
@@
-27961,7
+27931,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81F8
;
#endif
RET(88)
}
#endif
RET(88)
}
@@
-27973,7
+27943,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81F8:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(116)
}
#endif
RET(116)
}
@@
-27989,9
+27959,9
@@
OPCODE(0x81F9)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81F9
;
#endif
RET(22)
}
#endif
RET(22)
}
@@
-28003,7
+27973,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81F9
;
#endif
RET(62)
}
#endif
RET(62)
}
@@
-28017,7
+27987,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81F9
;
#endif
RET(92)
}
#endif
RET(92)
}
@@
-28029,7
+27999,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81F9:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(120)
}
#endif
RET(120)
}
@@
-28046,9
+28016,9
@@
OPCODE(0x81FA)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81FA
;
#endif
RET(18)
}
#endif
RET(18)
}
@@
-28060,7
+28030,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81FA
;
#endif
RET(58)
}
#endif
RET(58)
}
@@
-28074,7
+28044,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81FA
;
#endif
RET(88)
}
#endif
RET(88)
}
@@
-28086,7
+28056,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81FA:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(116)
}
#endif
RET(116)
}
@@
-28103,9
+28073,9
@@
OPCODE(0x81FB)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81FB
;
#endif
RET(20)
}
#endif
RET(20)
}
@@
-28117,7
+28087,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81FB
;
#endif
RET(60)
}
#endif
RET(60)
}
@@
-28131,7
+28101,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81FB
;
#endif
RET(90)
}
#endif
RET(90)
}
@@
-28143,7
+28113,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81FB:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(118)
}
#endif
RET(118)
}
@@
-28157,9
+28127,9
@@
OPCODE(0x81FC)
FETCH_SWORD(src);
if (src == 0)
{
FETCH_SWORD(src);
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81FC
;
#endif
RET(14)
}
#endif
RET(14)
}
@@
-28171,7
+28141,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81FC
;
#endif
RET(54)
}
#endif
RET(54)
}
@@
-28185,7
+28155,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81FC
;
#endif
RET(84)
}
#endif
RET(84)
}
@@
-28197,7
+28167,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81FC:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(112)
}
#endif
RET(112)
}
@@
-28214,9
+28184,9
@@
OPCODE(0x81DF)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81DF
;
#endif
RET(14)
}
#endif
RET(14)
}
@@
-28228,7
+28198,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81DF
;
#endif
RET(54)
}
#endif
RET(54)
}
@@
-28242,7
+28212,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81DF
;
#endif
RET(84)
}
#endif
RET(84)
}
@@
-28254,7
+28224,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81DF:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(112)
}
#endif
RET(112)
}
@@
-28271,9
+28241,9
@@
OPCODE(0x81E7)
READSX_WORD_F(adr, src)
if (src == 0)
{
READSX_WORD_F(adr, src)
if (src == 0)
{
-
execute_exception(M68K_ZERO_DIVIDE_EX
);
+
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR)
);
#ifdef USE_CYCLONE_TIMING_DIV
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81E7
;
#endif
RET(16)
}
#endif
RET(16)
}
@@
-28285,7
+28255,7
@@
goto end;
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
res = 0;
DREGu32((Opcode >> 9) & 7) = res;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81E7
;
#endif
RET(56)
}
#endif
RET(56)
}
@@
-28299,7
+28269,7
@@
goto end;
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
-goto end;
+goto end
81E7
;
#endif
RET(86)
}
#endif
RET(86)
}
@@
-28311,7
+28281,7
@@
goto end;
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
-end
:
m68kcontext.io_cycle_counter -= 50;
+end
81E7:
m68kcontext.io_cycle_counter -= 50;
#endif
RET(114)
}
#endif
RET(114)
}
@@
-28333,6
+28303,7
@@
RET(4)
}
// SUBaD
}
// SUBaD
+#if 0
OPCODE(0x9008)
{
u32 adr, res;
OPCODE(0x9008)
{
u32 adr, res;
@@
-28352,6
+28323,7
@@
OPCODE(0x9008)
*/
RET(4)
}
*/
RET(4)
}
+#endif
// SUBaD
OPCODE(0x9010)
// SUBaD
OPCODE(0x9010)
@@
-30026,7
+29998,11
@@
OPCODE(0x90D0)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(12)
+#else
RET(10)
RET(10)
+#endif
}
// SUBA
}
// SUBA
@@
-30043,7
+30019,11
@@
OPCODE(0x90D8)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(12)
+#else
RET(10)
RET(10)
+#endif
}
// SUBA
}
// SUBA
@@
-30060,7
+30040,11
@@
OPCODE(0x90E0)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(14)
+#else
RET(12)
RET(12)
+#endif
}
// SUBA
}
// SUBA
@@
-30077,7
+30061,11
@@
OPCODE(0x90E8)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(14)
RET(14)
+#endif
}
// SUBA
}
// SUBA
@@
-30094,7
+30082,11
@@
OPCODE(0x90F0)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(18)
+#else
RET(16)
RET(16)
+#endif
}
// SUBA
}
// SUBA
@@
-30110,7
+30102,11
@@
OPCODE(0x90F8)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(14)
RET(14)
+#endif
}
// SUBA
}
// SUBA
@@
-30126,7
+30122,11
@@
OPCODE(0x90F9)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(20)
+#else
RET(18)
RET(18)
+#endif
}
// SUBA
}
// SUBA
@@
-30143,7
+30143,11
@@
OPCODE(0x90FA)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(14)
RET(14)
+#endif
}
// SUBA
}
// SUBA
@@
-30160,7
+30164,11
@@
OPCODE(0x90FB)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(18)
+#else
RET(16)
RET(16)
+#endif
}
// SUBA
}
// SUBA
@@
-30190,7
+30198,11
@@
OPCODE(0x90DF)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(12)
+#else
RET(10)
RET(10)
+#endif
}
// SUBA
}
// SUBA
@@
-30207,7
+30219,11
@@
OPCODE(0x90E7)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(14)
+#else
RET(12)
RET(12)
+#endif
}
// SUBA
}
// SUBA
@@
-30461,6
+30477,7
@@
RET(4)
}
// CMP
}
// CMP
+#if 0
OPCODE(0xB008)
{
u32 adr, res;
OPCODE(0xB008)
{
u32 adr, res;
@@
-30479,6
+30496,7
@@
OPCODE(0xB008)
*/
RET(4)
}
*/
RET(4)
}
+#endif
// CMP
OPCODE(0xB010)
// CMP
OPCODE(0xB010)
@@
-34756,6
+34774,7
@@
RET(4)
}
// ADDaD
}
// ADDaD
+#if 0
OPCODE(0xD008)
{
u32 adr, res;
OPCODE(0xD008)
{
u32 adr, res;
@@
-34775,6
+34794,7
@@
OPCODE(0xD008)
*/
RET(4)
}
*/
RET(4)
}
+#endif
// ADDaD
OPCODE(0xD010)
// ADDaD
OPCODE(0xD010)
@@
-36449,7
+36469,11
@@
OPCODE(0xD0D0)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(12)
+#else
RET(10)
RET(10)
+#endif
}
// ADDA
}
// ADDA
@@
-36466,7
+36490,11
@@
OPCODE(0xD0D8)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(12)
+#else
RET(10)
RET(10)
+#endif
}
// ADDA
}
// ADDA
@@
-36483,7
+36511,11
@@
OPCODE(0xD0E0)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(14)
+#else
RET(12)
RET(12)
+#endif
}
// ADDA
}
// ADDA
@@
-36500,7
+36532,11
@@
OPCODE(0xD0E8)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(14)
RET(14)
+#endif
}
// ADDA
}
// ADDA
@@
-36517,7
+36553,11
@@
OPCODE(0xD0F0)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(18)
+#else
RET(16)
RET(16)
+#endif
}
// ADDA
}
// ADDA
@@
-36533,7
+36573,11
@@
OPCODE(0xD0F8)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(14)
RET(14)
+#endif
}
// ADDA
}
// ADDA
@@
-36549,7
+36593,11
@@
OPCODE(0xD0F9)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(20)
+#else
RET(18)
RET(18)
+#endif
}
// ADDA
}
// ADDA
@@
-36566,7
+36614,11
@@
OPCODE(0xD0FA)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(14)
RET(14)
+#endif
}
// ADDA
}
// ADDA
@@
-36583,7
+36635,11
@@
OPCODE(0xD0FB)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(18)
+#else
RET(16)
RET(16)
+#endif
}
// ADDA
}
// ADDA
@@
-36613,7
+36669,11
@@
OPCODE(0xD0DF)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(12)
+#else
RET(10)
RET(10)
+#endif
}
// ADDA
}
// ADDA
@@
-36630,7
+36690,11
@@
OPCODE(0xD0E7)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(14)
+#else
RET(12)
RET(12)
+#endif
}
// ADDA
}
// ADDA