+static u32 io_read_sio2_status()
+{
+ return 0x80;
+}
+
+#if !defined(DRC_DBG) && defined(__arm__)
+
+static void map_rcnt_rcount0(u32 mode)
+{
+ if (mode & 0x001) { // sync mode
+ map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1);
+ }
+ else if (mode & 0x100) { // pixel clock
+ map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
+ }
+ else {
+ map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
+ }
+}
+
+static void map_rcnt_rcount1(u32 mode)
+{
+ if (mode & 0x001) { // sync mode
+ map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1);
+ }
+ else if (mode & 0x100) { // hcnt
+ map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
+ }
+ else {
+ map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
+ }
+}
+
+static void map_rcnt_rcount2(u32 mode)
+{
+ if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode
+ map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
+ map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
+ }
+ else if (mode & 0x200) { // clk/8
+ map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
+ map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
+ }
+ else {
+ map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
+ map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
+ }
+}
+
+#else
+#define map_rcnt_rcount0(mode)
+#define map_rcnt_rcount1(mode)
+#define map_rcnt_rcount2(mode)
+#endif
+