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spu: patch up more savestate issues
[pcsx_rearmed.git]
/
libpcsxcore
/
psxdma.c
diff --git
a/libpcsxcore/psxdma.c
b/libpcsxcore/psxdma.c
index
31424b3
..
fa8f339
100644
(file)
--- a/
libpcsxcore/psxdma.c
+++ b/
libpcsxcore/psxdma.c
@@
-64,7
+64,10
@@
void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
break;
SPU_writeDMAMem(ptr, words_copy * 2, psxRegs.cycle);
HW_DMA4_MADR = SWAPu32(madr + words_copy * 2);
break;
SPU_writeDMAMem(ptr, words_copy * 2, psxRegs.cycle);
HW_DMA4_MADR = SWAPu32(madr + words_copy * 2);
- SPUDMA_INT(words * 4);
+ // This should be much slower, like 12+ cycles/byte, it's like
+ // that because the CPU runs too fast and fifo is not emulated.
+ // See also set_dma_end().
+ set_event(PSXINT_SPUDMA, words * 4);
return;
case 0x01000200: //spu to cpu transfer
return;
case 0x01000200: //spu to cpu transfer
@@
-75,7
+78,7
@@
void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
psxCpu->Clear(madr, words_copy);
HW_DMA4_MADR = SWAPu32(madr + words_copy * 4);
psxCpu->Clear(madr, words_copy);
HW_DMA4_MADR = SWAPu32(madr + words_copy * 4);
-
SPUDMA_INT(
words * 4);
+
set_event(PSXINT_SPUDMA,
words * 4);
return;
default:
return;
default:
@@
-153,8
+156,10
@@
void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
HW_DMA2_MADR = SWAPu32(madr + words_copy * 4);
HW_DMA2_MADR = SWAPu32(madr + words_copy * 4);
+ // careful: gpu_state_change() also messes with this
+ psxRegs.gpuIdleAfter = psxRegs.cycle + words / 4 + 16;
// already 32-bit word size ((size * 4) / 4)
// already 32-bit word size ((size * 4) / 4)
-
GPUDMA_INT(
words / 4);
+
set_event(PSXINT_GPUDMA,
words / 4);
return;
case 0x01000201: // mem2vram
return;
case 0x01000201: // mem2vram
@@
-174,8
+179,10
@@
void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
HW_DMA2_MADR = SWAPu32(madr);
HW_DMA2_MADR = SWAPu32(madr);
+ // careful: gpu_state_change() also messes with this
+ psxRegs.gpuIdleAfter = psxRegs.cycle + words / 4 + 16;
// already 32-bit word size ((size * 4) / 4)
// already 32-bit word size ((size * 4) / 4)
-
GPUDMA_INT(
words / 4);
+
set_event(PSXINT_GPUDMA,
words / 4);
return;
case 0x01000401: // dma chain
return;
case 0x01000401: // dma chain
@@
-192,14
+199,14
@@
void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
if ((int)size <= 0)
size = gpuDmaChainSize(madr);
if ((int)size <= 0)
size = gpuDmaChainSize(madr);
- HW_GPU_STATUS &= SWAP32(~PSXGPU_nBUSY);
HW_DMA2_MADR = SWAPu32(madr_next);
// Tekken 3 = use 1.0 only (not 1.5x)
// Einhander = parse linked list in pieces (todo)
// Rebel Assault 2 = parse linked list in pieces (todo)
HW_DMA2_MADR = SWAPu32(madr_next);
// Tekken 3 = use 1.0 only (not 1.5x)
// Einhander = parse linked list in pieces (todo)
// Rebel Assault 2 = parse linked list in pieces (todo)
- GPUDMA_INT(size);
+ psxRegs.gpuIdleAfter = psxRegs.cycle + size + 16;
+ set_event(PSXINT_GPUDMA, size);
return;
default:
return;
default:
@@
-214,10
+221,11
@@
void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
void gpuInterrupt() {
if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000)))
{
void gpuInterrupt() {
if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000)))
{
- u32 size, madr_next = 0xffffff;
- size = GPU_dmaChain((u32 *)psxM,
HW_DMA2_MADR
& 0x1fffff, &madr_next);
+ u32 size, madr_next = 0xffffff
, madr = SWAPu32(HW_DMA2_MADR)
;
+ size = GPU_dmaChain((u32 *)psxM,
madr
& 0x1fffff, &madr_next);
HW_DMA2_MADR = SWAPu32(madr_next);
HW_DMA2_MADR = SWAPu32(madr_next);
- GPUDMA_INT(size);
+ psxRegs.gpuIdleAfter = psxRegs.cycle + size + 64;
+ set_event(PSXINT_GPUDMA, size);
return;
}
if (HW_DMA2_CHCR & SWAP32(0x01000000))
return;
}
if (HW_DMA2_CHCR & SWAP32(0x01000000))
@@
-225,7
+233,6
@@
void gpuInterrupt() {
HW_DMA2_CHCR &= SWAP32(~0x01000000);
DMA_INTERRUPT(2);
}
HW_DMA2_CHCR &= SWAP32(~0x01000000);
DMA_INTERRUPT(2);
}
- HW_GPU_STATUS |= SWAP32(PSXGPU_nBUSY); // GPU no longer busy
}
void psxDma6(u32 madr, u32 bcr, u32 chcr) {
}
void psxDma6(u32 madr, u32 bcr, u32 chcr) {
@@
-238,7
+245,7
@@
void psxDma6(u32 madr, u32 bcr, u32 chcr) {
mem = getDmaRam(madr, &words_max);
if (mem == INVALID_PTR) {
log_unhandled("bad6 dma madr %x\n", madr);
mem = getDmaRam(madr, &words_max);
if (mem == INVALID_PTR) {
log_unhandled("bad6 dma madr %x\n", madr);
- HW_DMA6_CHCR &= SWAP32(~0x
0
1000000);
+ HW_DMA6_CHCR &= SWAP32(~0x
1
1000000);
DMA_INTERRUPT(6);
return;
}
DMA_INTERRUPT(6);
return;
}
@@
-252,10
+259,9
@@
void psxDma6(u32 madr, u32 bcr, u32 chcr) {
}
*++mem = SWAP32(0xffffff);
}
*++mem = SWAP32(0xffffff);
- //GPUOTCDMA_INT(size);
// halted
psxRegs.cycle += words;
// halted
psxRegs.cycle += words;
-
GPUOTCDMA_INT(
16);
+
set_event(PSXINT_GPUOTCDMA,
16);
return;
}
else {
return;
}
else {
@@
-263,7
+269,7
@@
void psxDma6(u32 madr, u32 bcr, u32 chcr) {
log_unhandled("*** DMA6 OT - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
}
log_unhandled("*** DMA6 OT - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
}
- HW_DMA6_CHCR &= SWAP32(~0x
0
1000000);
+ HW_DMA6_CHCR &= SWAP32(~0x
1
1000000);
DMA_INTERRUPT(6);
}
DMA_INTERRUPT(6);
}
@@
-271,7
+277,7
@@
void gpuotcInterrupt()
{
if (HW_DMA6_CHCR & SWAP32(0x01000000))
{
{
if (HW_DMA6_CHCR & SWAP32(0x01000000))
{
- HW_DMA6_CHCR &= SWAP32(~0x
0
1000000);
+ HW_DMA6_CHCR &= SWAP32(~0x
1
1000000);
DMA_INTERRUPT(6);
}
}
DMA_INTERRUPT(6);
}
}