- switch (add) {
- case 0x1f801040:
- sioWrite8((unsigned char)value);
- sioWrite8((unsigned char)((value&0xff) >> 8));
- sioWrite8((unsigned char)((value&0xff) >> 16));
- sioWrite8((unsigned char)((value&0xff) >> 24));
-#ifdef PAD_LOG
- PAD_LOG("sio write32 %x\n", value);
-#endif
- return;\r
-#ifdef ENABLE_SIO1API
- case 0x1f801050:
- SIO1_writeData32(value);
- return;\r
-#endif
-#ifdef PSXHW_LOG
- case 0x1f801060:
- PSXHW_LOG("RAM size write %x\n", value);
- psxHu32ref(add) = SWAPu32(value);
- return; // Ram size
-#endif
-
- case 0x1f801070:
-#ifdef PSXHW_LOG
- PSXHW_LOG("IREG 32bit write %x\n", value);
-#endif
- if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
- if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
- psxHu32ref(0x1070) &= SWAPu32((psxHu32(0x1074) & value));
- return;
- case 0x1f801074:
-#ifdef PSXHW_LOG
- PSXHW_LOG("IMASK 32bit write %x\n", value);
-#endif
- psxHu32ref(0x1074) = SWAPu32(value);
- if (psxHu32ref(0x1070) & value)
- new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
- return;
-
-#ifdef PSXHW_LOG
- case 0x1f801080:
- PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
- HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
- case 0x1f801084:
- PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
- HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr
-#endif
- case 0x1f801088:
-#ifdef PSXHW_LOG
- PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
-#endif
- DmaExec(0); // DMA0 chcr (MDEC in DMA)
- return;
-
-#ifdef PSXHW_LOG
- case 0x1f801090:
- PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
- HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
- case 0x1f801094:
- PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
- HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr
-#endif
- case 0x1f801098:
-#ifdef PSXHW_LOG
- PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
-#endif
- DmaExec(1); // DMA1 chcr (MDEC out DMA)
- return;
-
-#ifdef PSXHW_LOG
- case 0x1f8010a0:
- PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
- HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
- case 0x1f8010a4:
- PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
- HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr
-#endif
- case 0x1f8010a8:
-#ifdef PSXHW_LOG
- PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
-#endif
- DmaExec(2); // DMA2 chcr (GPU DMA)
- return;
-
-#ifdef PSXHW_LOG
- case 0x1f8010b0:
- PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
- HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
- case 0x1f8010b4:
- PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
- HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr
-#endif
- case 0x1f8010b8:
-#ifdef PSXHW_LOG
- PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
-#endif
- DmaExec(3); // DMA3 chcr (CDROM DMA)
-
- return;
-
-#ifdef PSXHW_LOG
- case 0x1f8010c0:
- PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
- HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
- case 0x1f8010c4:
- PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
- HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr
-#endif
- case 0x1f8010c8:
-#ifdef PSXHW_LOG
- PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
-#endif
- DmaExec(4); // DMA4 chcr (SPU DMA)
- return;
-
-#if 0
- case 0x1f8010d0: break; //DMA5write_madr();
- case 0x1f8010d4: break; //DMA5write_bcr();
- case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed
-#endif
-
-#ifdef PSXHW_LOG
- case 0x1f8010e0:
- PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
- HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
- case 0x1f8010e4:
- PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
- HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr
-#endif
- case 0x1f8010e8:
-#ifdef PSXHW_LOG
- PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
-#endif
- DmaExec(6); // DMA6 chcr (OT clear)
- return;
-
-#ifdef PSXHW_LOG
- case 0x1f8010f0:
- PSXHW_LOG("DMA PCR 32bit write %x\n", value);
- HW_DMA_PCR = SWAPu32(value);
- return;
-#endif
-
- case 0x1f8010f4:
-#ifdef PSXHW_LOG
- PSXHW_LOG("DMA ICR 32bit write %x\n", value);
-#endif
- {
- u32 tmp = (~value) & SWAPu32(HW_DMA_ICR);
- HW_DMA_ICR = SWAPu32(((tmp ^ value) & 0xffffff) ^ tmp);
+ switch (add & 0xffff) {
+ case 0x1040: sioWrite8(value); return;
+ case 0x1070: psxHwWriteIstat(value); return;
+ case 0x1074: psxHwWriteImask(value); return;
+ case 0x1088: // DMA0 chcr (MDEC in DMA)
+ case 0x108c: psxHwWriteChcr0(value); return;
+ case 0x1098: // DMA1 chcr (MDEC out DMA)
+ case 0x109c: psxHwWriteChcr1(value); return;
+ case 0x10a8: // DMA2 chcr (GPU DMA)
+ case 0x10ac: psxHwWriteChcr2(value); return;
+ case 0x10b8: // DMA3 chcr (CDROM DMA)
+ case 0x10bc: psxHwWriteChcr3(value); return;
+ case 0x10c8: // DMA4 chcr (SPU DMA)
+ case 0x10cc: psxHwWriteChcr4(value); return;
+ case 0x10e8: // DMA6 chcr (OT clear)
+ case 0x10ec: psxHwWriteChcr6(value); return;
+ case 0x10f4: psxHwWriteDmaIcr32(value); return;
+
+ case 0x1810: GPU_writeData(value); return;
+ case 0x1814: psxHwWriteGpuSR(value); return;
+ case 0x1820: mdecWrite0(value); break;
+ case 0x1824: mdecWrite1(value); break;
+
+ case 0x1100: psxRcntWcount(0, value & 0xffff); return;
+ case 0x1104: psxRcntWmode(0, value); return;
+ case 0x1108: psxRcntWtarget(0, value & 0xffff); return;
+ case 0x1110: psxRcntWcount(1, value & 0xffff); return;
+ case 0x1114: psxRcntWmode(1, value); return;
+ case 0x1118: psxRcntWtarget(1, value & 0xffff); return;
+ case 0x1120: psxRcntWcount(2, value & 0xffff); return;
+ case 0x1124: psxRcntWmode(2, value); return;
+ case 0x1128: psxRcntWtarget(2, value & 0xffff); return;
+
+ case 0x1044:
+ case 0x1048:
+ case 0x104c:
+ case 0x1050:
+ case 0x1054:
+ case 0x1058:
+ case 0x105c:
+ case 0x1800:
+ log_unhandled("unhandled w32 %08x %08x @%08x\n", add, value, psxRegs.pc);
+ break;
+
+ default:
+ if (0x1f801c00 <= add && add < 0x1f802000) {
+ SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
+ SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);