- break;
- case 0x8001:ROM_BANK8(0xA000,V); break;
- case 0x8002:VROM_BANK2(0x0000,V);break;
- case 0x8003:VROM_BANK2(0x0800,V);break;
- case 0xc000:IRQLatch=V;break;
- case 0xc001:IRQCount=IRQLatch;break;
- case 0xc003:IRQa=0;break;
- case 0xc002:IRQa=1;break;
- case 0xe000:mapbyte1[0]=1;MIRROR_SET((V>>6)&1);break;
+ break;
+ case 0x8001:ROM_BANK8(0xA000,V); break;
+ case 0x8002:VROM_BANK2(0x0000,V);break;
+ case 0x8003:VROM_BANK2(0x0800,V);break;
+ }
+}
+
+static DECLFW(Mapper48_HiWrite)
+{
+ switch(A&0xF003)
+ {
+ case 0xc000:IRQLatch=V;break;
+ case 0xc001:IRQCount=IRQLatch;break;
+ case 0xc003:IRQa=0;X6502_IRQEnd(FCEU_IQEXT);break;
+ case 0xc002:IRQa=1;break;
+ case 0xe000:MIRROR_SET((V>>6)&1);break;