+// the mask register is inconsistent, CMD is supposed to be a mask,
+// while others are actually irq trigger enables?
+// TODO: test on hw..
+void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
+{
+ Pico32x.sh2irqs |= mask & P32XI_VRES;
+ Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
+ Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
+
+ p32x_update_irls(sh2, m68k_cycles);
+}
+
+void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
+{
+ if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
+ Pico32x.sh2irqi[0] |= P32XI_CMD;
+ else
+ Pico32x.sh2irqi[0] &= ~P32XI_CMD;
+
+ if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
+ Pico32x.sh2irqi[1] |= P32XI_CMD;
+ else
+ Pico32x.sh2irqi[1] &= ~P32XI_CMD;
+
+ p32x_update_irls(sh2, m68k_cycles);
+}
+