+// -----------------------------------------------------------------
+// SH2
+// -----------------------------------------------------------------
+
+u32 p32x_sh2_read8(u32 a, int id)
+{
+ u32 d = 0;
+
+ if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+ return Pico32xMem->sh2_rom_m[a ^ 1];
+ if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+ return Pico32xMem->sh2_rom_s[a ^ 1];
+
+ if ((a & 0xdffc0000) == 0x06000000)
+ return Pico32xMem->sdram[(a & 0x3ffff) ^ 1];
+
+ if ((a & 0xdfc00000) == 0x02000000)
+ if ((a & 0x003fffff) < Pico.romsize)
+ return Pico.rom[(a & 0x3fffff) ^ 1];
+
+ if ((a & ~0xfff) == 0xc0000000)
+ return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
+
+ if ((a & 0xdffc0000) == 0x04000000) {
+ /* XXX: overwrite readable as normal? */
+ u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
+ return dram[(a & 0x1ffff) ^ 1];
+ }
+
+ if ((a & 0xdfffff00) == 0x4000) {
+ d = p32x_sh2reg_read16(a, id);
+ goto out_16to8;
+ }
+
+ if ((a & 0xdfffff00) == 0x4100) {
+ d = p32x_vdp_read16(a);
+ if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
+ ash2_end_run(8);
+ goto out_16to8;
+ }
+
+ if ((a & 0xdfffff00) == 0x4200) {
+ d = Pico32xMem->pal[(a & 0x1ff) / 2];
+ goto out_16to8;
+ }
+
+ if ((a & 0xfffffe00) == 0xfffffe00)
+ return sh2_peripheral_read8(a, id);
+
+ elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
+ id ? 's' : 'm', a, d, sh2_pc(id));
+ return d;
+
+out_16to8:
+ if (a & 1)
+ d &= 0xff;
+ else
+ d >>= 8;
+
+ elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
+ id ? 's' : 'm', a, d, sh2_pc(id));
+ return d;
+}
+
+u32 p32x_sh2_read16(u32 a, int id)
+{
+ u32 d = 0;
+
+ if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+ return *(u16 *)(Pico32xMem->sh2_rom_m + a);
+ if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+ return *(u16 *)(Pico32xMem->sh2_rom_s + a);
+
+ if ((a & 0xdffc0000) == 0x06000000)
+ return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2];
+
+ if ((a & 0xdfc00000) == 0x02000000)
+ if ((a & 0x003fffff) < Pico.romsize)
+ return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2];
+
+ if ((a & ~0xfff) == 0xc0000000)
+ return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
+
+ if ((a & 0xdffe0000) == 0x04000000)
+ return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
+
+ if ((a & 0xdfffff00) == 0x4000) {
+ d = p32x_sh2reg_read16(a, id);
+ if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
+ return d;
+ goto out;
+ }
+
+ if ((a & 0xdfffff00) == 0x4100) {
+ d = p32x_vdp_read16(a);
+ if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
+ ash2_end_run(8);
+ goto out;
+ }
+
+ if ((a & 0xdfffff00) == 0x4200) {
+ d = Pico32xMem->pal[(a & 0x1ff) / 2];
+ goto out;
+ }
+
+ if ((a & 0xfffffe00) == 0xfffffe00)
+ return sh2_peripheral_read16(a, id);
+
+ elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
+ id ? 's' : 'm', a, d, sh2_pc(id));
+ return d;
+
+out:
+ elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
+ id ? 's' : 'm', a, d, sh2_pc(id));
+ return d;
+}
+
+u32 p32x_sh2_read32(u32 a, int id)
+{
+ if ((a & 0xfffffe00) == 0xfffffe00)
+ return sh2_peripheral_read32(a, id);
+
+// elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc());
+ return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id);
+}
+
+void p32x_sh2_write8(u32 a, u32 d, int id)
+{
+ if ((a & 0xdffffc00) == 0x4000)
+ elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
+ id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+
+ if ((a & 0xdffc0000) == 0x06000000) {
+ Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d;
+ return;
+ }
+
+ if ((a & 0xdffc0000) == 0x04000000) {
+ u8 *dram;
+ if (!(a & 0x20000) || d) {
+ dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
+ dram[(a & 0x1ffff) ^ 1] = d;
+ }
+ return;
+ }
+
+ if ((a & ~0xfff) == 0xc0000000) {
+ Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d;
+ return;
+ }
+
+ if ((a & 0xdfffff00) == 0x4100) {
+ p32x_vdp_write8(a, d);
+ return;
+ }
+
+ if ((a & 0xdfffff00) == 0x4000) {
+ p32x_sh2reg_write8(a, d, id);
+ return;
+ }
+
+ if ((a & 0xfffffe00) == 0xfffffe00) {
+ sh2_peripheral_write8(a, d, id);
+ return;
+ }
+
+ elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
+ id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+}
+
+void p32x_sh2_write16(u32 a, u32 d, int id)
+{
+ if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
+ elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
+ id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+
+ // ignore "Associative purge space"
+ if ((a & 0xf8000000) == 0x40000000)
+ return;
+
+ if ((a & 0xdffc0000) == 0x06000000) {
+ ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d;
+ return;
+ }
+
+ if ((a & ~0xfff) == 0xc0000000) {
+ ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d;
+ return;
+ }
+
+ if ((a & 0xdffc0000) == 0x04000000) {
+ u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
+ if (!(a & 0x20000)) {
+ *pd = d;
+ return;
+ }
+ // overwrite
+ if (!(d & 0xff00)) d |= *pd & 0xff00;
+ if (!(d & 0x00ff)) d |= *pd & 0x00ff;
+ *pd = d;
+ return;
+ }
+
+ if ((a & 0xdfffff00) == 0x4100) {
+ sh2_poll[id].cnt = 0; // for poll before VDP accesses
+ p32x_vdp_write16(a, d);
+ return;
+ }
+
+ if ((a & 0xdffffe00) == 0x4200) {
+ Pico32xMem->pal[(a & 0x1ff) / 2] = d;
+ Pico32x.dirty_pal = 1;
+ return;
+ }
+
+ if ((a & 0xdfffff00) == 0x4000) {
+ p32x_sh2reg_write16(a, d, id);
+ return;
+ }
+
+ if ((a & 0xfffffe00) == 0xfffffe00) {
+ sh2_peripheral_write16(a, d, id);
+ return;
+ }
+
+ elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
+ id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+}
+
+void p32x_sh2_write32(u32 a, u32 d, int id)
+{
+ if ((a & 0xfffffe00) == 0xfffffe00) {
+ sh2_peripheral_write32(a, d, id);
+ return;
+ }
+
+ p32x_sh2_write16(a, d >> 16, id);
+ p32x_sh2_write16(a + 2, d, id);
+}
+
+static const u16 msh2_code[] = {
+ // trap instructions
+ 0xaffe, // bra <self>
+ 0x0009, // nop
+ // have to wait a bit until m68k initial program finishes clearing stuff
+ // to avoid races with game SH2 code, like in Tempo
+ 0xd004, // mov.l @(_m_ok,pc), r0
+ 0xd105, // mov.l @(_cnt,pc), r1
+ 0xd205, // mov.l @(_start,pc), r2
+ 0x71ff, // add #-1, r1
+ 0x4115, // cmp/pl r1
+ 0x89fc, // bt -2
+ 0xc208, // mov.l r0, @(h'20,gbr)
+ 0x6822, // mov.l @r2, r8
+ 0x482b, // jmp @r8
+ 0x0009, // nop
+ ('M'<<8)|'_', ('O'<<8)|'K',
+ 0x0001, 0x0000,
+ 0x2200, 0x03e0 // master start pointer in ROM
+};
+
+static const u16 ssh2_code[] = {
+ 0xaffe, // bra <self>
+ 0x0009, // nop
+ // code to wait for master, in case authentic master BIOS is used
+ 0xd104, // mov.l @(_m_ok,pc), r1
+ 0xd206, // mov.l @(_start,pc), r2
+ 0xc608, // mov.l @(h'20,gbr), r0
+ 0x3100, // cmp/eq r0, r1
+ 0x8bfc, // bf #-2
+ 0xd003, // mov.l @(_s_ok,pc), r0
+ 0xc209, // mov.l r0, @(h'24,gbr)
+ 0x6822, // mov.l @r2, r8
+ 0x482b, // jmp @r8
+ 0x0009, // nop
+ ('M'<<8)|'_', ('O'<<8)|'K',
+ ('S'<<8)|'_', ('O'<<8)|'K',
+ 0x2200, 0x03e4 // slave start pointer in ROM
+};
+