+
+#ifdef EMU_F68K
+ // setup FAME fetchmap
+ for (rs = 0x90; rs < 0xa0; rs++)
+ PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom + bank - 0x900000;
+#endif
+}
+
+// -----------------------------------------------------------------
+// SH2
+// -----------------------------------------------------------------
+
+// read8
+static u32 sh2_read8_unmapped(u32 a, int id)
+{
+ elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
+ id ? 's' : 'm', a, 0, sh2_pc(id));
+ return 0;
+}
+
+static u32 sh2_read8_cs0(u32 a, int id)
+{
+ u32 d = 0;
+
+ // 0x3ff00 is veridied
+ if ((a & 0x3ff00) == 0x4000) {
+ d = p32x_sh2reg_read16(a, id);
+ goto out_16to8;
+ }
+
+ if ((a & 0x3ff00) == 0x4100) {
+ d = p32x_vdp_read16(a);
+ if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
+ ash2_end_run(8);
+ goto out_16to8;
+ }
+
+ // TODO: mirroring?
+ if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+ return Pico32xMem->sh2_rom_m[a ^ 1];
+ if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+ return Pico32xMem->sh2_rom_s[a ^ 1];
+
+ if ((a & 0x3fe00) == 0x4200) {
+ d = Pico32xMem->pal[(a & 0x1ff) / 2];
+ goto out_16to8;
+ }
+
+ return sh2_read8_unmapped(a, id);
+
+out_16to8:
+ if (a & 1)
+ d &= 0xff;
+ else
+ d >>= 8;
+
+ elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
+ id ? 's' : 'm', a, d, sh2_pc(id));
+ return d;
+}
+
+static u32 sh2_read8_da(u32 a, int id)
+{
+ return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
+}
+
+// read16
+static u32 sh2_read16_unmapped(u32 a, int id)
+{
+ elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
+ id ? 's' : 'm', a, 0, sh2_pc(id));
+ return 0;
+}
+
+static u32 sh2_read16_cs0(u32 a, int id)
+{
+ u32 d = 0;
+
+ if ((a & 0x3ff00) == 0x4000) {
+ d = p32x_sh2reg_read16(a, id);
+ if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
+ return d;
+ goto out;
+ }
+
+ if ((a & 0x3ff00) == 0x4100) {
+ d = p32x_vdp_read16(a);
+ if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
+ ash2_end_run(8);
+ goto out;
+ }
+
+ if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+ return *(u16 *)(Pico32xMem->sh2_rom_m + a);
+ if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+ return *(u16 *)(Pico32xMem->sh2_rom_s + a);
+
+ if ((a & 0x3fe00) == 0x4200) {
+ d = Pico32xMem->pal[(a & 0x1ff) / 2];
+ goto out;
+ }
+
+ return sh2_read16_unmapped(a, id);
+
+out:
+ elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
+ id ? 's' : 'm', a, d, sh2_pc(id));
+ return d;
+}
+
+static u32 sh2_read16_da(u32 a, int id)
+{
+ return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
+}
+
+static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
+{
+ return 0;
+}
+
+// write8
+static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
+{
+ elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
+ id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+ return 0;
+}
+
+static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
+{
+ elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
+ id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+
+ if ((a & 0x3ff00) == 0x4100) {
+ p32x_vdp_write8(a, d);
+ return 0;
+ }
+
+ if ((a & 0x3ff00) == 0x4000) {
+ p32x_sh2reg_write8(a, d, id);
+ return 1;
+ }
+
+ return sh2_write8_unmapped(a, d, id);
+}
+
+/* quirk: in both normal and overwrite areas only nonzero values go through */
+#define sh2_write8_dramN(n) \
+ if ((d & 0xff) != 0) { \
+ u8 *dram = (u8 *)Pico32xMem->dram[n]; \
+ dram[(a & 0x1ffff) ^ 1] = d; \
+ } \
+ return 0;
+
+static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
+{
+ sh2_write8_dramN(0);
+}
+
+static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
+{
+ sh2_write8_dramN(1);
+}
+
+static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
+{
+ u32 a1 = a & 0x3ffff;
+#ifdef DRC_SH2
+ int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
+ if (t)
+ sh2_drc_wcheck_ram(a, t, id);
+#endif
+ Pico32xMem->sdram[a1 ^ 1] = d;
+ return 0;
+}
+
+static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
+{
+ u32 a1 = a & 0xfff;
+#ifdef DRC_SH2
+ int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
+ if (t)
+ sh2_drc_wcheck_da(a, t, id);
+#endif
+ Pico32xMem->data_array[id][a1 ^ 1] = d;
+ return 0;
+}
+
+// write16
+static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
+{
+ elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
+ id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+ return 0;
+}
+
+static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
+{
+ if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
+ elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
+ id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+
+ if ((a & 0x3ff00) == 0x4100) {
+ sh2_poll[id].cnt = 0; // for poll before VDP accesses
+ p32x_vdp_write16(a, d);
+ return 0;
+ }
+
+ if ((a & 0x3fe00) == 0x4200) {
+ Pico32xMem->pal[(a & 0x1ff) / 2] = d;
+ Pico32x.dirty_pal = 1;
+ return 0;
+ }
+
+ if ((a & 0x3ff00) == 0x4000) {
+ p32x_sh2reg_write16(a, d, id);
+ return 1;
+ }
+
+ return sh2_write16_unmapped(a, d, id);
+}
+
+#define sh2_write16_dramN(n) \
+ u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
+ if (!(a & 0x20000)) { \
+ *pd = d; \
+ return 0; \
+ } \
+ /* overwrite */ \
+ if (!(d & 0xff00)) d |= *pd & 0xff00; \
+ if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
+ *pd = d; \
+ return 0
+
+static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
+{
+ sh2_write16_dramN(0);
+}
+
+static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
+{
+ sh2_write16_dramN(1);
+}
+
+static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
+{
+ u32 a1 = a & 0x3ffff;
+#ifdef DRC_SH2
+ int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
+ if (t)
+ sh2_drc_wcheck_ram(a, t, id);
+#endif
+ ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
+ return 0;
+}
+
+static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
+{
+ u32 a1 = a & 0xfff;
+#ifdef DRC_SH2
+ int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
+ if (t)
+ sh2_drc_wcheck_da(a, t, id);
+#endif
+ ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
+ return 0;
+}
+
+
+typedef struct {
+ uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
+ u32 mask;
+} sh2_memmap;
+
+typedef u32 (sh2_read_handler)(u32 a, int id);
+typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
+
+#define SH2MAP_ADDR2OFFS_R(a) \
+ ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
+
+#define SH2MAP_ADDR2OFFS_W(a) \
+ ((u32)(a) >> SH2_WRITE_SHIFT)
+
+u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
+{
+ const sh2_memmap *sh2_map = sh2->read8_map;
+ uptr p;
+
+ sh2_map += SH2MAP_ADDR2OFFS_R(a);
+ p = sh2_map->addr;
+ if (map_flag_set(p))
+ return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+ else
+ return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
+}
+
+u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
+{
+ const sh2_memmap *sh2_map = sh2->read16_map;
+ uptr p;
+
+ sh2_map += SH2MAP_ADDR2OFFS_R(a);
+ p = sh2_map->addr;
+ if (map_flag_set(p))
+ return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+ else
+ return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
+}
+
+u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
+{
+ const sh2_memmap *sh2_map = sh2->read16_map;
+ sh2_read_handler *handler;
+ u32 offs;
+ uptr p;
+
+ offs = SH2MAP_ADDR2OFFS_R(a);
+ sh2_map += offs;
+ p = sh2_map->addr;
+ if (!map_flag_set(p)) {
+ // XXX: maybe 32bit access instead with ror?
+ u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
+ return (pd[0] << 16) | pd[1];
+ }
+
+ if (offs == 0x1f)
+ return sh2_peripheral_read32(a, sh2->is_slave);
+
+ handler = (sh2_read_handler *)(p << 1);
+ return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
+}
+
+// return nonzero if write potentially causes an interrupt (used by drc)
+int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
+{
+ const void **sh2_wmap = sh2->write8_tab;
+ sh2_write_handler *wh;
+
+ wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
+ return wh(a, d, sh2->is_slave);
+}
+
+int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
+{
+ const void **sh2_wmap = sh2->write16_tab;
+ sh2_write_handler *wh;
+
+ wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
+ return wh(a, d, sh2->is_slave);