+ // SYS regs
+ cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
+ cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
+ cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
+ cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
+
+ // SH2 maps: A31,A30,A29,CS1,CS0
+ // all unmapped by default
+ for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
+ sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
+ sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
+ sh2_write8_map[i] = sh2_write8_unmapped;
+ sh2_write16_map[i] = sh2_write16_unmapped;
+ }
+
+ // "purge area"
+ for (i = 0x40; i <= 0x5f; i++) {
+ sh2_write8_map[i >> 1] =
+ sh2_write16_map[i >> 1] = sh2_write_ignore;
+ }
+
+ // CS0
+ sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
+ sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
+ sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
+ sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
+ // CS1 - ROM
+ sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
+ sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
+ sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
+ sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
+ // CS2 - DRAM - done by Pico32xSwapDRAM()
+ sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
+ sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
+ // CS3 - SDRAM
+ sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
+ sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
+ sh2_write8_map[0x06/2] = sh2_write8_sdram;
+ sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
+ sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
+ sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
+ sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
+ // SH2 data array
+ sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
+ sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
+ sh2_write8_map[0xc0/2] = sh2_write8_da;
+ sh2_write16_map[0xc0/2] = sh2_write16_da;
+ // SH2 IO
+ sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
+ sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
+ sh2_write8_map[0xff/2] = sh2_peripheral_write8;
+ sh2_write16_map[0xff/2] = sh2_peripheral_write16;
+
+ // map DRAM area, both 68k and SH2
+ Pico32xSwapDRAM(1);
+
+ msh2.read8_map = ssh2.read8_map = sh2_read8_map;
+ msh2.read16_map = ssh2.read16_map = sh2_read16_map;
+ msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
+ msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
+
+ sh2_drc_mem_setup(&msh2);
+ sh2_drc_mem_setup(&ssh2);
+}
+
+void Pico32xMemStateLoaded(void)
+{
+ bank_switch(Pico32x.regs[4 / 2]);
+ Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
+ memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
+ Pico32x.dirty_pal = 1;
+
+ Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
+ memset(&m68k_poll, 0, sizeof(m68k_poll));
+ msh2.state = 0;
+ msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
+ ssh2.state = 0;
+ ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
+
+ sh2_drc_flush_all();