+ sh2_write16_dramN(0);
+}
+
+static void sh2_write16_dram1(u32 a, u32 d, int id)
+{
+ sh2_write16_dramN(1);
+}
+
+static void sh2_write16_sdram(u32 a, u32 d, int id)
+{
+ u32 a1 = a & 0x3ffff;
+#ifdef DRC_SH2
+ int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
+ if (t)
+ sh2_drc_wcheck_ram(a, t, id);
+#endif
+ ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
+}
+
+static void sh2_write16_da(u32 a, u32 d, int id)
+{
+ u32 a1 = a & 0xfff;
+#ifdef DRC_SH2
+ int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
+ if (t)
+ sh2_drc_wcheck_da(a, t, id);
+#endif
+ ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
+}
+
+
+typedef struct {
+ uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
+ u32 mask;
+} sh2_memmap;
+
+typedef u32 (sh2_read_handler)(u32 a, int id);
+typedef void (sh2_write_handler)(u32 a, u32 d, int id);
+
+#define SH2MAP_ADDR2OFFS(a) \
+ (((a >> 25) & 3) | ((a >> 27) & 0x1c))
+
+u32 p32x_sh2_read8(u32 a, SH2 *sh2)
+{
+ const sh2_memmap *sh2_map = sh2->read8_map;
+ uptr p;
+
+ sh2_map += SH2MAP_ADDR2OFFS(a);
+ p = sh2_map->addr;
+ if (p & (1 << 31))
+ return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+ else
+ return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
+}
+
+u32 p32x_sh2_read16(u32 a, SH2 *sh2)
+{
+ const sh2_memmap *sh2_map = sh2->read16_map;
+ uptr p;
+
+ sh2_map += SH2MAP_ADDR2OFFS(a);
+ p = sh2_map->addr;
+ if (p & (1 << 31))
+ return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+ else
+ return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
+}
+
+u32 p32x_sh2_read32(u32 a, SH2 *sh2)
+{
+ const sh2_memmap *sh2_map = sh2->read16_map;
+ sh2_read_handler *handler;
+ u32 offs;
+ uptr p;
+
+ offs = SH2MAP_ADDR2OFFS(a);
+ sh2_map += offs;
+ p = sh2_map->addr;
+ if (!(p & (1 << 31))) {
+ // XXX: maybe 32bit access instead with ror?
+ u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
+ return (pd[0] << 16) | pd[1];
+ }
+
+ if (offs == 0x1f)
+ return sh2_peripheral_read32(a, sh2->is_slave);
+
+ handler = (sh2_read_handler *)(p << 1);
+ return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
+}
+
+void p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
+{
+ const void **sh2_wmap = sh2->write8_tab;
+ sh2_write_handler *wh;
+
+ wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)];
+ wh(a, d, sh2->is_slave);
+}
+
+void p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
+{
+ const void **sh2_wmap = sh2->write16_tab;
+ sh2_write_handler *wh;
+
+ wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)];
+ wh(a, d, sh2->is_slave);
+}
+
+void p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
+{
+ const void **sh2_wmap = sh2->write16_tab;
+ sh2_write_handler *handler;
+ u32 offs;
+
+ offs = SH2MAP_ADDR2OFFS(a);
+
+ if (offs == 0x1f) {
+ sh2_peripheral_write32(a, d, sh2->is_slave);