sprintf(dstrp, "mode set 4: %02x\n", (r=reg[0xC])); MVP;
sprintf(dstrp, "interlace: %i%i, cells: %i, shadow: %i\n", bit(r,2), bit(r,1), (r&0x80) ? 40 : 32, bit(r,3)); MVP;
sprintf(dstrp, "scroll size: w: %i, h: %i SRAM: %i; eeprom: %i (%i)\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,
sprintf(dstrp, "mode set 4: %02x\n", (r=reg[0xC])); MVP;
sprintf(dstrp, "interlace: %i%i, cells: %i, shadow: %i\n", bit(r,2), bit(r,1), (r&0x80) ? 40 : 32, bit(r,3)); MVP;
sprintf(dstrp, "scroll size: w: %i, h: %i SRAM: %i; eeprom: %i (%i)\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,
- !!(SRam.flags & SRF_ENABLED), !!(SRam.flags & SRF_EEPROM), SRam.eeprom_type); MVP;
- sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); MVP;
+ !!(Pico.sv.flags & SRF_ENABLED), !!(Pico.sv.flags & SRF_EEPROM), Pico.sv.eeprom_type); MVP;
+ sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", Pico.sv.start, Pico.sv.end, Pico.m.sram_reg); MVP;
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status); MVP;
sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i, cycles: %u\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count, SekCyclesDone()); MVP;
sprintf(dstrp, "M68k: PC: %06x, SR: %04x, irql: %i\n", SekPc, SekSr, SekIrqLevel); MVP;
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status); MVP;
sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i, cycles: %u\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count, SekCyclesDone()); MVP;
sprintf(dstrp, "M68k: PC: %06x, SR: %04x, irql: %i\n", SekPc, SekSr, SekIrqLevel); MVP;
unsigned int *sprite;
int code, code2, sx, sy, height;
unsigned int *sprite;
int code, code2, sx, sy, height;
link=(sprite[0]>>16)&0x7f;
if (!link) break; // End of sprites
}
if (u >= max_sprites) return;
link=(sprite[0]>>16)&0x7f;
if (!link) break; // End of sprites
}
if (u >= max_sprites) return;
oldsprite[0] = fsprite[0];
oldsprite[1] = fsprite[1];
fsprite[0] = (sprite[0] & ~0x007f01ff) | 0x000080;
fsprite[1] = (sprite[1] & ~0x01ff8000) | 0x800000;
oldreg = pvid->reg[7];
oldsprite[0] = fsprite[0];
oldsprite[1] = fsprite[1];
fsprite[0] = (sprite[0] & ~0x007f01ff) | 0x000080;
fsprite[1] = (sprite[1] & ~0x01ff8000) | 0x800000;
oldreg = pvid->reg[7];
- dump_ram_noswab(Pico.zram, "dumps/zram.bin");
- dump_ram(Pico.cram, "dumps/cram.bin");
+ dump_ram_noswab(PicoMem.zram, "dumps/zram.bin");
+ dump_ram(PicoMem.cram, "dumps/cram.bin");
- dump_ram(Pico.ram, "dumps/ram.bin");
- dump_ram(Pico.vram, "dumps/vram.bin");
- dump_ram(Pico.vsram,"dumps/vsram.bin");
+ dump_ram(PicoMem.ram, "dumps/ram.bin");
+ dump_ram(PicoMem.vram, "dumps/vram.bin");
+ dump_ram(PicoMem.vsram,"dumps/vsram.bin");
{
dump_ram(Pico_mcd->prg_ram, "dumps/prg_ram.bin");
if (Pico_mcd->s68k_regs[3]&4) // 1M mode?
{
dump_ram(Pico_mcd->prg_ram, "dumps/prg_ram.bin");
if (Pico_mcd->s68k_regs[3]&4) // 1M mode?
{
dump_ram(Pico32xMem->sdram, "dumps/sdram.bin");
dump_ram(Pico32xMem->dram[0], "dumps/dram0.bin");
{
dump_ram(Pico32xMem->sdram, "dumps/sdram.bin");
dump_ram(Pico32xMem->dram[0], "dumps/dram0.bin");
- if (/*Pico.m.z80Run &&*/ !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
- PicoSyncZ80(SekCycleCnt + line_sample * 488);
- if (PsndOut)
+ if (/*Pico.m.z80Run &&*/ !Pico.m.z80_reset && (PicoIn.opt&POPT_EN_Z80))
+ PicoSyncZ80(Pico.t.m68c_cnt + line_sample * 488);
+ if (PicoIn.sndOut)
- if (/*Pico.m.z80Run &&*/ !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80)) {
- PicoSyncZ80(SekCycleCnt + 224 * 488);
+ if (/*Pico.m.z80Run &&*/ !Pico.m.z80_reset && (PicoIn.opt&POPT_EN_Z80)) {
+ PicoSyncZ80(Pico.t.m68c_cnt + 224 * 488);
- if (/*Pico.m.z80Run &&*/ !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80)) {
- SekCycleCnt += Pico.m.pal ? 151809 : 127671; // cycles adjusted for converter
- PicoSyncZ80(SekCycleCnt);
+ if (/*Pico.m.z80Run &&*/ !Pico.m.z80_reset && (PicoIn.opt&POPT_EN_Z80)) {
+ Pico.t.m68c_cnt += Pico.m.pal ? 151809 : 127671; // cycles adjusted for converter
+ PicoSyncZ80(Pico.t.m68c_cnt);