+#define P32XS_FM (1<<15)\r
+#define P32XS_REN (1<< 7)\r
+#define P32XS_nRES (1<< 1)\r
+#define P32XS_ADEN (1<< 0)\r
+#define P32XS2_ADEN (1<< 9)\r
+#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
+#define P32XS_68S (1<< 2)\r
+#define P32XS_DMA (1<< 1)\r
+#define P32XS_RV (1<< 0)\r
+\r
+#define P32XV_nPAL (1<<15) // VDP\r
+#define P32XV_PRI (1<< 7)\r
+#define P32XV_Mx (3<< 0) // display mode mask\r
+\r
+#define P32XV_SFT (1<< 0)\r
+\r
+#define P32XV_VBLK (1<<15)\r
+#define P32XV_HBLK (1<<14)\r
+#define P32XV_PEN (1<<13)\r
+#define P32XV_nFEN (1<< 1)\r
+#define P32XV_FS (1<< 0)\r
+\r
+#define P32XP_FULL (1<<15) // PWM\r
+#define P32XP_EMPTY (1<<14)\r
+\r
+#define P32XF_68KPOLL (1 << 0)\r
+#define P32XF_MSH2POLL (1 << 1)\r
+#define P32XF_SSH2POLL (1 << 2)\r
+#define P32XF_68KVPOLL (1 << 3)\r
+#define P32XF_MSH2VPOLL (1 << 4)\r
+#define P32XF_SSH2VPOLL (1 << 5)\r
+#define P32XF_PWM_PEND (1 << 6)\r
+\r
+#define P32XI_VRES (1 << 14/2) // IRL/2\r
+#define P32XI_VINT (1 << 12/2)\r
+#define P32XI_HINT (1 << 10/2)\r
+#define P32XI_CMD (1 << 8/2)\r
+#define P32XI_PWM (1 << 6/2)\r
+\r
+// peripheral reg access\r
+#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
+\r
+// real one is 4*2, but we use more because we don't lockstep\r
+#define DMAC_FIFO_LEN (4*4)\r
+#define PWM_BUFF_LEN 1024 // in one channel samples\r
+\r
+#define SH2_DRCBLK_RAM_SHIFT 1\r
+#define SH2_DRCBLK_DA_SHIFT 1\r
+\r
+#define SH2_WRITE_SHIFT 25\r
+\r