+ elprintf(EL_IO, "z80 port %04x write %02x", a, d);
+ a &= 0xc1;
+ switch (a)
+ {
+ case 0x01:
+ Pico.ms.io_ctl = d;
+ break;
+
+ case 0x40:
+ case 0x41:
+ if (PicoOpt & POPT_EN_PSG)
+ SN76496Write(d);
+ break;
+
+ case 0x80:
+ vdp_data_write(d);
+ break;
+
+ case 0x81:
+ vdp_ctl_write(d);
+ break;
+ }
+}
+
+static int bank_mask;
+
+static void write_bank(unsigned short a, unsigned char d)
+{
+ elprintf(EL_Z80BNK, "bank %04x %02x @ %04x", a, d, z80_pc());
+ switch (a & 0x0f)
+ {
+ case 0x0c:
+ elprintf(EL_STATUS|EL_ANOMALY, "%02x written to control reg!", d);
+ break;
+ case 0x0d:
+ if (d != 0)
+ elprintf(EL_STATUS|EL_ANOMALY, "bank0 changed to %d!", d);
+ break;
+ case 0x0e:
+ d &= bank_mask;
+ z80_map_set(z80_read_map, 0x4000, 0x7fff, Pico.rom + (d << 14), 0);
+#ifdef _USE_CZ80
+ Cz80_Set_Fetch(&CZ80, 0x4000, 0x7fff, (FPTR)Pico.rom + (d << 14));
+#endif
+ break;
+ case 0x0f:
+ d &= bank_mask;
+ z80_map_set(z80_read_map, 0x8000, 0xbfff, Pico.rom + (d << 14), 0);
+#ifdef _USE_CZ80
+ Cz80_Set_Fetch(&CZ80, 0x8000, 0xbfff, (FPTR)Pico.rom + (d << 14));
+#endif
+ break;
+ }
+ Pico.ms.carthw[a & 0x0f] = d;
+}
+
+static void xwrite(unsigned int a, unsigned char d)
+{
+ elprintf(EL_IO, "z80 write [%04x] %02x", a, d);
+ if (a >= 0xc000)
+ Pico.zram[a & 0x1fff] = d;
+ if (a >= 0xfff8)
+ write_bank(a, d);
+}
+
+void PicoResetMS(void)
+{
+ z80_reset();
+ PsndReset(); // pal must be known here