+ struct z80_state *s = data;
+ memset(data, 0, Z80_STATE_SIZE);
+ strcpy(s->magic, "Z80");
+#if defined(_USE_DRZ80)
+ #define DRR8(n) (drZ80.Z80##n >> 24)
+ #define DRR16(n) (drZ80.Z80##n >> 16)
+ #define DRR16H(n) (drZ80.Z80##n >> 24)
+ #define DRR16L(n) ((drZ80.Z80##n >> 16) & 0xff)
+ s->m.a = DRR8(A); s->m.f = drZ80.Z80F;
+ s->m.b = DRR16H(BC); s->m.c = DRR16L(BC);
+ s->m.d = DRR16H(DE); s->m.e = DRR16L(DE);
+ s->m.h = DRR16H(HL); s->m.l = DRR16L(HL);
+ s->a.a = DRR8(A2); s->a.f = drZ80.Z80F2;
+ s->a.b = DRR16H(BC2); s->a.c = DRR16L(BC2);
+ s->a.d = DRR16H(DE2); s->a.e = DRR16L(DE2);
+ s->a.h = DRR16H(HL2); s->a.l = DRR16L(HL2);
+ s->i = DRR8(I); s->r = drZ80.spare;
+ s->ix = DRR16(IX); s->iy = DRR16(IY);
+ s->sp = drZ80.Z80SP - drZ80.Z80SP_BASE;
+ s->pc = drZ80.Z80PC - drZ80.Z80PC_BASE;
+ s->halted = !!(drZ80.Z80IF & 4);
+ s->iff1 = !!(drZ80.Z80IF & 1);
+ s->iff2 = !!(drZ80.Z80IF & 2);
+ s->im = drZ80.Z80IM;
+ s->irq_pending = !!drZ80.Z80_IRQ;
+ s->irq_vector[0] = drZ80.z80irqvector >> 16;
+ s->irq_vector[1] = drZ80.z80irqvector >> 8;
+ s->irq_vector[2] = drZ80.z80irqvector;
+#elif defined(_USE_CZ80)
+ {
+ const cz80_struc *CPU = &CZ80;
+ s->m.a = zA; s->m.f = zF;
+ s->m.b = zB; s->m.c = zC;
+ s->m.d = zD; s->m.e = zE;
+ s->m.h = zH; s->m.l = zL;
+ s->a.a = zA2; s->a.f = zF2;
+ s->a.b = CZ80.BC2.B.H; s->a.c = CZ80.BC2.B.L;
+ s->a.d = CZ80.DE2.B.H; s->a.e = CZ80.DE2.B.L;
+ s->a.h = CZ80.HL2.B.H; s->a.l = CZ80.HL2.B.L;
+ s->i = zI; s->r = zR;
+ s->ix = zIX; s->iy = zIY;
+ s->sp = Cz80_Get_Reg(&CZ80, CZ80_SP);
+ s->pc = Cz80_Get_Reg(&CZ80, CZ80_PC);
+ s->halted = !!Cz80_Get_Reg(&CZ80, CZ80_HALT);
+ s->iff1 = !!zIFF1;
+ s->iff2 = !!zIFF2;
+ s->im = zIM;
+ s->irq_pending = (Cz80_Get_Reg(&CZ80, CZ80_IRQ) == HOLD_LINE);
+ s->irq_vector[0] = 0xff;