+ const struct z80_state *s = data;
+ if (strcmp(s->magic, "Z80") != 0) {
+ if (z80_unpack_legacy(data) != 0)
+ goto fail;
+ elprintf(EL_STATUS, "legacy z80 state");
+ return 0;
+ }
+
+#if defined(_USE_DRZ80)
+ #define DRW8(n, v) drZ80.Z80##n = (u32)(v) << 24
+ #define DRW16(n, v) drZ80.Z80##n = (u32)(v) << 16
+ #define DRW16HL(n, h, l) drZ80.Z80##n = ((u32)(h) << 24) | ((u32)(l) << 16)
+ DRW8(A, s->m.a); drZ80.Z80F = s->m.f;
+ DRW16HL(BC, s->m.b, s->m.c);
+ DRW16HL(DE, s->m.d, s->m.e);
+ DRW16HL(HL, s->m.h, s->m.l);
+ DRW8(A2, s->a.a); drZ80.Z80F2 = s->a.f;
+ DRW16HL(BC2, s->a.b, s->a.c);
+ DRW16HL(DE2, s->a.d, s->a.e);
+ DRW16HL(HL2, s->a.h, s->a.l);
+ DRW8(I, s->i); drZ80.spare = s->r;
+ DRW16(IX, s->ix); DRW16(IY, s->iy);
+ drz80_load_pcsp(s->pc, s->sp);
+ drZ80.Z80IF = 0;
+ if (s->halted) drZ80.Z80IF |= 4;
+ if (s->iff1) drZ80.Z80IF |= 1;
+ if (s->iff2) drZ80.Z80IF |= 2;
+ drZ80.Z80IM = s->im;
+ drZ80.Z80_IRQ = s->irq_pending;
+ drZ80.z80irqvector = ((u32)s->irq_vector[0] << 16) |
+ ((u32)s->irq_vector[1] << 8) | s->irq_vector[2];
+ return 0;
+#elif defined(_USE_CZ80)
+ {
+ cz80_struc *CPU = &CZ80;
+ zA = s->m.a; zF = s->m.f;
+ zB = s->m.b; zC = s->m.c;
+ zD = s->m.d; zE = s->m.e;
+ zH = s->m.h; zL = s->m.l;
+ zA2 = s->a.a; zF2 = s->a.f;
+ CZ80.BC2.B.H = s->a.b; CZ80.BC2.B.L = s->a.c;
+ CZ80.DE2.B.H = s->a.d; CZ80.DE2.B.L = s->a.e;
+ CZ80.HL2.B.H = s->a.h; CZ80.HL2.B.L = s->a.l;
+ zI = s->i; zR = s->r;
+ zIX = s->ix; zIY = s->iy;
+ Cz80_Set_Reg(&CZ80, CZ80_SP, s->sp);
+ Cz80_Set_Reg(&CZ80, CZ80_PC, s->pc);
+ Cz80_Set_Reg(&CZ80, CZ80_HALT, s->halted);
+ Cz80_Set_Reg(&CZ80, CZ80_IFF1, s->iff1);
+ Cz80_Set_Reg(&CZ80, CZ80_IFF2, s->iff2);
+ zIM = s->im;
+ Cz80_Set_Reg(&CZ80, CZ80_IRQ, s->irq_pending ? HOLD_LINE : CLEAR_LINE);
+ return 0;
+ }