+.macro ymwrite areg, dreg addr dat
+ move.b \addr, (\areg) /* 12 addr */
+ nbcd d0 /* 6 delay to reach 17 ym cycles (M/7) */
+ move.b \dat, (\dreg) /* 12 data */
+.endm
+
+.global test_ym_stopped_tick
+test_ym_stopped_tick:
+ movem.l a2-a3, -(sp)
+ movea.l #0xa04000, a0
+ movea.l #0xa04001, a1
+ movea.l #0xc00007, a2
+ movea.l #0xfff000, a3
+
+ ymwrite a0, a1, #0x27, #0x30 /* 30 disable, clear */
+ ymwrite a0, a1, #0x26, #0xff /* 30 timer b shortest interval */
+ move.b #0x27, (a0) /* 12 addr prep */
+0:
+ btst #3, (a2)
+ beq 0b /* not blanking */
+0:
+ btst #3, (a2)
+ bne 0b /* blanking */
+
+ addq.l #1, a2
+0:
+ tst.b (a2)
+ bne 0b /* not line 0 - waiting for sequential vcnt */
+
+ move.b #0x0a, (a1) /* 12 start timer b */
+ moveq.l #0, d0
+ moveq.l #2, d1
+0:
+ move.b (a0), d0
+ and.b d1, d0
+ beq 0b
+0:
+# move.w (a2), (a3)+ /* 12 save hvcnt */
+ move.b (a2), d0
+ cmp.b (a2), d0
+ bne 0b
+ move.w d0, (a3)+
+ move.b #0x30, (a1) /* 12 stop b, clear */
+
+ move.w #(1900/10-1), d0 /* waste cycles */
+0:
+ dbra d0, 0b
+ moveq.l #0, d0
+
+ move.w (a0), (a3)+ /* 12 save status */
+ move.b #0x0a, (a1) /* 12 start b */
+0:
+ move.b (a0), d0
+ and.b d1, d0
+ beq 0b
+
+0:
+# move.w (a2), (a3)+ /* 12 save hvcnt */
+ move.b (a2), d1
+ cmp.b (a2), d1
+ bne 0b
+ move.w d1, (a3)+
+ move.w d0, (a3)+ /* 12 save status */
+
+ movem.l (sp)+, a2-a3
+ rts
+
+.global test_ym_ab_sync
+test_ym_ab_sync:
+ movea.l #0xa04000, a0
+ movea.l #0xa04001, a1
+
+ ymwrite a0, a1, #0x27, #0x30 /* 30 disable, clear */
+ ymwrite a0, a1, #0x24, #0xfc /* 30 timer a */
+ ymwrite a0, a1, #0x25, #0x01 /* 30 =15 - why 15? expected 16 */
+ ymwrite a0, a1, #0x26, #0xff /* 30 timer b shortest interval */
+ move.b #0x27, (a0) /* 12 addr prep */
+ nop
+ nop
+
+ move.b #0x0a, (a1) /* 12 start timer b */
+ moveq.l #0, d0
+ moveq.l #2, d1
+0:
+ move.b (a0), d0 /* 8 */
+ and.b d1, d0 /* 4 */
+ beq 0b /* 10|8 */
+0:
+ move.b #0x3f, (a1) /* 12 start a, clear */
+ move.w #(1800/10-1), d0 /* waste cycles */
+0:
+ dbra d0, 0b
+
+ ymwrite a0, a1, #0x24, #0x00 /* 30 show that rewriting count */
+ ymwrite a0, a1, #0x25, #0x00 /* 30 does nothing */
+ ymwrite a0, a1, #0x26, #0x00 /* 30 */
+ ymwrite a0, a1, #0x27, #0x0f /* 30 setting already set bits too */
+ moveq.l #0, d0
+ moveq.l #3, d1
+0:
+ move.b (a0), d0
+ and.b d1, d0
+ beq 0b
+ move.b (a0), d0 /* re-read, else very occasionally get 1 */
+ rts
+