.long m_read_null @ 0xB80000 - 0xBFFFFF\r
.long m_read8_vdp @ 0xC00000 - 0xC7FFFF\r
.long m_read8_vdp @ 0xC80000 - 0xCFFFFF\r
- .long m_read_null @ 0xD00000 - 0xD7FFFF\r
- .long m_read_null @ 0xD80000 - 0xDFFFFF\r
+ .long m_read8_vdp @ 0xD00000 - 0xD7FFFF\r
+ .long m_read8_vdp @ 0xD80000 - 0xDFFFFF\r
.long m_read8_ram @ 0xE00000 - 0xE7FFFF\r
.long m_read8_ram @ 0xE80000 - 0xEFFFFF\r
.long m_read8_ram @ 0xF00000 - 0xF7FFFF\r
.long m_read_null @ 0xB00000 - 0xB7FFFF\r
.long m_read_null @ 0xB80000 - 0xBFFFFF\r
.long m_read16_vdp @ 0xC00000 - 0xC7FFFF\r
- .long m_read_null @ 0xC80000 - 0xCFFFFF\r
- .long m_read_null @ 0xD00000 - 0xD7FFFF\r
- .long m_read_null @ 0xD80000 - 0xDFFFFF\r
+ .long m_read16_vdp @ 0xC80000 - 0xCFFFFF\r
+ .long m_read16_vdp @ 0xD00000 - 0xD7FFFF\r
+ .long m_read16_vdp @ 0xD80000 - 0xDFFFFF\r
.long m_read16_ram @ 0xE00000 - 0xE7FFFF\r
.long m_read16_ram @ 0xE80000 - 0xEFFFFF\r
.long m_read16_ram @ 0xF00000 - 0xF7FFFF\r
.long m_read_null @ 0xB00000 - 0xB7FFFF\r
.long m_read_null @ 0xB80000 - 0xBFFFFF\r
.long m_read32_vdp @ 0xC00000 - 0xC7FFFF\r
- .long m_read_null @ 0xC80000 - 0xCFFFFF\r
- .long m_read_null @ 0xD00000 - 0xD7FFFF\r
- .long m_read_null @ 0xD80000 - 0xDFFFFF\r
+ .long m_read32_vdp @ 0xC80000 - 0xCFFFFF\r
+ .long m_read32_vdp @ 0xD00000 - 0xD7FFFF\r
+ .long m_read32_vdp @ 0xD80000 - 0xDFFFFF\r
.long m_read32_ram @ 0xE00000 - 0xE7FFFF\r
.long m_read32_ram @ 0xE80000 - 0xEFFFFF\r
.long m_read32_ram @ 0xF00000 - 0xF7FFFF\r
orr r0, r0, #0x200000\r
cmp r0, r1\r
bgt m_read8_nosram\r
- ldr r1, [r2, #4] @ SRam.start (1ci)\r
+ ldr r1, [r2, #4] @ SRam.start\r
cmp r0, r1\r
blt m_read8_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg (1ci)\r
- sub r12,r0, #0x200000\r
- tst r1, #0x10\r
- bne m_read8_detected\r
- cmp r12,#1\r
- ble m_read8_detected\r
- tst r1, #1\r
- orrne r1, r1, #0x10\r
- strneb r1, [r3, #0x11]\r
-m_read8_detected:\r
- tst r1, #4 @ EEPROM read?\r
- ldrne r0, =SRAMReadEEPROM @ (1ci if ne)\r
- bxne r0\r
-m_read8_noteeprom:\r
- tst r1, #1\r
- beq m_read8_nosram\r
- ldr r3, [r2] @ SRam.data\r
- ldr r2, [r2, #4] @ SRam.start (1ci)\r
- sub r3, r3, r2\r
- ldrb r0, [r3, r0]\r
- bx lr\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ bne SRAMRead\r
m_read8_nosram:\r
- ldr r1, [r3, #4] @ 1ci\r
+ ldr r1, [r3, #4] @ romsize\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
ands r0, r0, #0x1e\r
beq m_read8_misc_hwreg\r
cmp r0, #4\r
- ldrle r2, =PadRead\r
movlt r0, #0\r
moveq r0, #1\r
- bxle r2\r
+ ble PadRead\r
ldr r3, =(Pico+0x22000)\r
mov r0, r0, lsr #1 @ other IO ports (Pico.ioports[a])\r
ldrb r0, [r3, r0]\r
mov r2, #0xa10000 @ games also like to poll busreq,\r
orr r2, r2, #0x001100 @ so we'll try it now\r
cmp r0, r2\r
- ldreq r2, =z80ReadBusReq\r
- bxeq r2\r
+ beq z80ReadBusReq\r
\r
and r2, r0, #0xff0000 @ finally it might be\r
cmp r2, #0xa00000 @ z80 area\r
bne m_read8_misc3\r
tst r0, #0x4000\r
- ldreq r2, =z80Read8 @ z80 RAM\r
- bxeq r2\r
+ beq z80Read8 @ z80 RAM\r
and r2, r0, #0x6000\r
cmp r2, #0x4000\r
mvnne r0, #0\r
tst r1, #1\r
beq m_read8_fake_ym2612\r
tst r1, #0x200\r
- ldreq r2, =YM2612Read_\r
- ldrne r2, =YM2612Read_940\r
+ beq YM2612Read_\r
+ b YM2612Read_940\r
.else\r
- ldr r2, =YM2612Read_\r
+ b YM2612Read_\r
.endif\r
- bx r2 @ ym2612\r
\r
m_read8_fake_ym2612:\r
ldr r3, =(Pico+0x22200)\r
orr r0, r0, #0x200000\r
cmp r0, r1\r
bgt m_read16_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg (2ci)\r
- tst r1, #1\r
- beq m_read16_nosram\r
- ldr r1, [r2, #4] @ SRam.start (1ci)\r
+ ldr r1, [r2, #4] @ SRam.start\r
cmp r0, r1\r
blt m_read16_nosram\r
- ldr r2, [r2] @ SRam.data (1ci)\r
- sub r2, r2, r1\r
- ldrh r0, [r2, r0] @ 2ci\r
- and r1, r0, #0xff\r
- mov r0, r0, lsr #8\r
- orr r0, r0, r1, lsl #8\r
- bx lr\r
-\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ beq m_read16_nosram\r
+ stmfd sp!,{lr}\r
+ bl SRAMRead\r
+ orr r0, r0, r0, lsl #8\r
+ ldmfd sp!,{pc}\r
m_read16_nosram:\r
- ldr r1, [r3, #4] @ 1ci\r
+ ldr r1, [r3, #4] @ romsize\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
b OtherRead16\r
\r
m_read16_vdp:\r
- tst r0, #0x70000\r
+ tst r0, #0x70000 @ if ((a&0xe700e0)==0xc00000)\r
tsteq r0, #0x000e0\r
bxne lr @ invalid read\r
bic r0, r0, #1\r
orr r0, r0, #0x200000\r
cmp r0, r1\r
bgt m_read32_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg (2ci)\r
- tst r1, #1\r
- beq m_read32_nosram\r
- ldr r1, [r2, #4] @ SRam.start (1ci)\r
+ ldr r1, [r2, #4] @ SRam.start\r
cmp r0, r1\r
blt m_read32_nosram\r
- ldr r2, [r2] @ SRam.data (1ci)\r
- sub r2, r2, r1\r
- ldrh r0, [r2, r0]! @ (1ci)\r
- ldrh r1, [r2, #2]\r
- orr r0, r0, r0, lsl #16\r
- mov r0, r0, ror #8\r
- mov r0, r0, lsl #16\r
- orr r0, r0, r1, lsr #8\r
- and r1, r1, #0xff\r
- orr r0, r0, r1, lsl #8\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ beq m_read32_nosram\r
+ stmfd sp!,{r0,lr}\r
+ bl SRAMRead\r
+ ldmfd sp!,{r1,lr}\r
+ stmfd sp!,{r0,lr}\r
+ add r0, r1, #2\r
+ bl SRAMRead\r
+ ldmfd sp!,{r1,lr}\r
+ orr r0, r1, r0, lsl #16\r
+ orr r0, r0, r0, lsl #8\r
bx lr\r
-\r
m_read32_nosram:\r
- ldr r1, [r3, #4] @ (1ci)\r
+ ldr r1, [r3, #4] @ romsize\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
m_write8_not_z80:\r
and r2, r0, #0xe70000\r
cmp r2, #0xc00000 @ VDP area?\r
- bne m_write8_misc4\r
+ bne OtherWrite8 @ passthrough\r
and r2, r0, #0xf9\r
cmp r2, #0x11\r
- bne m_write8_misc4\r
+ bne OtherWrite8\r
m_write8_psg:\r
ldr r2, =PicoOpt\r
mov r0, r1\r
ldr r2, [r2]\r
tst r2, #2\r
bxeq lr\r
- ldr r2, =SN76496Write\r
- bx r2\r
- \r
-\r
-m_write8_misc4:\r
- @ passthrough\r
- ldr r2, =OtherWrite8\r
- bx r2\r
+ b SN76496Write\r
\r