/*
+ * Basic macros to emit x86 instructions and some utils
+ * Copyright (C) 2008,2009,2010 notaz
+ *
+ * This work is licensed under the terms of MAME license.
+ * See COPYING file in the top-level directory.
+ *
* note:
- * temp registers must be eax-edx due to use of SETcc.
+ * temp registers must be eax-edx due to use of SETcc and r/w 8/16.
* note about silly things like emith_eor_r_r_r:
* these are here because the compiler was designed
* for ARM as it's primary target.
#define EMIT_SIB(scale,index,base) \
EMIT(((scale)<<6) | ((index)<<3) | (base), u8)
-#define EMIT_OP_MODRM(op,mod,r,rm) { \
+#define EMIT_OP_MODRM(op,mod,r,rm) do { \
EMIT_OP(op); \
EMIT_MODRM(mod, r, rm); \
-}
+} while (0)
#define JMP8_POS(ptr) \
ptr = tcache_ptr; \
}
// _r_r_r
+#define emith_add_r_r_r(d, s1, s2) { \
+ if (d == s1) { \
+ emith_add_r_r(d, s2); \
+ } else if (d == s2) { \
+ emith_add_r_r(d, s1); \
+ } else { \
+ emith_move_r_r(d, s1); \
+ emith_add_r_r(d, s2); \
+ } \
+}
+
#define emith_eor_r_r_r(d, s1, s2) { \
if (d == s1) { \
emith_eor_r_r(d, s2); \
EMIT(imm, u32); \
} while (0)
-// 2 - adc, 3 - sbb
#define emith_add_r_imm(r, imm) \
emith_arith_r_imm(0, r, imm)
#define emith_or_r_imm(r, imm) \
emith_arith_r_imm(1, r, imm)
+#define emith_adc_r_imm(r, imm) \
+ emith_arith_r_imm(2, r, imm)
+
+#define emith_sbc_r_imm(r, imm) \
+ emith_arith_r_imm(3, r, imm) // sbb
+
#define emith_and_r_imm(r, imm) \
emith_arith_r_imm(4, r, imm)
emith_add_r_imm(r, imm); \
}
-#define emith_or_r_imm_c(cond, r, imm) { \
- (void)(cond); \
- emith_or_r_imm(r, imm); \
-}
-
-#define emith_eor_r_imm_c(cond, r, imm) { \
- (void)(cond); \
- emith_eor_r_imm(r, imm); \
-}
-
#define emith_sub_r_imm_c(cond, r, imm) { \
(void)(cond); \
emith_sub_r_imm(r, imm); \
}
-#define emith_bic_r_imm_c(cond, r, imm) { \
- (void)(cond); \
- emith_bic_r_imm(r, imm); \
-}
-
-#define emith_jump_reg_c(cond, r) emith_jump_reg(r)
-#define emith_jump_ctx_c(cond, offs) emith_jump_ctx(offs)
-#define emith_ret_c(cond) emith_ret()
+#define emith_or_r_imm_c(cond, r, imm) \
+ emith_or_r_imm(r, imm)
+#define emith_eor_r_imm_c(cond, r, imm) \
+ emith_eor_r_imm(r, imm)
+#define emith_bic_r_imm_c(cond, r, imm) \
+ emith_bic_r_imm(r, imm)
+#define emith_ror_c(cond, d, s, cnt) \
+ emith_ror(d, s, cnt)
+
+#define emith_read_r_r_offs_c(cond, r, rs, offs) \
+ emith_read_r_r_offs(r, rs, offs)
+#define emith_write_r_r_offs_c(cond, r, rs, offs) \
+ emith_write_r_r_offs(r, rs, offs)
+#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
+ emith_read8_r_r_offs(r, rs, offs)
+#define emith_write8_r_r_offs_c(cond, r, rs, offs) \
+ emith_write8_r_r_offs(r, rs, offs)
+#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
+ emith_read16_r_r_offs(r, rs, offs)
+#define emith_write16_r_r_offs_c(cond, r, rs, offs) \
+ emith_write16_r_r_offs(r, rs, offs)
+#define emith_jump_reg_c(cond, r) \
+ emith_jump_reg(r)
+#define emith_jump_ctx_c(cond, offs) \
+ emith_jump_ctx(offs)
+#define emith_ret_c(cond) \
+ emith_ret()
// _r_r_imm
#define emith_add_r_r_imm(d, s, imm) { \
#define emith_rolcf emith_rolc
#define emith_rorcf emith_rorc
-#define emith_ctx_op(op, r, offs) do { \
+#define emith_deref_op(op, r, rs, offs) do { \
/* mov r <-> [ebp+#offs] */ \
if ((offs) >= 0x80) { \
- EMIT_OP_MODRM(op, 2, r, xBP); \
+ EMIT_OP_MODRM(op, 2, r, rs); \
EMIT(offs, u32); \
} else { \
- EMIT_OP_MODRM(op, 1, r, xBP); \
+ EMIT_OP_MODRM(op, 1, r, rs); \
EMIT(offs, u8); \
} \
} while (0)
+#define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
+
+#define emith_read_r_r_offs(r, rs, offs) \
+ emith_deref_op(0x8b, r, rs, offs)
+
+#define emith_write_r_r_offs(r, rs, offs) \
+ emith_deref_op(0x89, r, rs, offs)
+
+// note: don't use prefixes on this
+#define emith_read8_r_r_offs(r, rs, offs) do { \
+ int r_ = r; \
+ if (!is_abcdx(r)) \
+ r_ = rcache_get_tmp(); \
+ emith_deref_op(0x8a, r_, rs, offs); \
+ if ((r) != r_) { \
+ emith_move_r_r(r, r_); \
+ rcache_free_tmp(r_); \
+ } \
+} while (0)
+
+#define emith_write8_r_r_offs(r, rs, offs) do {\
+ int r_ = r; \
+ if (!is_abcdx(r)) { \
+ r_ = rcache_get_tmp(); \
+ emith_move_r_r(r_, r); \
+ } \
+ emith_deref_op(0x88, r_, rs, offs); \
+ if ((r) != r_) \
+ rcache_free_tmp(r_); \
+} while (0)
+
+#define emith_read16_r_r_offs(r, rs, offs) { \
+ EMIT(0x66, u8); /* operand override */ \
+ emith_read_r_r_offs(r, rs, offs); \
+}
+
+#define emith_write16_r_r_offs(r, rs, offs) { \
+ EMIT(0x66, u8); \
+ emith_write_r_r_offs(r, rs, offs); \
+}
+
#define emith_ctx_read(r, offs) \
- emith_ctx_op(0x8b, r, offs)
+ emith_read_r_r_offs(r, CONTEXT_REG, offs)
#define emith_ctx_write(r, offs) \
- emith_ctx_op(0x89, r, offs)
+ emith_write_r_r_offs(r, CONTEXT_REG, offs)
#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
int r_ = r, offs_ = offs, cnt_ = cnt; \
EMIT(disp, u32); \
}
+#define emith_jump_patchable(target) \
+ emith_jump(target)
+
#define emith_jump_cond(cond, ptr) { \
u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
EMIT(0x0f, u8); \
EMIT(disp, u32); \
}
-#define emith_jump_patchable(cond) \
- emith_jump_cond(cond, 0)
+#define emith_jump_cond_patchable(cond, target) \
+ emith_jump_cond(cond, target)
#define emith_jump_patch(ptr, target) do { \
- u32 disp = (u32)(target) - ((u32)(ptr) + 6); \
- EMIT_PTR((u8 *)(ptr) + 2, disp, u32); \
+ u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
+ u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
+ EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
} while (0)
+#define emith_jump_at(ptr, target) { \
+ u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
+ EMIT_PTR(ptr, 0xe9, u8); \
+ EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
+}
+
#define emith_call(ptr) { \
u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
EMIT_OP(0xe8); \
EMIT_OP_MODRM(0xff, 3, 2, r)
#define emith_call_ctx(offs) { \
- EMIT_OP_MODRM(0xff, 2, 2, xBP); \
+ EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
EMIT(offs, u32); \
}
EMIT_OP_MODRM(0xff, 3, 4, r)
#define emith_jump_ctx(offs) { \
- EMIT_OP_MODRM(0xff, 2, 4, xBP); \
+ EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
EMIT(offs, u32); \
}
+#define emith_push_ret()
+
+#define emith_pop_and_ret() \
+ emith_ret()
+
#define EMITH_JMP_START(cond) { \
u8 *cond_ptr; \
JMP8_POS(cond_ptr)
JMP8_EMIT(cond, cond_ptr); \
}
+#define EMITH_JMP3_START(cond) { \
+ u8 *cond_ptr, *else_ptr; \
+ JMP8_POS(cond_ptr)
+
+#define EMITH_JMP3_MID(cond) \
+ JMP8_POS(else_ptr); \
+ JMP8_EMIT(cond, cond_ptr);
+
+#define EMITH_JMP3_END() \
+ JMP8_EMIT_NC(else_ptr); \
+}
+
// "simple" jump (no more then a few insns)
+// ARM will use conditional instructions here
#define EMITH_SJMP_START EMITH_JMP_START
#define EMITH_SJMP_END EMITH_JMP_END
-#define host_arg2reg(rd, arg) \
- switch (arg) { \
- case 0: rd = xAX; break; \
- case 1: rd = xDX; break; \
- case 2: rd = xCX; break; \
- }
+#define EMITH_SJMP3_START EMITH_JMP3_START
+#define EMITH_SJMP3_MID EMITH_JMP3_MID
+#define EMITH_SJMP3_END EMITH_JMP3_END
#define emith_pass_arg_r(arg, reg) { \
int rd = 7; \
emith_move_r_imm(rd, imm); \
}
+#define host_instructions_updated(base, end)
+
+#define host_arg2reg(rd, arg) \
+ switch (arg) { \
+ case 0: rd = xAX; break; \
+ case 1: rd = xDX; break; \
+ case 2: rd = xCX; break; \
+ }
+
/* SH2 drc specific */
#define emith_sh2_drc_entry() { \
emith_push(xBX); \
}
// assumes EBX is free temporary
-#define emith_sh2_wcall(a, tab, ret_ptr) { \
+#define emith_sh2_wcall(a, tab) { \
int arg2_; \
host_arg2reg(arg2_, 2); \
emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
- emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
- emith_push_imm((long)(ret_ptr)); \
+ emith_move_r_r(arg2_, CONTEXT_REG); \
emith_jump_reg(xBX); \
}