// reg cache must be clean before call
static int emit_memhandler_read_(int size, int ram_check)
{
- int arg0, arg1;
+ int arg1;
+#if 0
+ int arg0;
host_arg2reg(arg0, 0);
+#endif
rcache_clean();
1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
}
-int sh2_execute(SH2 *sh2c, int cycles)
+int sh2_execute_drc(SH2 *sh2c, int cycles)
{
int ret_cycles;
- sh2c->cycles_timeslice = cycles;
-
// cycles are kept in SHR_SR unused bits (upper 20)
// bit11 contains T saved for delay slot
// others are usual SH2 flags
dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
sh2c->sr &= 0x3f3;
- return sh2c->cycles_timeslice - ret_cycles;
+ return ret_cycles;
}
#if (DRC_DEBUG & 2)
void sh2_drc_mem_setup(SH2 *sh2)
{
// fill the convenience pointers
- sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
+ sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
sh2->p_da = sh2->data_array;
sh2->p_sdram = Pico32xMem->sdram;
sh2->p_rom = Pico.rom;
if ((pc & ~0x7ff) == 0) {
// BIOS
- ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
+ ret = is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
mask = 0x7ff;
}
else if ((pc & 0xfffff000) == 0xc0000000) {