void *p_rom;\r
unsigned int pdb_io_csum[2];\r
\r
+#define SH2_STATE_RUN (1 << 0) // to prevent recursion\r
+#define SH2_STATE_SLEEP (1 << 1)\r
+#define SH2_STATE_CPOLL (1 << 2) // polling comm regs\r
+#define SH2_STATE_VPOLL (1 << 3) // polling VDP\r
+ unsigned int state;\r
+ unsigned int poll_addr;\r
+ int poll_cycles;\r
+ int poll_cnt;\r
+\r
// interpreter stuff\r
int icount; // cycles left in current timeslice\r
unsigned int ea;\r
int REGPARM(2) (*irq_callback)(struct SH2_ *sh2, int level);\r
int is_slave;\r
\r
- unsigned int cycles_aim; // subtract sh2_icount to get global counter\r
- unsigned int cycles_done;\r
+ unsigned int cycles_timeslice;\r
+\r
+ struct SH2_ *other_sh2;\r
+\r
+ // we use 68k reference cycles for easier sync\r
+ unsigned int m68krcycles_done;\r
+ unsigned int mult_m68k_to_sh2;\r
+ unsigned int mult_sh2_to_m68k;\r
+\r
+ unsigned char data_array[0x1000]; // cache (can be used as RAM)\r
+ unsigned int peri_regs[0x200/4]; // periphereal regs\r
} SH2;\r
\r
-extern SH2 *sh2; // active sh2. XXX: consider removing\r
+#define CYCLE_MULT_SHIFT 10\r
+#define C_M68K_TO_SH2(xsh2, c) \\r
+ ((int)((c) * (xsh2).mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)\r
+#define C_SH2_TO_M68K(xsh2, c) \\r
+ ((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r
\r
-int sh2_init(SH2 *sh2, int is_slave);\r
+int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
-void sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
+int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
void sh2_do_irq(SH2 *sh2, int level, int vector);\r
void sh2_pack(const SH2 *sh2, unsigned char *buff);\r
void sh2_unpack(SH2 *sh2, const unsigned char *buff);\r
\r
-void sh2_execute(SH2 *sh2, int cycles);\r
+int sh2_execute_drc(SH2 *sh2c, int cycles);\r
+int sh2_execute_interpreter(SH2 *sh2c, int cycles);\r
+\r
+static INLINE int sh2_execute(SH2 *sh2, int cycles, int use_drc)\r
+{\r
+ int ret;\r
+\r
+ sh2->cycles_timeslice = cycles;\r
+#ifdef DRC_SH2\r
+ if (use_drc)\r
+ ret = sh2_execute_drc(sh2, cycles);\r
+ else\r
+#endif\r
+ ret = sh2_execute_interpreter(sh2, cycles);\r
+\r
+ return sh2->cycles_timeslice - ret;\r
+}\r
\r
// regs, pending_int*, cycles, reserved\r
#define SH2_STATE_SIZE ((24 + 2 + 2 + 12) * 4)\r
unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
-int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
-int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
-int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+\r
+// debug\r
+#ifdef DRC_CMP\r
+void do_sh2_trace(SH2 *current, int cycles);\r
+void do_sh2_cmp(SH2 *current);\r
+#endif\r
\r
#endif /* __SH2_H__ */\r