typedef unsigned char UINT8;
// pico memhandlers
-unsigned int p32x_sh2_read8(unsigned int a);
-unsigned int p32x_sh2_read16(unsigned int a);
-unsigned int p32x_sh2_read32(unsigned int a);
-void p32x_sh2_write8(unsigned int a, unsigned int d);
-void p32x_sh2_write16(unsigned int a, unsigned int d);
-void p32x_sh2_write32(unsigned int a, unsigned int d);
-
-#define RB p32x_sh2_read8
-#define RW p32x_sh2_read16
-#define RL p32x_sh2_read32
-#define WB p32x_sh2_write8
-#define WW p32x_sh2_write16
-#define WL p32x_sh2_write32
+unsigned int p32x_sh2_read8(unsigned int a, int id);
+unsigned int p32x_sh2_read16(unsigned int a, int id);
+unsigned int p32x_sh2_read32(unsigned int a, int id);
+void p32x_sh2_write8(unsigned int a, unsigned int d, int id);
+void p32x_sh2_write16(unsigned int a, unsigned int d, int id);
+void p32x_sh2_write32(unsigned int a, unsigned int d, int id);
+
+#define RB(a) p32x_sh2_read8(a,sh2->is_slave)
+#define RW(a) p32x_sh2_read16(a,sh2->is_slave)
+#define RL(a) p32x_sh2_read32(a,sh2->is_slave)
+#define WB(a,d) p32x_sh2_write8(a,d,sh2->is_slave)
+#define WW(a,d) p32x_sh2_write16(a,d,sh2->is_slave)
+#define WL(a,d) p32x_sh2_write32(a,d,sh2->is_slave)
// some stuff from sh2comn.h
#define T 0x00000001
sh2->pc = RL(0);
sh2->r[15] = RL(4);
sh2->sr = I;
+}
+
+static void sh2_do_irq(SH2 *sh2, int level, int vector)
+{
+ sh2->irq_callback(sh2->is_slave, level);
+
+ sh2->r[15] -= 4;
+ WL(sh2->r[15], sh2->sr); /* push SR onto stack */
+ sh2->r[15] -= 4;
+ WL(sh2->r[15], sh2->pc); /* push PC onto stack */
+
+ /* set I flags in SR */
+ sh2->sr = (sh2->sr & ~I) | (level << 4);
+
+ /* fetch PC */
+ sh2->pc = RL(sh2->vbr + vector * 4);
- sh2->internal_irq_level = -1;
+ /* 13 cycles at best */
+ sh2_icount -= 13;
}
/* Execute cycles - returns number of cycles actually run */
{
sh2 = sh2_;
sh2_icount = cycles;
+ sh2->cycles_aim += cycles;
do
{
if (sh2->delay)
{
+ sh2->ppc = sh2->delay;
opcode = RW(sh2->delay);
sh2->pc -= 2;
}
else
+ {
+ sh2->ppc = sh2->pc;
opcode = RW(sh2->pc);
+ }
sh2->delay = 0;
sh2->pc += 2;
- sh2->ppc = sh2->pc;
switch (opcode & ( 15 << 12))
{
if (sh2->test_irq && !sh2->delay)
{
- if (sh2->pending_irq)
- sh2_irl_irq(sh2, sh2->pending_irq);
+ if (sh2->pending_irl > sh2->pending_int_irq)
+ sh2_irl_irq(sh2, sh2->pending_irl);
+ else
+ sh2_internal_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
sh2->test_irq = 0;
}
sh2_icount--;
}
- while (sh2_icount > 0);
+ while (sh2_icount > 0 || sh2->delay); /* can't interrupt before delay */
return cycles - sh2_icount;
}
-void sh2_init(SH2 *sh2)
+void sh2_init(SH2 *sh2, int is_slave)
{
memset(sh2, 0, sizeof(*sh2));
+ sh2->is_slave = is_slave;
}
void sh2_irl_irq(SH2 *sh2, int level)
{
- int vector;
-
- sh2->pending_irq = level;
-
+ sh2->pending_irl = level;
if (level <= ((sh2->sr >> 4) & 0x0f))
- /* masked */
return;
- sh2->irq_callback(level);
- vector = 64 + level/2;
-
- sh2->r[15] -= 4;
- WL(sh2->r[15], sh2->sr); /* push SR onto stack */
- sh2->r[15] -= 4;
- WL(sh2->r[15], sh2->pc); /* push PC onto stack */
-
- /* set I flags in SR */
- sh2->sr = (sh2->sr & ~I) | (level << 4);
+ sh2_do_irq(sh2, level, 64 + level/2);
+}
- /* fetch PC */
- sh2->pc = RL(sh2->vbr + vector * 4);
+void sh2_internal_irq(SH2 *sh2, int level, int vector)
+{
+ sh2->pending_int_irq = level;
+ sh2->pending_int_vector = vector;
+ if (level <= ((sh2->sr >> 4) & 0x0f))
+ return;
- /* 13 cycles at best */
- sh2_icount -= 13;
+ sh2_do_irq(sh2, level, vector);
+ sh2->pending_int_irq = 0; // auto-clear
}