}
}
}
- printf("This shouldn't happen (alloc_reg)");exit(1);
+ SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
}
void alloc_reg64(struct regstat *cur,int i,signed char reg)
}
}
}
- printf("This shouldn't happen");exit(1);
+ SysPrintf("This shouldn't happen");exit(1);
}
// Allocate a temporary register. This is done without regard to
}
}
}
- printf("This shouldn't happen");exit(1);
+ SysPrintf("This shouldn't happen");exit(1);
}
// Allocate a specific ARM register.
void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
int offset=addr-(int)out-8;
if(offset<-33554432||offset>=33554432) {
if (addr>2) {
- printf("genjmp: out of range: %08x\n", offset);
+ SysPrintf("genjmp: out of range: %08x\n", offset);
exit(1);
}
return 0;
{
#ifdef FORCE32
if(r&64) {
- printf("64bit load in 32bit mode!\n");
+ SysPrintf("64bit load in 32bit mode!\n");
assert(0);
return;
}
{
#ifdef FORCE32
if(r&64) {
- printf("64bit store in 32bit mode!\n");
+ SysPrintf("64bit store in 32bit mode!\n");
assert(0);
return;
}
emit_writeword(rt,(int)&dword);
emit_writeword(r?rth:rt,(int)&dword+4);
#else
- printf("STORED_STUB\n");
+ SysPrintf("STORED_STUB\n");
#endif
}
//emit_pusha();
emit_writeword(rt,(int)&dword);
emit_writeword(target?rth:rt,(int)&dword+4);
#else
- printf("STORED_STUB\n");
+ SysPrintf("STORED_STUB\n");
#endif
}
//emit_pusha();
#else
-static int do_tlb_r() { return 0; }
-static int do_tlb_r_branch() { return 0; }
-static int gen_tlb_addr_r() { return 0; }
-static int do_tlb_w() { return 0; }
-static int do_tlb_w_branch() { return 0; }
-static int gen_tlb_addr_w() { return 0; }
+static int do_tlb_r(int a, ...) { return 0; }
+static int do_tlb_r_branch(int a, ...) { return 0; }
+static int gen_tlb_addr_r(int a, ...) { return 0; }
+static int do_tlb_w(int a, ...) { return 0; }
+static int do_tlb_w_branch(int a, ...) { return 0; }
+static int gen_tlb_addr_w(int a, ...) { return 0; }
#endif // DISABLE_TLB
int lm = (source[i] >> 10) & 1;
switch(c2op) {
#ifndef DRC_DBG
-#ifdef HAVE_ARMV5
case GTE_MVMVA: {
+#ifdef HAVE_ARMV5
int v = (source[i] >> 15) & 3;
int cv = (source[i] >> 13) & 3;
int mx = (source[i] >> 17) & 3;
}
if(need_flags||need_ir)
c2op_call_MACtoIR(lm,need_flags);
+#endif
+#else /* if not HAVE_ARMV5 */
+ c2op_prologue(c2op,reglist);
+ emit_movimm(source[i],1); // opcode
+ emit_writeword(1,(int)&psxRegs.code);
+ emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
#endif
break;
}
-#endif /* HAVE_ARMV5 */
case GTE_OP:
c2op_prologue(c2op,reglist);
emit_call((int)(shift?gteOP_part_shift:gteOP_part_noshift));
emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
emit_movs(d2,HOST_TEMPREG);
emit_jeq((int)out+52); // Division by zero
- emit_negmi(HOST_TEMPREG,HOST_TEMPREG);
+ emit_negsmi(HOST_TEMPREG,HOST_TEMPREG);
#ifdef HAVE_ARMV5
emit_clz(HOST_TEMPREG,quotient);
emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
emit_shl(d2,HOST_TEMPREG,d2);
#else
emit_movimm(0,HOST_TEMPREG);
- emit_addpl_imm(d2,1,d2);
- emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
+ emit_addpl_imm(HOST_TEMPREG,1,HOST_TEMPREG);
+ emit_lslpls_imm(d2,1,d2);
emit_jns((int)out-2*4);
emit_movimm(1<<31,quotient);
#endif