evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
MTC0(reg, val);
gen_interupt();
+ if (Cause & Status & 0x0300) // possible sw irq
+ pending_exception = 1;
}
void pcsx_mtc0_ds(u32 reg, u32 val)
[GTE_OP] = GCBITS3(0,2,4) | GDBITS3(9,10,11),
[GTE_DPCS] = GCBITS3(21,22,23) | GDBITS4(6,8,21,22),
[GTE_INTPL] = GCBITS3(21,22,23) | GDBITS7(6,8,9,10,11,21,22),
- [GTE_MVMVA] = 0x00ffffff00000000ll | GDBITS6(0,1,2,3,4,5), // XXX: maybe decode further?
- [GTE_NCDS] = 0x00ffff0000000000ll | GDBITS5(0,1,6,21,22),
- [GTE_CDP] = 0x00fff00000000000ll | GDBITS7(6,8,9,10,11,21,22),
+ [GTE_MVMVA] = 0x00ffffff00000000ll | GDBITS9(0,1,2,3,4,5,9,10,11), // XXX: maybe decode further?
+ [GTE_NCDS] = 0x00ffff0000000000ll | GDBITS6(0,1,6,8,21,22),
+ [GTE_CDP] = 0x00ffe00000000000ll | GDBITS7(6,8,9,10,11,21,22),
[GTE_NCDT] = 0x00ffff0000000000ll | GDBITS8(0,1,2,3,4,5,6,8),
- [GTE_NCCS] = 0x00ffff0000000000ll | GDBITS6(0,1,6,8,21,22),
+ [GTE_NCCS] = 0x001fff0000000000ll | GDBITS5(0,1,6,21,22),
[GTE_CC] = 0x001fe00000000000ll | GDBITS6(6,9,10,11,21,22),
- [GTE_NCS] = 0x001fff0000000000ll | GDBITS4(0,1,21,22),
+ [GTE_NCS] = 0x001fff0000000000ll | GDBITS5(0,1,6,21,22),
[GTE_NCT] = 0x001fff0000000000ll | GDBITS7(0,1,2,3,4,5,6),
[GTE_SQR] = GDBITS3(9,10,11),
[GTE_DCPL] = GCBITS3(21,22,23) | GDBITS7(6,8,9,10,11,21,22),
pending_exception = 1;
}
+#ifdef __arm__
// execute until predefined leave points
// (HLE softcall exit and BIOS fastboot end)
static void ari64_execute_until()
evprintf("drc left @%08x\n", psxRegs.pc);
}
}
+#endif
static void ari64_clear(u32 addr, u32 size)
{