#define evprintf(...)
char invalid_code[0x100000];
+static u32 scratch_buf[8*8*2] __attribute__((aligned(64)));
u32 event_cycles[PSXINT_COUNT];
static void schedule_timeslice(void)
{
extern void (*psxCP2[64])();
extern void psxNULL();
+ extern u_char *out;
size_t i;
new_dynarec_init();
if (psxCP2[i] != psxNULL)
gte_handlers[i] = psxCP2[i];
-#if !defined(DRC_DBG)
-#ifdef __arm__
+#if defined(__arm__) && !defined(DRC_DBG)
gte_handlers[0x06] = gteNCLIP_arm;
+#ifdef HAVE_ARMV5
gte_handlers_nf[0x01] = gteRTPS_nf_arm;
gte_handlers_nf[0x30] = gteRTPT_nf_arm;
#endif
#endif
psxH_ptr = psxH;
zeromem_ptr = zero_mem;
+ scratch_buf_ptr = scratch_buf;
+
+ SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
+ SysPrintf("%08x/%08x/%08x/%08x/%08x\n",
+ psxM, psxH, psxR, mem_rtab, out);
return 0;
}
static void ari64_shutdown()
{
new_dynarec_cleanup();
+ new_dyna_pcsx_mem_shutdown();
}
extern void intExecute();
R3000Acpu psxRec = {
ari64_init,
ari64_reset,
-#if defined(__arm__)
+#ifndef DRC_DISABLE
ari64_execute,
ari64_execute_until,
#else
void do_insn_cmp() {}
#endif
-#if defined(__x86_64__) || defined(__i386__)
+#ifdef DRC_DISABLE
unsigned int address;
int pending_exception, stop;
unsigned int next_interupt;
void *psxH_ptr;
void *zeromem_ptr;
u8 zero_mem[0x1000];
-void new_dynarec_init() {}
+u_char *out;
+void *mem_rtab;
+void *scratch_buf_ptr;
+void new_dynarec_init() { (void)ari64_execute; }
void new_dyna_start() {}
void new_dynarec_cleanup() {}
void new_dynarec_clear_full() {}
void new_dyna_pcsx_mem_init(void) {}
void new_dyna_pcsx_mem_reset(void) {}
void new_dyna_pcsx_mem_load_state(void) {}
+void new_dyna_pcsx_mem_shutdown(void) {}
#endif
#ifdef DRC_DBG